ns16550.h 8.4 KB

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  1. /*
  2. * NS16550 Serial Port
  3. * originally from linux source (arch/powerpc/boot/ns16550.h)
  4. *
  5. * Cleanup and unification
  6. * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
  7. *
  8. * modified slightly to
  9. * have addresses as offsets from CONFIG_SYS_ISA_BASE
  10. * added a few more definitions
  11. * added prototypes for ns16550.c
  12. * reduced no of com ports to 2
  13. * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
  14. *
  15. * added support for port on 64-bit bus
  16. * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
  17. */
  18. /*
  19. * Note that the following macro magic uses the fact that the compiler
  20. * will not allocate storage for arrays of size 0
  21. */
  22. #ifndef __ns16550_h
  23. #define __ns16550_h
  24. #include <linux/types.h>
  25. #ifdef CONFIG_DM_SERIAL
  26. /*
  27. * For driver model we always use one byte per register, and sort out the
  28. * differences in the driver
  29. */
  30. #define CONFIG_SYS_NS16550_REG_SIZE (-1)
  31. #endif
  32. #ifdef CONFIG_NS16550_DYNAMIC
  33. #define UART_REG(x) unsigned char x
  34. #else
  35. #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
  36. #error "Please define NS16550 registers size."
  37. #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
  38. #define UART_REG(x) u32 x
  39. #elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
  40. #define UART_REG(x) \
  41. unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
  42. unsigned char x;
  43. #elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
  44. #define UART_REG(x) \
  45. unsigned char x; \
  46. unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
  47. #endif
  48. #endif /* CONFIG_NS16550_DYNAMIC */
  49. enum ns16550_flags {
  50. NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */
  51. NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */
  52. NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */
  53. };
  54. /**
  55. * struct ns16550_plat - information about a NS16550 port
  56. *
  57. * @base: Base register address
  58. * @reg_width: IO accesses size of registers (in bytes, 1 or 4)
  59. * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
  60. * @reg_offset: Offset to start of registers (normally 0)
  61. * @clock: UART base clock speed in Hz
  62. * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL)
  63. * @flags: A few flags (enum ns16550_flags)
  64. * @bdf: PCI slot/function (pci_dev_t)
  65. */
  66. struct ns16550_plat {
  67. unsigned long base;
  68. int reg_width;
  69. int reg_shift;
  70. int reg_offset;
  71. int clock;
  72. u32 fcr;
  73. int flags;
  74. #if defined(CONFIG_PCI) && defined(CONFIG_SPL)
  75. int bdf;
  76. #endif
  77. };
  78. struct udevice;
  79. struct ns16550 {
  80. UART_REG(rbr); /* 0 */
  81. UART_REG(ier); /* 1 */
  82. UART_REG(fcr); /* 2 */
  83. UART_REG(lcr); /* 3 */
  84. UART_REG(mcr); /* 4 */
  85. UART_REG(lsr); /* 5 */
  86. UART_REG(msr); /* 6 */
  87. UART_REG(spr); /* 7 */
  88. #ifdef CONFIG_SOC_DA8XX
  89. UART_REG(reg8); /* 8 */
  90. UART_REG(reg9); /* 9 */
  91. UART_REG(revid1); /* A */
  92. UART_REG(revid2); /* B */
  93. UART_REG(pwr_mgmt); /* C */
  94. UART_REG(mdr1); /* D */
  95. #else
  96. UART_REG(mdr1); /* 8 */
  97. UART_REG(reg9); /* 9 */
  98. UART_REG(regA); /* A */
  99. UART_REG(regB); /* B */
  100. UART_REG(regC); /* C */
  101. UART_REG(regD); /* D */
  102. UART_REG(regE); /* E */
  103. UART_REG(uasr); /* F */
  104. UART_REG(scr); /* 10*/
  105. UART_REG(ssr); /* 11*/
  106. #endif
  107. #ifdef CONFIG_DM_SERIAL
  108. struct ns16550_plat *plat;
  109. #endif
  110. };
  111. #define thr rbr
  112. #define iir fcr
  113. #define dll rbr
  114. #define dlm ier
  115. /*
  116. * These are the definitions for the FIFO Control Register
  117. */
  118. #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
  119. #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
  120. #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
  121. #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
  122. #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
  123. #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
  124. #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
  125. #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
  126. #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
  127. #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
  128. #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
  129. /* Ingenic JZ47xx specific UART-enable bit. */
  130. #define UART_FCR_UME 0x10
  131. /* Clear & enable FIFOs */
  132. #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
  133. UART_FCR_RXSR | \
  134. UART_FCR_TXSR)
  135. /*
  136. * These are the definitions for the Modem Control Register
  137. */
  138. #define UART_MCR_DTR 0x01 /* DTR */
  139. #define UART_MCR_RTS 0x02 /* RTS */
  140. #define UART_MCR_OUT1 0x04 /* Out 1 */
  141. #define UART_MCR_OUT2 0x08 /* Out 2 */
  142. #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
  143. #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
  144. #define UART_MCR_DMA_EN 0x04
  145. #define UART_MCR_TX_DFR 0x08
  146. /*
  147. * These are the definitions for the Line Control Register
  148. *
  149. * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
  150. * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  151. */
  152. #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
  153. #define UART_LCR_WLS_5 0x00 /* 5 bit character length */
  154. #define UART_LCR_WLS_6 0x01 /* 6 bit character length */
  155. #define UART_LCR_WLS_7 0x02 /* 7 bit character length */
  156. #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
  157. #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
  158. #define UART_LCR_PEN 0x08 /* Parity eneble */
  159. #define UART_LCR_EPS 0x10 /* Even Parity Select */
  160. #define UART_LCR_STKP 0x20 /* Stick Parity */
  161. #define UART_LCR_SBRK 0x40 /* Set Break */
  162. #define UART_LCR_BKSE 0x80 /* Bank select enable */
  163. #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
  164. /*
  165. * These are the definitions for the Line Status Register
  166. */
  167. #define UART_LSR_DR 0x01 /* Data ready */
  168. #define UART_LSR_OE 0x02 /* Overrun */
  169. #define UART_LSR_PE 0x04 /* Parity error */
  170. #define UART_LSR_FE 0x08 /* Framing error */
  171. #define UART_LSR_BI 0x10 /* Break */
  172. #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
  173. #define UART_LSR_TEMT 0x40 /* Xmitter empty */
  174. #define UART_LSR_ERR 0x80 /* Error */
  175. #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
  176. #define UART_MSR_RI 0x40 /* Ring Indicator */
  177. #define UART_MSR_DSR 0x20 /* Data Set Ready */
  178. #define UART_MSR_CTS 0x10 /* Clear to Send */
  179. #define UART_MSR_DDCD 0x08 /* Delta DCD */
  180. #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
  181. #define UART_MSR_DDSR 0x02 /* Delta DSR */
  182. #define UART_MSR_DCTS 0x01 /* Delta CTS */
  183. /*
  184. * These are the definitions for the Interrupt Identification Register
  185. */
  186. #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
  187. #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
  188. #define UART_IIR_MSI 0x00 /* Modem status interrupt */
  189. #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
  190. #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
  191. #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
  192. /*
  193. * These are the definitions for the Interrupt Enable Register
  194. */
  195. #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
  196. #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
  197. #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
  198. #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
  199. /* useful defaults for LCR */
  200. #define UART_LCR_8N1 0x03
  201. void ns16550_init(struct ns16550 *com_port, int baud_divisor);
  202. void ns16550_putc(struct ns16550 *com_port, char c);
  203. char ns16550_getc(struct ns16550 *com_port);
  204. int ns16550_tstc(struct ns16550 *com_port);
  205. void ns16550_reinit(struct ns16550 *com_port, int baud_divisor);
  206. /**
  207. * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
  208. *
  209. * Given the UART input clock and required baudrate, calculate the divisor
  210. * that should be used.
  211. *
  212. * @port: UART port
  213. * @clock: UART input clock speed in Hz
  214. * @baudrate: Required baud rate
  215. * @return baud rate divisor that should be used
  216. */
  217. int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate);
  218. /**
  219. * ns16550_serial_of_to_plat() - convert DT to platform data
  220. *
  221. * Decode a device tree node for an ns16550 device. This includes the
  222. * register base address and register shift properties. The caller must set
  223. * up the clock frequency.
  224. *
  225. * @dev: dev to decode platform data for
  226. * @return: 0 if OK, -EINVAL on error
  227. */
  228. int ns16550_serial_of_to_plat(struct udevice *dev);
  229. /**
  230. * ns16550_serial_probe() - probe a serial port
  231. *
  232. * This sets up the serial port ready for use, except for the baud rate
  233. * @return 0, or -ve on error
  234. */
  235. int ns16550_serial_probe(struct udevice *dev);
  236. /**
  237. * struct ns16550_serial_ops - ns16550 serial operations
  238. *
  239. * These should be used by the client driver for the driver's 'ops' member
  240. */
  241. extern const struct dm_serial_ops ns16550_serial_ops;
  242. #endif /* __ns16550_h */