k3-clk.h 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com
  4. * Tero Kristo <t-kristo@ti.com>
  5. */
  6. #ifndef __K3_CLK_H__
  7. #define __K3_CLK_H__
  8. #include <asm/io.h>
  9. #include <linux/bitops.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/types.h>
  12. #include <stdint.h>
  13. struct dev_clk {
  14. int dev_id;
  15. int clk_id;
  16. const char *clk_name;
  17. };
  18. #define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id, \
  19. .clk_id = _clk_id, .clk_name = _clk_name, }
  20. #define CLK_TYPE_MUX 0x01
  21. #define CLK_TYPE_DIV 0x02
  22. #define CLK_TYPE_PLL 0x03
  23. #define CLK_TYPE_HFOSC 0x04
  24. #define CLK_TYPE_POSTDIV 0x05
  25. #define CLK_TYPE_MUX_PLLCTRL 0x06
  26. #define CLK_TYPE_FIXED_RATE 0x07
  27. struct pll_data {
  28. u32 reg;
  29. const char *name;
  30. const char *parent;
  31. u32 flags;
  32. };
  33. struct mux_data {
  34. u32 reg;
  35. const char *name;
  36. const char * const *parents;
  37. int num_parents;
  38. u32 flags;
  39. int shift;
  40. int width;
  41. };
  42. struct div_data {
  43. u32 reg;
  44. const char *name;
  45. const char *parent;
  46. u32 flags;
  47. int shift;
  48. int width;
  49. };
  50. struct hfosc_data {
  51. const char *name;
  52. u32 flags;
  53. };
  54. struct fixed_rate_data {
  55. const char *name;
  56. u64 rate;
  57. u32 flags;
  58. };
  59. struct postdiv_data {
  60. const char *name;
  61. const char *parent;
  62. int width;
  63. u32 flags;
  64. };
  65. struct mux_pllctrl_data {
  66. u32 reg;
  67. const char *name;
  68. const char * const *parents;
  69. int num_parents;
  70. u32 flags;
  71. };
  72. struct clk_data {
  73. int type;
  74. u32 default_freq;
  75. union {
  76. struct pll_data pll;
  77. struct mux_data mux;
  78. struct div_data div;
  79. struct hfosc_data hfosc;
  80. struct postdiv_data postdiv;
  81. struct mux_pllctrl_data mux_pllctrl;
  82. struct fixed_rate_data fixed_rate;
  83. } clk;
  84. };
  85. #define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \
  86. { \
  87. .type = CLK_TYPE_MUX, \
  88. .clk.mux = { .name = _name, .parents = _parents, \
  89. .reg = _reg, \
  90. .num_parents = _num_parents, .shift = _shift, \
  91. .width = _width, .flags = _flags } \
  92. }
  93. #define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags) \
  94. { \
  95. .type = CLK_TYPE_DIV, \
  96. .clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \
  97. }
  98. #define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \
  99. { \
  100. .type = CLK_TYPE_DIV, \
  101. .default_freq = _freq, \
  102. .clk.div = { \
  103. .name = _name, .parent = _parent, \
  104. .reg = _reg, .shift = _shift, \
  105. .width = _width, .flags = _flags } \
  106. }
  107. #define CLK_PLL(_name, _parent, _reg, _flags) \
  108. { \
  109. .type = CLK_TYPE_PLL, \
  110. .clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \
  111. }
  112. #define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq) \
  113. { \
  114. .type = CLK_TYPE_PLL, \
  115. .default_freq = _freq, \
  116. .clk.pll = { .name = _name, .parent = _parent, \
  117. .reg = _reg, .flags = _flags } \
  118. }
  119. #define CLK_HFOSC(_name, _flags) \
  120. { \
  121. .type = CLK_TYPE_HFOSC, \
  122. .clk.hfosc = { .name = _name, .flags = _flags } \
  123. }
  124. #define CLK_FIXED_RATE(_name, _rate, _flags) \
  125. { \
  126. .type = CLK_TYPE_FIXED_RATE, \
  127. .clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \
  128. }
  129. #define CLK_POSTDIV(_name, _parent, _width, _flags) \
  130. { \
  131. .type = CLK_TYPE_POSTDIV, \
  132. .clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \
  133. }
  134. #define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags) \
  135. { \
  136. .type = CLK_TYPE_MUX, \
  137. .clk.mux_pllctrl = { .name = _name, .parents = _parents,\
  138. .num_parents = _num_parents, .flags = _flags } \
  139. }
  140. struct ti_k3_clk_platdata {
  141. const struct clk_data *clk_list;
  142. int clk_list_cnt;
  143. const struct dev_clk *soc_dev_clk_data;
  144. int soc_dev_clk_data_cnt;
  145. };
  146. extern const struct ti_k3_clk_platdata j721e_clk_platdata;
  147. extern const struct ti_k3_clk_platdata j7200_clk_platdata;
  148. struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
  149. void __iomem *reg);
  150. #endif /* __K3_CLK_H__ */