dwc2_udc_otg_regs.h 9.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
  3. *
  4. * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
  5. *
  6. * Registers remapping:
  7. * Lukasz Majewski <l.majewski@samsumg.com>
  8. */
  9. #ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
  10. #define __ASM_ARCH_REGS_USB_OTG_HS_H
  11. /* USB2.0 OTG Controller register */
  12. #include <linux/bitops.h>
  13. struct dwc2_usbotg_phy {
  14. u32 phypwr;
  15. u32 phyclk;
  16. u32 rstcon;
  17. };
  18. /* Device Logical IN Endpoint-Specific Registers */
  19. struct dwc2_dev_in_endp {
  20. u32 diepctl;
  21. u8 res1[4];
  22. u32 diepint;
  23. u8 res2[4];
  24. u32 dieptsiz;
  25. u32 diepdma;
  26. u8 res3[4];
  27. u32 diepdmab;
  28. };
  29. /* Device Logical OUT Endpoint-Specific Registers */
  30. struct dwc2_dev_out_endp {
  31. u32 doepctl;
  32. u8 res1[4];
  33. u32 doepint;
  34. u8 res2[4];
  35. u32 doeptsiz;
  36. u32 doepdma;
  37. u8 res3[4];
  38. u32 doepdmab;
  39. };
  40. struct ep_fifo {
  41. u32 fifo;
  42. u8 res[4092];
  43. };
  44. /* USB2.0 OTG Controller register */
  45. struct dwc2_usbotg_reg {
  46. /* Core Global Registers */
  47. u32 gotgctl; /* OTG Control & Status */
  48. u32 gotgint; /* OTG Interrupt */
  49. u32 gahbcfg; /* Core AHB Configuration */
  50. u32 gusbcfg; /* Core USB Configuration */
  51. u32 grstctl; /* Core Reset */
  52. u32 gintsts; /* Core Interrupt */
  53. u32 gintmsk; /* Core Interrupt Mask */
  54. u32 grxstsr; /* Receive Status Debug Read/Status Read */
  55. u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
  56. u32 grxfsiz; /* Receive FIFO Size */
  57. u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
  58. u8 res0[12];
  59. u32 ggpio; /* 0x038 */
  60. u8 res1[20];
  61. u32 ghwcfg4; /* User HW Config4 */
  62. u8 res2[176];
  63. u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
  64. u8 res3[1728];
  65. /* Device Configuration */
  66. u32 dcfg; /* Device Configuration Register */
  67. u32 dctl; /* Device Control */
  68. u32 dsts; /* Device Status */
  69. u8 res4[4];
  70. u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
  71. u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
  72. u32 daint; /* Device All Endpoints Interrupt */
  73. u32 daintmsk; /* Device All Endpoints Interrupt Mask */
  74. u8 res5[224];
  75. struct dwc2_dev_in_endp in_endp[16];
  76. struct dwc2_dev_out_endp out_endp[16];
  77. u8 res6[768];
  78. struct ep_fifo ep[16];
  79. };
  80. /*===================================================================== */
  81. /*definitions related to CSR setting */
  82. /* DWC2_UDC_OTG_GOTGCTL */
  83. #define B_SESSION_VALID BIT(19)
  84. #define A_SESSION_VALID BIT(18)
  85. #define B_VALOVAL BIT(7)
  86. #define B_VALOEN BIT(6)
  87. #define A_VALOVAL BIT(5)
  88. #define A_VALOEN BIT(4)
  89. #define VB_VALOVAL BIT(3)
  90. #define VB_VALOEN BIT(2)
  91. /* DWC2_UDC_OTG_GOTINT */
  92. #define GOTGINT_SES_END_DET (1<<2)
  93. /* DWC2_UDC_OTG_GAHBCFG */
  94. #define PTXFE_HALF (0<<8)
  95. #define PTXFE_ZERO (1<<8)
  96. #define NPTXFE_HALF (0<<7)
  97. #define NPTXFE_ZERO (1<<7)
  98. #define MODE_SLAVE (0<<5)
  99. #define MODE_DMA (1<<5)
  100. #define BURST_SINGLE (0<<1)
  101. #define BURST_INCR (1<<1)
  102. #define BURST_INCR4 (3<<1)
  103. #define BURST_INCR8 (5<<1)
  104. #define BURST_INCR16 (7<<1)
  105. #define GBL_INT_UNMASK (1<<0)
  106. #define GBL_INT_MASK (0<<0)
  107. /* DWC2_UDC_OTG_GRSTCTL */
  108. #define AHB_MASTER_IDLE (1u<<31)
  109. #define CORE_SOFT_RESET (0x1<<0)
  110. /* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
  111. #define INT_RESUME (1u<<31)
  112. #define INT_DISCONN (0x1<<29)
  113. #define INT_CONN_ID_STS_CNG (0x1<<28)
  114. #define INT_OUT_EP (0x1<<19)
  115. #define INT_IN_EP (0x1<<18)
  116. #define INT_ENUMDONE (0x1<<13)
  117. #define INT_RESET (0x1<<12)
  118. #define INT_SUSPEND (0x1<<11)
  119. #define INT_EARLY_SUSPEND (0x1<<10)
  120. #define INT_NP_TX_FIFO_EMPTY (0x1<<5)
  121. #define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
  122. #define INT_SOF (0x1<<3)
  123. #define INT_OTG (0x1<<2)
  124. #define INT_DEV_MODE (0x0<<0)
  125. #define INT_HOST_MODE (0x1<<1)
  126. #define INT_GOUTNakEff (0x01<<7)
  127. #define INT_GINNakEff (0x01<<6)
  128. #define FULL_SPEED_CONTROL_PKT_SIZE 8
  129. #define FULL_SPEED_BULK_PKT_SIZE 64
  130. #define HIGH_SPEED_CONTROL_PKT_SIZE 64
  131. #define HIGH_SPEED_BULK_PKT_SIZE 512
  132. #define RX_FIFO_SIZE (1024)
  133. #define NPTX_FIFO_SIZE (1024)
  134. #define PTX_FIFO_SIZE (384)
  135. #define DEPCTL_TXFNUM_0 (0x0<<22)
  136. #define DEPCTL_TXFNUM_1 (0x1<<22)
  137. #define DEPCTL_TXFNUM_2 (0x2<<22)
  138. #define DEPCTL_TXFNUM_3 (0x3<<22)
  139. #define DEPCTL_TXFNUM_4 (0x4<<22)
  140. /* Enumeration speed */
  141. #define USB_HIGH_30_60MHZ (0x0<<1)
  142. #define USB_FULL_30_60MHZ (0x1<<1)
  143. #define USB_LOW_6MHZ (0x2<<1)
  144. #define USB_FULL_48MHZ (0x3<<1)
  145. /* DWC2_UDC_OTG_GRXSTSP STATUS */
  146. #define OUT_PKT_RECEIVED (0x2<<17)
  147. #define OUT_TRANSFER_COMPLELTED (0x3<<17)
  148. #define SETUP_TRANSACTION_COMPLETED (0x4<<17)
  149. #define SETUP_PKT_RECEIVED (0x6<<17)
  150. #define GLOBAL_OUT_NAK (0x1<<17)
  151. /* DWC2_UDC_OTG_DCTL device control register */
  152. #define NORMAL_OPERATION (0x1<<0)
  153. #define SOFT_DISCONNECT (0x1<<1)
  154. /* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
  155. #define DAINT_OUT_BIT (16)
  156. #define DAINT_MASK (0xFFFF)
  157. /* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
  158. control IN/OUT endpoint 0 control register */
  159. #define DEPCTL_EPENA (0x1<<31)
  160. #define DEPCTL_EPDIS (0x1<<30)
  161. #define DEPCTL_SETD1PID (0x1<<29)
  162. #define DEPCTL_SETD0PID (0x1<<28)
  163. #define DEPCTL_SNAK (0x1<<27)
  164. #define DEPCTL_CNAK (0x1<<26)
  165. #define DEPCTL_STALL (0x1<<21)
  166. #define DEPCTL_TYPE_BIT (18)
  167. #define DEPCTL_TYPE_MASK (0x3<<18)
  168. #define DEPCTL_CTRL_TYPE (0x0<<18)
  169. #define DEPCTL_ISO_TYPE (0x1<<18)
  170. #define DEPCTL_BULK_TYPE (0x2<<18)
  171. #define DEPCTL_INTR_TYPE (0x3<<18)
  172. #define DEPCTL_USBACTEP (0x1<<15)
  173. #define DEPCTL_NEXT_EP_BIT (11)
  174. #define DEPCTL_MPS_BIT (0)
  175. #define DEPCTL_MPS_MASK (0x7FF)
  176. #define DEPCTL0_MPS_64 (0x0<<0)
  177. #define DEPCTL0_MPS_32 (0x1<<0)
  178. #define DEPCTL0_MPS_16 (0x2<<0)
  179. #define DEPCTL0_MPS_8 (0x3<<0)
  180. #define DEPCTL_MPS_BULK_512 (512<<0)
  181. #define DEPCTL_MPS_INT_MPS_16 (16<<0)
  182. #define DIEPCTL0_NEXT_EP_BIT (11)
  183. /* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
  184. common interrupt mask register */
  185. /* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
  186. #define BACK2BACK_SETUP_RECEIVED (0x1<<6)
  187. #define INTKNEPMIS (0x1<<5)
  188. #define INTKN_TXFEMP (0x1<<4)
  189. #define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
  190. #define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
  191. #define AHB_ERROR (0x1<<2)
  192. #define EPDISBLD (0x1<<1)
  193. #define TRANSFER_DONE (0x1<<0)
  194. #define USB_PHY_CTRL_EN0 (0x1 << 0)
  195. /* OPHYPWR */
  196. #define PHY_0_SLEEP (0x1 << 5)
  197. #define OTG_DISABLE_0 (0x1 << 4)
  198. #define ANALOG_PWRDOWN (0x1 << 3)
  199. #define FORCE_SUSPEND_0 (0x1 << 0)
  200. /* URSTCON */
  201. #define HOST_SW_RST (0x1 << 4)
  202. #define PHY_SW_RST1 (0x1 << 3)
  203. #define PHYLNK_SW_RST (0x1 << 2)
  204. #define LINK_SW_RST (0x1 << 1)
  205. #define PHY_SW_RST0 (0x1 << 0)
  206. /* OPHYCLK */
  207. #define COMMON_ON_N1 (0x1 << 7)
  208. #define COMMON_ON_N0 (0x1 << 4)
  209. #define ID_PULLUP0 (0x1 << 2)
  210. #define CLK_SEL_24MHZ (0x3 << 0)
  211. #define CLK_SEL_12MHZ (0x2 << 0)
  212. #define CLK_SEL_48MHZ (0x0 << 0)
  213. #define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
  214. #define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
  215. #define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
  216. #define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
  217. /* Device Configuration Register DCFG */
  218. #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
  219. #define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
  220. #define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
  221. #define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
  222. #define EP_MISS_CNT(x) (x << 18)
  223. #define DEVICE_ADDRESS(x) (x << 4)
  224. /* Core Reset Register (GRSTCTL) */
  225. #define TX_FIFO_FLUSH (0x1 << 5)
  226. #define RX_FIFO_FLUSH (0x1 << 4)
  227. #define TX_FIFO_NUMBER(x) (x << 6)
  228. #define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10)
  229. /* Masks definitions */
  230. #define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
  231. | INT_RESET | INT_SUSPEND | INT_OTG)
  232. #define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
  233. #define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
  234. #define GAHBCFG_INIT (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
  235. | GBL_INT_UNMASK)
  236. /* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
  237. #define DIEPT_SIZ_PKT_CNT(x) (x << 19)
  238. #define DIEPT_SIZ_XFER_SIZE(x) (x << 0)
  239. /* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
  240. #define DOEPT_SIZ_PKT_CNT(x) (x << 19)
  241. #define DOEPT_SIZ_XFER_SIZE(x) (x << 0)
  242. #define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
  243. #define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
  244. /* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
  245. #define DIEPCTL_TX_FIFO_NUM(x) (x << 22)
  246. #define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
  247. /* Device ALL Endpoints Interrupt Register (DAINT) */
  248. #define DAINT_IN_EP_INT(x) (x << 0)
  249. #define DAINT_OUT_EP_INT(x) (x << 16)
  250. /* User HW Config4 */
  251. #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
  252. #define GHWCFG4_NUM_IN_EPS_SHIFT 26
  253. /* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */
  254. #define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21)
  255. #define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22)
  256. #endif