dimm_spd_eeprom.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. */
  5. #include <i2c.h>
  6. #include <ram.h>
  7. #include <mach/octeon_ddr.h>
  8. #define DEVICE_TYPE DDR4_SPD_KEY_BYTE_DEVICE_TYPE // same for DDR3 and DDR4
  9. #define MODULE_TYPE DDR4_SPD_KEY_BYTE_MODULE_TYPE // same for DDR3 and DDR4
  10. #define BUS_WIDTH(t) (((t) == DDR4_DRAM) ? \
  11. DDR4_SPD_MODULE_MEMORY_BUS_WIDTH : \
  12. DDR3_SPD_MEMORY_BUS_WIDTH)
  13. /*
  14. * Allow legacy code to encode bus number in the upper bits of the address
  15. * These are only supported in read_spd()
  16. */
  17. #define OCTEON_TWSI_BUS_IN_ADDR_BIT 12
  18. #define OCTEON_TWSI_BUS_IN_ADDR_MASK (15 << OCTEON_TWSI_BUS_IN_ADDR_BIT)
  19. #define OCTEON_TWSI_GET_BUS(addr) \
  20. (((addr) >> OCTEON_TWSI_BUS_IN_ADDR_BIT) & 0xf)
  21. const char *ddr3_dimm_types[] = {
  22. /* 0000 */ "Undefined",
  23. /* 0001 */ "RDIMM",
  24. /* 0010 */ "UDIMM",
  25. /* 0011 */ "SO-DIMM",
  26. /* 0100 */ "Micro-DIMM",
  27. /* 0101 */ "Mini-RDIMM",
  28. /* 0110 */ "Mini-UDIMM",
  29. /* 0111 */ "Mini-CDIMM",
  30. /* 1000 */ "72b-SO-UDIMM",
  31. /* 1001 */ "72b-SO-RDIMM",
  32. /* 1010 */ "72b-SO-CDIMM"
  33. /* 1011 */ "LRDIMM",
  34. /* 1100 */ "16b-SO-DIMM",
  35. /* 1101 */ "32b-SO-DIMM",
  36. /* 1110 */ "Reserved",
  37. /* 1111 */ "Reserved"
  38. };
  39. const char *ddr4_dimm_types[] = {
  40. /* 0000 */ "Extended",
  41. /* 0001 */ "RDIMM",
  42. /* 0010 */ "UDIMM",
  43. /* 0011 */ "SO-DIMM",
  44. /* 0100 */ "LRDIMM",
  45. /* 0101 */ "Mini-RDIMM",
  46. /* 0110 */ "Mini-UDIMM",
  47. /* 0111 */ "Reserved",
  48. /* 1000 */ "72b-SO-RDIMM",
  49. /* 1001 */ "72b-SO-UDIMM",
  50. /* 1010 */ "Reserved",
  51. /* 1011 */ "Reserved",
  52. /* 1100 */ "16b-SO-DIMM",
  53. /* 1101 */ "32b-SO-DIMM",
  54. /* 1110 */ "Reserved",
  55. /* 1111 */ "Reserved"
  56. };
  57. static u16 ddr3_crc16(u8 *ptr, int count)
  58. {
  59. /* From DDR3 SPD specification */
  60. int crc, i;
  61. crc = 0;
  62. while (--count >= 0) {
  63. crc = crc ^ (int)*ptr++ << 8;
  64. for (i = 0; i < 8; ++i) {
  65. if (crc & 0x8000)
  66. crc = crc << 1 ^ 0x1021;
  67. else
  68. crc = crc << 1;
  69. }
  70. }
  71. return (crc & 0xFFFF);
  72. }
  73. static int validate_spd_checksum_ddr4(struct dimm_config *dimm_config,
  74. int dimm_index, int twsi_addr, int silent)
  75. {
  76. u8 *spd_data = dimm_config->spd_data[dimm_index];
  77. int crc_bytes = 126;
  78. u16 crc_comp;
  79. /* Check byte 0 to see how many bytes checksum is over */
  80. if (spd_data[0] & 0x80)
  81. crc_bytes = 117;
  82. crc_comp = ddr3_crc16(spd_data, crc_bytes);
  83. if (spd_data[126] == (crc_comp & 0xff) &&
  84. spd_data[127] == (crc_comp >> 8))
  85. return 1;
  86. if (!silent) {
  87. printf("DDR4 SPD CRC error, spd addr: 0x%x, calculated crc: 0x%04x, read crc: 0x%02x%02x\n",
  88. twsi_addr, crc_comp, spd_data[127], spd_data[126]);
  89. }
  90. return 0;
  91. }
  92. static int validate_spd_checksum(struct ddr_priv *priv,
  93. struct dimm_config *dimm_config,
  94. int dimm_index, int twsi_addr,
  95. int silent, u8 rv)
  96. {
  97. if (ddr_verbose(priv))
  98. debug("Validating DIMM at address 0x%x\n", twsi_addr);
  99. if (rv >= 0x8 && rv <= 0xA)
  100. printf("%s: Error: DDR2 support disabled\n", __func__);
  101. if (rv == 0xB)
  102. printf("%s: Error: DDR3 support disabled\n", __func__);
  103. if (rv == 0xC) {
  104. return validate_spd_checksum_ddr4(dimm_config, dimm_index,
  105. twsi_addr, silent);
  106. }
  107. if (!silent) {
  108. printf("Unrecognized DIMM type: 0x%x at spd address: 0x%x\n",
  109. rv, twsi_addr);
  110. }
  111. return 0;
  112. }
  113. /*
  114. * Read an DIMM SPD value, either using TWSI to read it from the DIMM, or
  115. * from a provided array.
  116. */
  117. int read_spd(struct dimm_config *dimm_config, int dimm_index, int spd_field)
  118. {
  119. dimm_index = !!dimm_index;
  120. if (spd_field >= SPD_EEPROM_SIZE) {
  121. printf("ERROR: Trying to read unsupported SPD EEPROM value %d\n",
  122. spd_field);
  123. }
  124. /*
  125. * If pointer to data is provided, use it, otherwise read from SPD
  126. * over twsi
  127. */
  128. if (dimm_config->spd_ptrs[dimm_index])
  129. return dimm_config->spd_ptrs[dimm_index][spd_field];
  130. else if (dimm_config->spd_addrs[dimm_index])
  131. return dimm_config->spd_data[dimm_index][spd_field];
  132. return -1;
  133. }
  134. int read_spd_init(struct dimm_config *dimm_config, int dimm_index)
  135. {
  136. u8 busno = OCTEON_TWSI_GET_BUS(dimm_config->spd_addrs[dimm_index]);
  137. u8 cmdno = dimm_config->spd_addrs[dimm_index];
  138. struct udevice *dev_i2c;
  139. u8 *spd_data;
  140. int ret;
  141. if (dimm_config->spd_cached[dimm_index])
  142. return 0;
  143. dimm_config->spd_cached[dimm_index] = 1;
  144. spd_data = dimm_config->spd_data[dimm_index];
  145. ret = i2c_get_chip_for_busnum(busno, cmdno, 2, &dev_i2c);
  146. if (ret) {
  147. debug("Cannot find SPL EEPROM: %d\n", ret);
  148. return -ENODEV;
  149. }
  150. ret = dm_i2c_read(dev_i2c, 0, spd_data, SPD_EEPROM_SIZE);
  151. return ret;
  152. }
  153. int validate_dimm(struct ddr_priv *priv, struct dimm_config *dimm_config,
  154. int dimm_index)
  155. {
  156. int spd_addr;
  157. dimm_index = !!dimm_index; /* Normalize to 0/1 */
  158. spd_addr = dimm_config->spd_addrs[dimm_index];
  159. debug("Validating dimm %d, spd addr: 0x%02x spd ptr: %p\n",
  160. dimm_index,
  161. dimm_config->spd_addrs[dimm_index],
  162. dimm_config->spd_ptrs[dimm_index]);
  163. /* Only validate 'real' dimms, assume compiled in values are OK */
  164. if (!dimm_config->spd_ptrs[dimm_index]) {
  165. int val0, val1;
  166. int dimm_type;
  167. int ret;
  168. ret = read_spd_init(dimm_config, dimm_index);
  169. if (ret)
  170. return 0;
  171. dimm_type = read_spd(dimm_config, dimm_index,
  172. DDR2_SPD_MEM_TYPE) & 0xff;
  173. switch (dimm_type) {
  174. case 0x0B: /* DDR3 */
  175. if (ddr_verbose(priv))
  176. printf("Validating DDR3 DIMM %d\n", dimm_index);
  177. val0 = read_spd(dimm_config, dimm_index,
  178. DDR3_SPD_DENSITY_BANKS);
  179. val1 = read_spd(dimm_config, dimm_index,
  180. DDR3_SPD_ADDRESSING_ROW_COL_BITS);
  181. if (val0 < 0 && val1 < 0) {
  182. if (ddr_verbose(priv))
  183. printf("Error reading SPD for DIMM %d\n",
  184. dimm_index);
  185. return 0; /* Failed to read dimm */
  186. }
  187. if (val0 == 0xff && val1 == 0xff) {
  188. if (ddr_verbose(priv))
  189. printf("Blank or unreadable SPD for DIMM %d\n",
  190. dimm_index);
  191. /* Blank SPD or otherwise unreadable device */
  192. return 0;
  193. }
  194. /* Don't treat bad checksums as fatal */
  195. validate_spd_checksum(priv, dimm_config, dimm_index,
  196. spd_addr, 0, dimm_type);
  197. break;
  198. case 0x0C: /* DDR4 */
  199. if (ddr_verbose(priv))
  200. printf("Validating DDR4 DIMM %d\n", dimm_index);
  201. val0 = read_spd(dimm_config, dimm_index,
  202. DDR4_SPD_DENSITY_BANKS);
  203. val1 = read_spd(dimm_config, dimm_index,
  204. DDR4_SPD_ADDRESSING_ROW_COL_BITS);
  205. if (val0 < 0 && val1 < 0) {
  206. if (ddr_verbose(priv))
  207. printf("Error reading SPD for DIMM %d\n",
  208. dimm_index);
  209. return 0; /* Failed to read dimm */
  210. }
  211. if (val0 == 0xff && val1 == 0xff) {
  212. if (ddr_verbose(priv)) {
  213. printf("Blank or unreadable SPD for DIMM %d\n",
  214. dimm_index);
  215. }
  216. /* Blank SPD or otherwise unreadable device */
  217. return 0;
  218. }
  219. /* Don't treat bad checksums as fatal */
  220. validate_spd_checksum(priv, dimm_config, dimm_index,
  221. spd_addr, 0, dimm_type);
  222. break;
  223. case 0x00:
  224. /* Terminator detected. Fail silently. */
  225. return 0;
  226. default:
  227. debug("Unknown DIMM type 0x%x for DIMM %d @ 0x%x\n",
  228. dimm_type, dimm_index,
  229. dimm_config->spd_addrs[dimm_index]);
  230. return 0; /* Failed to read dimm */
  231. }
  232. }
  233. return 1;
  234. }
  235. int get_ddr_type(struct dimm_config *dimm_config, int upper_dimm)
  236. {
  237. int spd_ddr_type;
  238. spd_ddr_type = read_spd(dimm_config, upper_dimm, DEVICE_TYPE);
  239. debug("%s:%d spd_ddr_type=0x%02x\n", __func__, __LINE__,
  240. spd_ddr_type);
  241. /* we return only DDR4 or DDR3 */
  242. return (spd_ddr_type == 0x0C) ? DDR4_DRAM : DDR3_DRAM;
  243. }
  244. static int get_dimm_ecc(struct dimm_config *dimm_config, int upper_dimm,
  245. int ddr_type)
  246. {
  247. return !!(read_spd(dimm_config, upper_dimm, BUS_WIDTH(ddr_type)) & 8);
  248. }
  249. int get_dimm_module_type(struct dimm_config *dimm_config, int upper_dimm,
  250. int ddr_type)
  251. {
  252. return read_spd(dimm_config, upper_dimm, MODULE_TYPE) & 0x0f;
  253. }
  254. char *printable_rank_spec(char *buffer, int num_ranks, int dram_width,
  255. int spd_package)
  256. {
  257. int die_count = ((spd_package >> 4) & 7) + 1;
  258. if (spd_package & 0x80) { // non-monolithic
  259. if ((spd_package & 3) == 2) { // 3DS
  260. sprintf(buffer, "%dS%dRx%d", num_ranks, die_count,
  261. dram_width);
  262. } else { // MLS
  263. char hchar = (die_count == 2) ? 'D' : 'Q';
  264. sprintf(buffer, "%d%cRx%d", num_ranks, hchar,
  265. dram_width);
  266. }
  267. } else {
  268. sprintf(buffer, "%dRx%d", num_ranks, dram_width);
  269. }
  270. return buffer;
  271. }
  272. static void report_common_dimm(struct dimm_config *dimm_config, int upper_dimm,
  273. int dimm, const char **dimm_types, int ddr_type,
  274. char *volt_str, int if_num,
  275. int num_ranks, int dram_width, int spd_package)
  276. {
  277. unsigned int spd_module_type;
  278. char rank_spec[8];
  279. int spd_ecc;
  280. spd_module_type = get_dimm_module_type(dimm_config, upper_dimm,
  281. ddr_type);
  282. spd_ecc = get_dimm_ecc(dimm_config, upper_dimm, ddr_type);
  283. printable_rank_spec(rank_spec, num_ranks, dram_width, spd_package);
  284. printf("LMC%d.DIMM%d: DDR%d %s %s %s, %s\n",
  285. if_num, dimm, ddr_type, dimm_types[spd_module_type],
  286. rank_spec, spd_ecc ? "ECC" : "non-ECC", volt_str);
  287. }
  288. static void report_ddr3_dimm(struct dimm_config *dimm_config, int upper_dimm,
  289. int dimm, int if_num)
  290. {
  291. int spd_voltage;
  292. char *volt_str;
  293. int spd_org = read_spd(dimm_config, upper_dimm,
  294. DDR3_SPD_MODULE_ORGANIZATION);
  295. int num_ranks = 1 + ((spd_org >> 3) & 0x7);
  296. int dram_width = 4 << ((spd_org >> 0) & 0x7);
  297. spd_voltage = read_spd(dimm_config, upper_dimm,
  298. DDR3_SPD_NOMINAL_VOLTAGE);
  299. if (spd_voltage == 0 || spd_voltage & 3)
  300. volt_str = "1.5V";
  301. if (spd_voltage & 2)
  302. volt_str = "1.35V";
  303. if (spd_voltage & 4)
  304. volt_str = "1.2xV";
  305. report_common_dimm(dimm_config, upper_dimm, dimm, ddr3_dimm_types,
  306. DDR3_DRAM, volt_str, if_num,
  307. num_ranks, dram_width, /*spd_package*/0);
  308. }
  309. static void report_ddr4_dimm(struct dimm_config *dimm_config, int upper_dimm,
  310. int dimm, int if_num)
  311. {
  312. int spd_voltage;
  313. char *volt_str;
  314. int spd_package = 0xff & read_spd(dimm_config, upper_dimm,
  315. DDR4_SPD_PACKAGE_TYPE);
  316. int spd_org = 0xff & read_spd(dimm_config, upper_dimm,
  317. DDR4_SPD_MODULE_ORGANIZATION);
  318. int num_ranks = 1 + ((spd_org >> 3) & 0x7);
  319. int dram_width = 4 << ((spd_org >> 0) & 0x7);
  320. spd_voltage = read_spd(dimm_config, upper_dimm,
  321. DDR4_SPD_MODULE_NOMINAL_VOLTAGE);
  322. if (spd_voltage == 0x01 || spd_voltage & 0x02)
  323. volt_str = "1.2V";
  324. if (spd_voltage == 0x04 || spd_voltage & 0x08)
  325. volt_str = "TBD1 V";
  326. if (spd_voltage == 0x10 || spd_voltage & 0x20)
  327. volt_str = "TBD2 V";
  328. report_common_dimm(dimm_config, upper_dimm, dimm, ddr4_dimm_types,
  329. DDR4_DRAM, volt_str, if_num,
  330. num_ranks, dram_width, spd_package);
  331. }
  332. void report_dimm(struct dimm_config *dimm_config, int upper_dimm,
  333. int dimm, int if_num)
  334. {
  335. int ddr_type;
  336. /* ddr_type only indicates DDR4 or DDR3 */
  337. ddr_type = get_ddr_type(dimm_config, upper_dimm);
  338. if (ddr_type == DDR4_DRAM)
  339. report_ddr4_dimm(dimm_config, 0, dimm, if_num);
  340. else
  341. report_ddr3_dimm(dimm_config, 0, dimm, if_num);
  342. }