pinctrl-sti.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Pinctrl driver for STMicroelectronics STi SoCs
  4. *
  5. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  6. * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  7. */
  8. #include <common.h>
  9. #include <bitfield.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <regmap.h>
  13. #include <syscon.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <dm/pinctrl.h>
  17. #include <linux/bug.h>
  18. #include <linux/libfdt.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define MAX_STI_PINCONF_ENTRIES 7
  21. /* Output enable */
  22. #define OE (1 << 27)
  23. /* Pull Up */
  24. #define PU (1 << 26)
  25. /* Open Drain */
  26. #define OD (1 << 25)
  27. /* User-frendly defines for Pin Direction */
  28. /* oe = 0, pu = 0, od = 0 */
  29. #define IN (0)
  30. /* oe = 0, pu = 1, od = 0 */
  31. #define IN_PU (PU)
  32. /* oe = 1, pu = 0, od = 0 */
  33. #define OUT (OE)
  34. /* oe = 1, pu = 1, od = 0 */
  35. #define OUT_PU (OE | PU)
  36. /* oe = 1, pu = 0, od = 1 */
  37. #define BIDIR (OE | OD)
  38. /* oe = 1, pu = 1, od = 1 */
  39. #define BIDIR_PU (OE | PU | OD)
  40. struct sti_pinctrl_plat {
  41. struct regmap *regmap;
  42. };
  43. struct sti_pin_desc {
  44. unsigned char bank;
  45. unsigned char pin;
  46. unsigned char alt;
  47. int dir;
  48. };
  49. /*
  50. * PIO alternative Function selector
  51. */
  52. void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
  53. {
  54. struct sti_pinctrl_plat *plat = dev_get_plat(dev);
  55. unsigned long sysconf, *sysconfreg;
  56. int alt = pin_desc->alt;
  57. int bank = pin_desc->bank;
  58. int pin = pin_desc->pin;
  59. sysconfreg = (unsigned long *)plat->regmap->ranges[0].start;
  60. switch (bank) {
  61. case 0 ... 5: /* in "SBC Bank" */
  62. sysconfreg += bank;
  63. break;
  64. case 10 ... 20: /* in "FRONT Bank" */
  65. sysconfreg += bank - 10;
  66. break;
  67. case 30 ... 35: /* in "REAR Bank" */
  68. sysconfreg += bank - 30;
  69. break;
  70. case 40 ... 42: /* in "FLASH Bank" */
  71. sysconfreg += bank - 40;
  72. break;
  73. default:
  74. BUG();
  75. return;
  76. }
  77. sysconf = readl(sysconfreg);
  78. sysconf = bitfield_replace(sysconf, pin * 4, 3, alt);
  79. writel(sysconf, sysconfreg);
  80. }
  81. /* pin configuration */
  82. void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
  83. {
  84. struct sti_pinctrl_plat *plat = dev_get_plat(dev);
  85. int bit;
  86. int oe = 0, pu = 0, od = 0;
  87. unsigned long *sysconfreg;
  88. int bank = pin_desc->bank;
  89. sysconfreg = (unsigned long *)plat->regmap->ranges[0].start + 40;
  90. /*
  91. * NOTE: The PIO configuration for the PIO pins in the
  92. * "FLASH Bank" are different from all the other banks!
  93. * Specifically, the output-enable pin control register
  94. * (SYS_CFG_3040) and the pull-up pin control register
  95. * (SYS_CFG_3050), are both classed as being "reserved".
  96. * Hence, we do not write to these registers to configure
  97. * the OE and PU features for PIOs in this bank. However,
  98. * the open-drain pin control register (SYS_CFG_3060)
  99. * follows the style of the other banks, and so we can
  100. * treat that register normally.
  101. *
  102. * Being pedantic, we should configure the PU and PD features
  103. * in the "FLASH Bank" explicitly instead using the four
  104. * SYS_CFG registers: 3080, 3081, 3085, and 3086. However, this
  105. * would necessitate passing in the alternate function number
  106. * to this function, and adding some horrible complexity here.
  107. * Alternatively, we could just perform 4 32-bit "pokes" to
  108. * these four SYS_CFG registers early in the initialization.
  109. * In practice, these four SYS_CFG registers are correct
  110. * after a reset, and U-Boot does not need to change them, so
  111. * we (cheat and) rely on these registers being correct.
  112. * WARNING: Please be aware of this (pragmatic) behaviour!
  113. */
  114. int flashss = 0; /* bool: PIO in the Flash Sub-System ? */
  115. switch (pin_desc->dir) {
  116. case IN:
  117. oe = 0; pu = 0; od = 0;
  118. break;
  119. case IN_PU:
  120. oe = 0; pu = 1; od = 0;
  121. break;
  122. case OUT:
  123. oe = 1; pu = 0; od = 0;
  124. break;
  125. case BIDIR:
  126. oe = 1; pu = 0; od = 1;
  127. break;
  128. case BIDIR_PU:
  129. oe = 1; pu = 1; od = 1;
  130. break;
  131. default:
  132. pr_err("%s invalid direction value: 0x%x\n",
  133. __func__, pin_desc->dir);
  134. BUG();
  135. break;
  136. }
  137. switch (bank) {
  138. case 0 ... 5: /* in "SBC Bank" */
  139. sysconfreg += bank / 4;
  140. break;
  141. case 10 ... 20: /* in "FRONT Bank" */
  142. bank -= 10;
  143. sysconfreg += bank / 4;
  144. break;
  145. case 30 ... 35: /* in "REAR Bank" */
  146. bank -= 30;
  147. sysconfreg += bank / 4;
  148. break;
  149. case 40 ... 42: /* in "FLASH Bank" */
  150. bank -= 40;
  151. sysconfreg += bank / 4;
  152. flashss = 1; /* pin is in the Flash Sub-System */
  153. break;
  154. default:
  155. BUG();
  156. return;
  157. }
  158. bit = ((bank * 8) + pin_desc->pin) % 32;
  159. /*
  160. * set the "Output Enable" pin control
  161. * but, do nothing if in the flashSS
  162. */
  163. if (!flashss) {
  164. if (oe)
  165. generic_set_bit(bit, sysconfreg);
  166. else
  167. generic_clear_bit(bit, sysconfreg);
  168. }
  169. sysconfreg += 10; /* skip to next set of syscfg registers */
  170. /*
  171. * set the "Pull Up" pin control
  172. * but, do nothing if in the FlashSS
  173. */
  174. if (!flashss) {
  175. if (pu)
  176. generic_set_bit(bit, sysconfreg);
  177. else
  178. generic_clear_bit(bit, sysconfreg);
  179. }
  180. sysconfreg += 10; /* skip to next set of syscfg registers */
  181. /* set the "Open Drain Enable" pin control */
  182. if (od)
  183. generic_set_bit(bit, sysconfreg);
  184. else
  185. generic_clear_bit(bit, sysconfreg);
  186. }
  187. static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  188. {
  189. struct fdtdec_phandle_args args;
  190. const void *blob = gd->fdt_blob;
  191. const char *prop_name;
  192. int node = dev_of_offset(config);
  193. int property_offset, prop_len;
  194. int pinconf_node, ret, count;
  195. const char *bank_name;
  196. u32 cells[MAX_STI_PINCONF_ENTRIES];
  197. struct sti_pin_desc pin_desc;
  198. /* go to next node "st,pins" which contains the pins configuration */
  199. pinconf_node = fdt_subnode_offset(blob, node, "st,pins");
  200. /*
  201. * parse each pins configuration which looks like :
  202. * pin_name = <bank_phandle pin_nb alt dir rt_type rt_delay rt_clk>
  203. */
  204. fdt_for_each_property_offset(property_offset, blob, pinconf_node) {
  205. fdt_getprop_by_offset(blob, property_offset, &prop_name,
  206. &prop_len);
  207. /* extract the bank of the pin description */
  208. ret = fdtdec_parse_phandle_with_args(blob, pinconf_node,
  209. prop_name, "#gpio-cells",
  210. 0, 0, &args);
  211. if (ret < 0) {
  212. pr_err("Can't get the gpio bank phandle: %d\n", ret);
  213. return ret;
  214. }
  215. bank_name = fdt_getprop(blob, args.node, "st,bank-name",
  216. &count);
  217. if (count < 0) {
  218. pr_err("Can't find bank-name property %d\n", count);
  219. return -EINVAL;
  220. }
  221. pin_desc.bank = trailing_strtoln(bank_name, NULL);
  222. count = fdtdec_get_int_array_count(blob, pinconf_node,
  223. prop_name, cells,
  224. ARRAY_SIZE(cells));
  225. if (count < 0) {
  226. pr_err("Bad pin configuration array %d\n", count);
  227. return -EINVAL;
  228. }
  229. if (count > MAX_STI_PINCONF_ENTRIES) {
  230. pr_err("Unsupported pinconf array count %d\n", count);
  231. return -EINVAL;
  232. }
  233. pin_desc.pin = cells[1];
  234. pin_desc.alt = cells[2];
  235. pin_desc.dir = cells[3];
  236. sti_alternate_select(dev, &pin_desc);
  237. sti_pin_configure(dev, &pin_desc);
  238. };
  239. return 0;
  240. }
  241. static int sti_pinctrl_probe(struct udevice *dev)
  242. {
  243. struct sti_pinctrl_plat *plat = dev_get_plat(dev);
  244. struct udevice *syscon;
  245. int err;
  246. /* get corresponding syscon phandle */
  247. err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  248. "st,syscfg", &syscon);
  249. if (err) {
  250. pr_err("unable to find syscon device\n");
  251. return err;
  252. }
  253. plat->regmap = syscon_get_regmap(syscon);
  254. if (!plat->regmap) {
  255. pr_err("unable to find regmap\n");
  256. return -ENODEV;
  257. }
  258. return 0;
  259. }
  260. static const struct udevice_id sti_pinctrl_ids[] = {
  261. { .compatible = "st,stih407-sbc-pinctrl" },
  262. { .compatible = "st,stih407-front-pinctrl" },
  263. { .compatible = "st,stih407-rear-pinctrl" },
  264. { .compatible = "st,stih407-flash-pinctrl" },
  265. { }
  266. };
  267. const struct pinctrl_ops sti_pinctrl_ops = {
  268. .set_state = sti_pinctrl_set_state,
  269. };
  270. U_BOOT_DRIVER(pinctrl_sti) = {
  271. .name = "pinctrl_sti",
  272. .id = UCLASS_PINCTRL,
  273. .of_match = sti_pinctrl_ids,
  274. .ops = &sti_pinctrl_ops,
  275. .probe = sti_pinctrl_probe,
  276. .plat_auto = sizeof(struct sti_pinctrl_plat),
  277. .ops = &sti_pinctrl_ops,
  278. };