mv88e6352.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012
  4. * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <log.h>
  9. #include <miiphy.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <mv88e6352.h>
  13. #define SMI_HDR ((0x8 | 0x1) << 12)
  14. #define SMI_BUSY_MASK (0x8000)
  15. #define SMIRD_OP (0x2 << 10)
  16. #define SMIWR_OP (0x1 << 10)
  17. #define SMI_MASK 0x1f
  18. #define PORT_SHIFT 5
  19. #define COMMAND_REG 0
  20. #define DATA_REG 1
  21. /* global registers */
  22. #define GLOBAL 0x1b
  23. #define GLOBAL_STATUS 0x00
  24. #define PPU_STATE 0x8000
  25. #define GLOBAL_CTRL 0x04
  26. #define SW_RESET 0x8000
  27. #define PPU_ENABLE 0x4000
  28. static int sw_wait_rdy(const char *devname, u8 phy_addr)
  29. {
  30. u16 command;
  31. u32 timeout = 100;
  32. int ret;
  33. /* wait till the SMI is not busy */
  34. do {
  35. /* read command register */
  36. ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command);
  37. if (ret < 0) {
  38. printf("%s: Error reading command register\n",
  39. __func__);
  40. return ret;
  41. }
  42. if (timeout-- == 0) {
  43. printf("Err..(%s) SMI busy timeout\n", __func__);
  44. return -EFAULT;
  45. }
  46. } while (command & SMI_BUSY_MASK);
  47. return 0;
  48. }
  49. static int sw_reg_read(const char *devname, u8 phy_addr, u8 port,
  50. u8 reg, u16 *data)
  51. {
  52. int ret;
  53. u16 command;
  54. ret = sw_wait_rdy(devname, phy_addr);
  55. if (ret)
  56. return ret;
  57. command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) |
  58. (reg & SMI_MASK);
  59. debug("%s: write to command: %#x\n", __func__, command);
  60. ret = miiphy_write(devname, phy_addr, COMMAND_REG, command);
  61. if (ret)
  62. return ret;
  63. ret = sw_wait_rdy(devname, phy_addr);
  64. if (ret)
  65. return ret;
  66. ret = miiphy_read(devname, phy_addr, DATA_REG, data);
  67. return ret;
  68. }
  69. static int sw_reg_write(const char *devname, u8 phy_addr, u8 port,
  70. u8 reg, u16 data)
  71. {
  72. int ret;
  73. u16 value;
  74. ret = sw_wait_rdy(devname, phy_addr);
  75. if (ret)
  76. return ret;
  77. debug("%s: write to data: %#x\n", __func__, data);
  78. ret = miiphy_write(devname, phy_addr, DATA_REG, data);
  79. if (ret)
  80. return ret;
  81. value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) |
  82. (reg & SMI_MASK);
  83. debug("%s: write to command: %#x\n", __func__, value);
  84. ret = miiphy_write(devname, phy_addr, COMMAND_REG, value);
  85. if (ret)
  86. return ret;
  87. ret = sw_wait_rdy(devname, phy_addr);
  88. if (ret)
  89. return ret;
  90. return 0;
  91. }
  92. static int ppu_enable(const char *devname, u8 phy_addr)
  93. {
  94. int i, ret = 0;
  95. u16 reg;
  96. ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, &reg);
  97. if (ret) {
  98. printf("%s: Error reading global ctrl reg\n", __func__);
  99. return ret;
  100. }
  101. reg |= PPU_ENABLE;
  102. ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
  103. if (ret) {
  104. printf("%s: Error writing global ctrl reg\n", __func__);
  105. return ret;
  106. }
  107. for (i = 0; i < 1000; i++) {
  108. sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
  109. &reg);
  110. if ((reg & 0xc000) == 0xc000)
  111. return 0;
  112. udelay(1000);
  113. }
  114. return -ETIMEDOUT;
  115. }
  116. static int ppu_disable(const char *devname, u8 phy_addr)
  117. {
  118. int i, ret = 0;
  119. u16 reg;
  120. ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, &reg);
  121. if (ret) {
  122. printf("%s: Error reading global ctrl reg\n", __func__);
  123. return ret;
  124. }
  125. reg &= ~PPU_ENABLE;
  126. ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
  127. if (ret) {
  128. printf("%s: Error writing global ctrl reg\n", __func__);
  129. return ret;
  130. }
  131. for (i = 0; i < 1000; i++) {
  132. sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
  133. &reg);
  134. if ((reg & 0xc000) != 0xc000)
  135. return 0;
  136. udelay(1000);
  137. }
  138. return -ETIMEDOUT;
  139. }
  140. int mv88e_sw_program(const char *devname, u8 phy_addr,
  141. struct mv88e_sw_reg *regs, int regs_nb)
  142. {
  143. int i, ret = 0;
  144. /* first we need to disable the PPU */
  145. ret = ppu_disable(devname, phy_addr);
  146. if (ret) {
  147. printf("%s: Error disabling PPU\n", __func__);
  148. return ret;
  149. }
  150. for (i = 0; i < regs_nb; i++) {
  151. ret = sw_reg_write(devname, phy_addr, regs[i].port,
  152. regs[i].reg, regs[i].value);
  153. if (ret) {
  154. printf("%s: Error configuring switch\n", __func__);
  155. ppu_enable(devname, phy_addr);
  156. return ret;
  157. }
  158. }
  159. /* re-enable the PPU */
  160. ret = ppu_enable(devname, phy_addr);
  161. if (ret) {
  162. printf("%s: Error enabling PPU\n", __func__);
  163. return ret;
  164. }
  165. return 0;
  166. }
  167. int mv88e_sw_reset(const char *devname, u8 phy_addr)
  168. {
  169. int i, ret = 0;
  170. u16 reg;
  171. ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, &reg);
  172. if (ret) {
  173. printf("%s: Error reading global ctrl reg\n", __func__);
  174. return ret;
  175. }
  176. reg = SW_RESET | PPU_ENABLE | 0x0400;
  177. ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
  178. if (ret) {
  179. printf("%s: Error writing global ctrl reg\n", __func__);
  180. return ret;
  181. }
  182. for (i = 0; i < 1000; i++) {
  183. sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
  184. &reg);
  185. if ((reg & 0xc800) != 0xc800)
  186. return 0;
  187. udelay(1000);
  188. }
  189. return -ETIMEDOUT;
  190. }
  191. int do_mvsw_reg_read(const char *name, int argc, char *const argv[])
  192. {
  193. u16 value = 0, phyaddr, reg, port;
  194. int ret;
  195. phyaddr = dectoul(argv[1], NULL);
  196. port = dectoul(argv[2], NULL);
  197. reg = dectoul(argv[3], NULL);
  198. ret = sw_reg_read(name, phyaddr, port, reg, &value);
  199. printf("%#x\n", value);
  200. return ret;
  201. }
  202. int do_mvsw_reg_write(const char *name, int argc, char *const argv[])
  203. {
  204. u16 value = 0, phyaddr, reg, port;
  205. int ret;
  206. phyaddr = dectoul(argv[1], NULL);
  207. port = dectoul(argv[2], NULL);
  208. reg = dectoul(argv[3], NULL);
  209. value = hextoul(argv[4], NULL);
  210. ret = sw_reg_write(name, phyaddr, port, reg, value);
  211. return ret;
  212. }
  213. int do_mvsw_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  214. {
  215. int ret;
  216. const char *cmd, *ethname;
  217. if (argc < 2)
  218. return cmd_usage(cmdtp);
  219. cmd = argv[1];
  220. --argc;
  221. ++argv;
  222. if (strcmp(cmd, "read") == 0) {
  223. if (argc < 5)
  224. return cmd_usage(cmdtp);
  225. ethname = argv[1];
  226. --argc;
  227. ++argv;
  228. ret = do_mvsw_reg_read(ethname, argc, argv);
  229. } else if (strcmp(cmd, "write") == 0) {
  230. if (argc < 6)
  231. return cmd_usage(cmdtp);
  232. ethname = argv[1];
  233. --argc;
  234. ++argv;
  235. ret = do_mvsw_reg_write(ethname, argc, argv);
  236. } else
  237. return cmd_usage(cmdtp);
  238. return ret;
  239. }
  240. U_BOOT_CMD(
  241. mvsw_reg, 7, 1, do_mvsw_reg,
  242. "marvell 88e6352 switch register access",
  243. "write ethname phyaddr port reg value\n"
  244. "mvsw_reg read ethname phyaddr port reg\n"
  245. );