e1000.c 171 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**************************************************************************
  3. Intel Pro 1000 for ppcboot/das-u-boot
  4. Drivers are port from Intel's Linux driver e1000-4.3.15
  5. and from Etherboot pro 1000 driver by mrakes at vivato dot net
  6. tested on both gig copper and gig fiber boards
  7. ***************************************************************************/
  8. /*******************************************************************************
  9. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  10. Contact Information:
  11. Linux NICS <linux.nics@intel.com>
  12. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  13. *******************************************************************************/
  14. /*
  15. * Copyright (C) Archway Digital Solutions.
  16. *
  17. * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  18. * 2/9/2002
  19. *
  20. * Copyright (C) Linux Networx.
  21. * Massive upgrade to work with the new intel gigabit NICs.
  22. * <ebiederman at lnxi dot com>
  23. *
  24. * Copyright 2011 Freescale Semiconductor, Inc.
  25. */
  26. #include <common.h>
  27. #include <command.h>
  28. #include <cpu_func.h>
  29. #include <dm.h>
  30. #include <errno.h>
  31. #include <log.h>
  32. #include <malloc.h>
  33. #include <memalign.h>
  34. #include <net.h>
  35. #include <pci.h>
  36. #include <linux/delay.h>
  37. #include "e1000.h"
  38. #include <asm/cache.h>
  39. #define TOUT_LOOP 100000
  40. #define E1000_DEFAULT_PCI_PBA 0x00000030
  41. #define E1000_DEFAULT_PCIE_PBA 0x000a0026
  42. /* NIC specific static variables go here */
  43. /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  44. #define E1000_BUFFER_ALIGN 128
  45. /*
  46. * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  47. * Concurrent receiving on multiple active Ethernet devices will not work.
  48. * Normally U-Boot does not support this anyway. To fix it in this driver,
  49. * move these buffers and the tx/rx pointers to struct e1000_hw.
  50. */
  51. DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  52. DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  53. DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  54. static int tx_tail;
  55. static int rx_tail, rx_last;
  56. #ifdef CONFIG_DM_ETH
  57. static int num_cards; /* Number of E1000 devices seen so far */
  58. #endif
  59. static struct pci_device_id e1000_supported[] = {
  60. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  61. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  62. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  63. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  64. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  65. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  66. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  67. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  68. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  69. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  70. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  71. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  73. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  74. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  76. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  77. /* E1000 PCIe card */
  78. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  79. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
  80. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
  81. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
  82. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
  83. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
  84. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
  85. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
  86. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
  87. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
  88. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
  89. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
  90. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
  91. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
  92. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
  93. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
  94. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
  95. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
  96. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
  97. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
  98. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
  99. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
  100. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
  101. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
  102. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
  103. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
  104. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
  105. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
  106. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
  107. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
  108. {}
  109. };
  110. /* Function forward declarations */
  111. static int e1000_setup_link(struct e1000_hw *hw);
  112. static int e1000_setup_fiber_link(struct e1000_hw *hw);
  113. static int e1000_setup_copper_link(struct e1000_hw *hw);
  114. static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
  115. static void e1000_config_collision_dist(struct e1000_hw *hw);
  116. static int e1000_config_mac_to_phy(struct e1000_hw *hw);
  117. static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
  118. static int e1000_check_for_link(struct e1000_hw *hw);
  119. static int e1000_wait_autoneg(struct e1000_hw *hw);
  120. static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
  121. uint16_t * duplex);
  122. static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  123. uint16_t * phy_data);
  124. static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  125. uint16_t phy_data);
  126. static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
  127. static int e1000_phy_reset(struct e1000_hw *hw);
  128. static int e1000_detect_gig_phy(struct e1000_hw *hw);
  129. static void e1000_set_media_type(struct e1000_hw *hw);
  130. static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
  131. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
  132. static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
  133. #ifndef CONFIG_E1000_NO_NVM
  134. static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
  135. static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
  136. static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  137. uint16_t words,
  138. uint16_t *data);
  139. /******************************************************************************
  140. * Raises the EEPROM's clock input.
  141. *
  142. * hw - Struct containing variables accessed by shared code
  143. * eecd - EECD's current value
  144. *****************************************************************************/
  145. void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  146. {
  147. /* Raise the clock input to the EEPROM (by setting the SK bit), and then
  148. * wait 50 microseconds.
  149. */
  150. *eecd = *eecd | E1000_EECD_SK;
  151. E1000_WRITE_REG(hw, EECD, *eecd);
  152. E1000_WRITE_FLUSH(hw);
  153. udelay(50);
  154. }
  155. /******************************************************************************
  156. * Lowers the EEPROM's clock input.
  157. *
  158. * hw - Struct containing variables accessed by shared code
  159. * eecd - EECD's current value
  160. *****************************************************************************/
  161. void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  162. {
  163. /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
  164. * wait 50 microseconds.
  165. */
  166. *eecd = *eecd & ~E1000_EECD_SK;
  167. E1000_WRITE_REG(hw, EECD, *eecd);
  168. E1000_WRITE_FLUSH(hw);
  169. udelay(50);
  170. }
  171. /******************************************************************************
  172. * Shift data bits out to the EEPROM.
  173. *
  174. * hw - Struct containing variables accessed by shared code
  175. * data - data to send to the EEPROM
  176. * count - number of bits to shift out
  177. *****************************************************************************/
  178. static void
  179. e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
  180. {
  181. uint32_t eecd;
  182. uint32_t mask;
  183. /* We need to shift "count" bits out to the EEPROM. So, value in the
  184. * "data" parameter will be shifted out to the EEPROM one bit at a time.
  185. * In order to do this, "data" must be broken down into bits.
  186. */
  187. mask = 0x01 << (count - 1);
  188. eecd = E1000_READ_REG(hw, EECD);
  189. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  190. do {
  191. /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  192. * and then raising and then lowering the clock (the SK bit controls
  193. * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
  194. * by setting "DI" to "0" and then raising and then lowering the clock.
  195. */
  196. eecd &= ~E1000_EECD_DI;
  197. if (data & mask)
  198. eecd |= E1000_EECD_DI;
  199. E1000_WRITE_REG(hw, EECD, eecd);
  200. E1000_WRITE_FLUSH(hw);
  201. udelay(50);
  202. e1000_raise_ee_clk(hw, &eecd);
  203. e1000_lower_ee_clk(hw, &eecd);
  204. mask = mask >> 1;
  205. } while (mask);
  206. /* We leave the "DI" bit set to "0" when we leave this routine. */
  207. eecd &= ~E1000_EECD_DI;
  208. E1000_WRITE_REG(hw, EECD, eecd);
  209. }
  210. /******************************************************************************
  211. * Shift data bits in from the EEPROM
  212. *
  213. * hw - Struct containing variables accessed by shared code
  214. *****************************************************************************/
  215. static uint16_t
  216. e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
  217. {
  218. uint32_t eecd;
  219. uint32_t i;
  220. uint16_t data;
  221. /* In order to read a register from the EEPROM, we need to shift 'count'
  222. * bits in from the EEPROM. Bits are "shifted in" by raising the clock
  223. * input to the EEPROM (setting the SK bit), and then reading the
  224. * value of the "DO" bit. During this "shifting in" process the
  225. * "DI" bit should always be clear.
  226. */
  227. eecd = E1000_READ_REG(hw, EECD);
  228. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  229. data = 0;
  230. for (i = 0; i < count; i++) {
  231. data = data << 1;
  232. e1000_raise_ee_clk(hw, &eecd);
  233. eecd = E1000_READ_REG(hw, EECD);
  234. eecd &= ~(E1000_EECD_DI);
  235. if (eecd & E1000_EECD_DO)
  236. data |= 1;
  237. e1000_lower_ee_clk(hw, &eecd);
  238. }
  239. return data;
  240. }
  241. /******************************************************************************
  242. * Returns EEPROM to a "standby" state
  243. *
  244. * hw - Struct containing variables accessed by shared code
  245. *****************************************************************************/
  246. void e1000_standby_eeprom(struct e1000_hw *hw)
  247. {
  248. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  249. uint32_t eecd;
  250. eecd = E1000_READ_REG(hw, EECD);
  251. if (eeprom->type == e1000_eeprom_microwire) {
  252. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  253. E1000_WRITE_REG(hw, EECD, eecd);
  254. E1000_WRITE_FLUSH(hw);
  255. udelay(eeprom->delay_usec);
  256. /* Clock high */
  257. eecd |= E1000_EECD_SK;
  258. E1000_WRITE_REG(hw, EECD, eecd);
  259. E1000_WRITE_FLUSH(hw);
  260. udelay(eeprom->delay_usec);
  261. /* Select EEPROM */
  262. eecd |= E1000_EECD_CS;
  263. E1000_WRITE_REG(hw, EECD, eecd);
  264. E1000_WRITE_FLUSH(hw);
  265. udelay(eeprom->delay_usec);
  266. /* Clock low */
  267. eecd &= ~E1000_EECD_SK;
  268. E1000_WRITE_REG(hw, EECD, eecd);
  269. E1000_WRITE_FLUSH(hw);
  270. udelay(eeprom->delay_usec);
  271. } else if (eeprom->type == e1000_eeprom_spi) {
  272. /* Toggle CS to flush commands */
  273. eecd |= E1000_EECD_CS;
  274. E1000_WRITE_REG(hw, EECD, eecd);
  275. E1000_WRITE_FLUSH(hw);
  276. udelay(eeprom->delay_usec);
  277. eecd &= ~E1000_EECD_CS;
  278. E1000_WRITE_REG(hw, EECD, eecd);
  279. E1000_WRITE_FLUSH(hw);
  280. udelay(eeprom->delay_usec);
  281. }
  282. }
  283. /***************************************************************************
  284. * Description: Determines if the onboard NVM is FLASH or EEPROM.
  285. *
  286. * hw - Struct containing variables accessed by shared code
  287. ****************************************************************************/
  288. static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
  289. {
  290. uint32_t eecd = 0;
  291. DEBUGFUNC();
  292. if (hw->mac_type == e1000_ich8lan)
  293. return false;
  294. if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
  295. eecd = E1000_READ_REG(hw, EECD);
  296. /* Isolate bits 15 & 16 */
  297. eecd = ((eecd >> 15) & 0x03);
  298. /* If both bits are set, device is Flash type */
  299. if (eecd == 0x03)
  300. return false;
  301. }
  302. return true;
  303. }
  304. /******************************************************************************
  305. * Prepares EEPROM for access
  306. *
  307. * hw - Struct containing variables accessed by shared code
  308. *
  309. * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  310. * function should be called before issuing a command to the EEPROM.
  311. *****************************************************************************/
  312. int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
  313. {
  314. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  315. uint32_t eecd, i = 0;
  316. DEBUGFUNC();
  317. if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
  318. return -E1000_ERR_SWFW_SYNC;
  319. eecd = E1000_READ_REG(hw, EECD);
  320. if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
  321. /* Request EEPROM Access */
  322. if (hw->mac_type > e1000_82544) {
  323. eecd |= E1000_EECD_REQ;
  324. E1000_WRITE_REG(hw, EECD, eecd);
  325. eecd = E1000_READ_REG(hw, EECD);
  326. while ((!(eecd & E1000_EECD_GNT)) &&
  327. (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
  328. i++;
  329. udelay(5);
  330. eecd = E1000_READ_REG(hw, EECD);
  331. }
  332. if (!(eecd & E1000_EECD_GNT)) {
  333. eecd &= ~E1000_EECD_REQ;
  334. E1000_WRITE_REG(hw, EECD, eecd);
  335. DEBUGOUT("Could not acquire EEPROM grant\n");
  336. return -E1000_ERR_EEPROM;
  337. }
  338. }
  339. }
  340. /* Setup EEPROM for Read/Write */
  341. if (eeprom->type == e1000_eeprom_microwire) {
  342. /* Clear SK and DI */
  343. eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  344. E1000_WRITE_REG(hw, EECD, eecd);
  345. /* Set CS */
  346. eecd |= E1000_EECD_CS;
  347. E1000_WRITE_REG(hw, EECD, eecd);
  348. } else if (eeprom->type == e1000_eeprom_spi) {
  349. /* Clear SK and CS */
  350. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  351. E1000_WRITE_REG(hw, EECD, eecd);
  352. udelay(1);
  353. }
  354. return E1000_SUCCESS;
  355. }
  356. /******************************************************************************
  357. * Sets up eeprom variables in the hw struct. Must be called after mac_type
  358. * is configured. Additionally, if this is ICH8, the flash controller GbE
  359. * registers must be mapped, or this will crash.
  360. *
  361. * hw - Struct containing variables accessed by shared code
  362. *****************************************************************************/
  363. static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
  364. {
  365. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  366. uint32_t eecd;
  367. int32_t ret_val = E1000_SUCCESS;
  368. uint16_t eeprom_size;
  369. if (hw->mac_type == e1000_igb)
  370. eecd = E1000_READ_REG(hw, I210_EECD);
  371. else
  372. eecd = E1000_READ_REG(hw, EECD);
  373. DEBUGFUNC();
  374. switch (hw->mac_type) {
  375. case e1000_82542_rev2_0:
  376. case e1000_82542_rev2_1:
  377. case e1000_82543:
  378. case e1000_82544:
  379. eeprom->type = e1000_eeprom_microwire;
  380. eeprom->word_size = 64;
  381. eeprom->opcode_bits = 3;
  382. eeprom->address_bits = 6;
  383. eeprom->delay_usec = 50;
  384. eeprom->use_eerd = false;
  385. eeprom->use_eewr = false;
  386. break;
  387. case e1000_82540:
  388. case e1000_82545:
  389. case e1000_82545_rev_3:
  390. case e1000_82546:
  391. case e1000_82546_rev_3:
  392. eeprom->type = e1000_eeprom_microwire;
  393. eeprom->opcode_bits = 3;
  394. eeprom->delay_usec = 50;
  395. if (eecd & E1000_EECD_SIZE) {
  396. eeprom->word_size = 256;
  397. eeprom->address_bits = 8;
  398. } else {
  399. eeprom->word_size = 64;
  400. eeprom->address_bits = 6;
  401. }
  402. eeprom->use_eerd = false;
  403. eeprom->use_eewr = false;
  404. break;
  405. case e1000_82541:
  406. case e1000_82541_rev_2:
  407. case e1000_82547:
  408. case e1000_82547_rev_2:
  409. if (eecd & E1000_EECD_TYPE) {
  410. eeprom->type = e1000_eeprom_spi;
  411. eeprom->opcode_bits = 8;
  412. eeprom->delay_usec = 1;
  413. if (eecd & E1000_EECD_ADDR_BITS) {
  414. eeprom->page_size = 32;
  415. eeprom->address_bits = 16;
  416. } else {
  417. eeprom->page_size = 8;
  418. eeprom->address_bits = 8;
  419. }
  420. } else {
  421. eeprom->type = e1000_eeprom_microwire;
  422. eeprom->opcode_bits = 3;
  423. eeprom->delay_usec = 50;
  424. if (eecd & E1000_EECD_ADDR_BITS) {
  425. eeprom->word_size = 256;
  426. eeprom->address_bits = 8;
  427. } else {
  428. eeprom->word_size = 64;
  429. eeprom->address_bits = 6;
  430. }
  431. }
  432. eeprom->use_eerd = false;
  433. eeprom->use_eewr = false;
  434. break;
  435. case e1000_82571:
  436. case e1000_82572:
  437. eeprom->type = e1000_eeprom_spi;
  438. eeprom->opcode_bits = 8;
  439. eeprom->delay_usec = 1;
  440. if (eecd & E1000_EECD_ADDR_BITS) {
  441. eeprom->page_size = 32;
  442. eeprom->address_bits = 16;
  443. } else {
  444. eeprom->page_size = 8;
  445. eeprom->address_bits = 8;
  446. }
  447. eeprom->use_eerd = false;
  448. eeprom->use_eewr = false;
  449. break;
  450. case e1000_82573:
  451. case e1000_82574:
  452. eeprom->type = e1000_eeprom_spi;
  453. eeprom->opcode_bits = 8;
  454. eeprom->delay_usec = 1;
  455. if (eecd & E1000_EECD_ADDR_BITS) {
  456. eeprom->page_size = 32;
  457. eeprom->address_bits = 16;
  458. } else {
  459. eeprom->page_size = 8;
  460. eeprom->address_bits = 8;
  461. }
  462. if (e1000_is_onboard_nvm_eeprom(hw) == false) {
  463. eeprom->use_eerd = true;
  464. eeprom->use_eewr = true;
  465. eeprom->type = e1000_eeprom_flash;
  466. eeprom->word_size = 2048;
  467. /* Ensure that the Autonomous FLASH update bit is cleared due to
  468. * Flash update issue on parts which use a FLASH for NVM. */
  469. eecd &= ~E1000_EECD_AUPDEN;
  470. E1000_WRITE_REG(hw, EECD, eecd);
  471. }
  472. break;
  473. case e1000_80003es2lan:
  474. eeprom->type = e1000_eeprom_spi;
  475. eeprom->opcode_bits = 8;
  476. eeprom->delay_usec = 1;
  477. if (eecd & E1000_EECD_ADDR_BITS) {
  478. eeprom->page_size = 32;
  479. eeprom->address_bits = 16;
  480. } else {
  481. eeprom->page_size = 8;
  482. eeprom->address_bits = 8;
  483. }
  484. eeprom->use_eerd = true;
  485. eeprom->use_eewr = false;
  486. break;
  487. case e1000_igb:
  488. /* i210 has 4k of iNVM mapped as EEPROM */
  489. eeprom->type = e1000_eeprom_invm;
  490. eeprom->opcode_bits = 8;
  491. eeprom->delay_usec = 1;
  492. eeprom->page_size = 32;
  493. eeprom->address_bits = 16;
  494. eeprom->use_eerd = true;
  495. eeprom->use_eewr = false;
  496. break;
  497. default:
  498. break;
  499. }
  500. if (eeprom->type == e1000_eeprom_spi ||
  501. eeprom->type == e1000_eeprom_invm) {
  502. /* eeprom_size will be an enum [0..8] that maps
  503. * to eeprom sizes 128B to
  504. * 32KB (incremented by powers of 2).
  505. */
  506. if (hw->mac_type <= e1000_82547_rev_2) {
  507. /* Set to default value for initial eeprom read. */
  508. eeprom->word_size = 64;
  509. ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
  510. &eeprom_size);
  511. if (ret_val)
  512. return ret_val;
  513. eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
  514. >> EEPROM_SIZE_SHIFT;
  515. /* 256B eeprom size was not supported in earlier
  516. * hardware, so we bump eeprom_size up one to
  517. * ensure that "1" (which maps to 256B) is never
  518. * the result used in the shifting logic below. */
  519. if (eeprom_size)
  520. eeprom_size++;
  521. } else {
  522. eeprom_size = (uint16_t)((eecd &
  523. E1000_EECD_SIZE_EX_MASK) >>
  524. E1000_EECD_SIZE_EX_SHIFT);
  525. }
  526. eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
  527. }
  528. return ret_val;
  529. }
  530. /******************************************************************************
  531. * Polls the status bit (bit 1) of the EERD to determine when the read is done.
  532. *
  533. * hw - Struct containing variables accessed by shared code
  534. *****************************************************************************/
  535. static int32_t
  536. e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
  537. {
  538. uint32_t attempts = 100000;
  539. uint32_t i, reg = 0;
  540. int32_t done = E1000_ERR_EEPROM;
  541. for (i = 0; i < attempts; i++) {
  542. if (eerd == E1000_EEPROM_POLL_READ) {
  543. if (hw->mac_type == e1000_igb)
  544. reg = E1000_READ_REG(hw, I210_EERD);
  545. else
  546. reg = E1000_READ_REG(hw, EERD);
  547. } else {
  548. if (hw->mac_type == e1000_igb)
  549. reg = E1000_READ_REG(hw, I210_EEWR);
  550. else
  551. reg = E1000_READ_REG(hw, EEWR);
  552. }
  553. if (reg & E1000_EEPROM_RW_REG_DONE) {
  554. done = E1000_SUCCESS;
  555. break;
  556. }
  557. udelay(5);
  558. }
  559. return done;
  560. }
  561. /******************************************************************************
  562. * Reads a 16 bit word from the EEPROM using the EERD register.
  563. *
  564. * hw - Struct containing variables accessed by shared code
  565. * offset - offset of word in the EEPROM to read
  566. * data - word read from the EEPROM
  567. * words - number of words to read
  568. *****************************************************************************/
  569. static int32_t
  570. e1000_read_eeprom_eerd(struct e1000_hw *hw,
  571. uint16_t offset,
  572. uint16_t words,
  573. uint16_t *data)
  574. {
  575. uint32_t i, eerd = 0;
  576. int32_t error = 0;
  577. for (i = 0; i < words; i++) {
  578. eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
  579. E1000_EEPROM_RW_REG_START;
  580. if (hw->mac_type == e1000_igb)
  581. E1000_WRITE_REG(hw, I210_EERD, eerd);
  582. else
  583. E1000_WRITE_REG(hw, EERD, eerd);
  584. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
  585. if (error)
  586. break;
  587. if (hw->mac_type == e1000_igb) {
  588. data[i] = (E1000_READ_REG(hw, I210_EERD) >>
  589. E1000_EEPROM_RW_REG_DATA);
  590. } else {
  591. data[i] = (E1000_READ_REG(hw, EERD) >>
  592. E1000_EEPROM_RW_REG_DATA);
  593. }
  594. }
  595. return error;
  596. }
  597. void e1000_release_eeprom(struct e1000_hw *hw)
  598. {
  599. uint32_t eecd;
  600. DEBUGFUNC();
  601. eecd = E1000_READ_REG(hw, EECD);
  602. if (hw->eeprom.type == e1000_eeprom_spi) {
  603. eecd |= E1000_EECD_CS; /* Pull CS high */
  604. eecd &= ~E1000_EECD_SK; /* Lower SCK */
  605. E1000_WRITE_REG(hw, EECD, eecd);
  606. udelay(hw->eeprom.delay_usec);
  607. } else if (hw->eeprom.type == e1000_eeprom_microwire) {
  608. /* cleanup eeprom */
  609. /* CS on Microwire is active-high */
  610. eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  611. E1000_WRITE_REG(hw, EECD, eecd);
  612. /* Rising edge of clock */
  613. eecd |= E1000_EECD_SK;
  614. E1000_WRITE_REG(hw, EECD, eecd);
  615. E1000_WRITE_FLUSH(hw);
  616. udelay(hw->eeprom.delay_usec);
  617. /* Falling edge of clock */
  618. eecd &= ~E1000_EECD_SK;
  619. E1000_WRITE_REG(hw, EECD, eecd);
  620. E1000_WRITE_FLUSH(hw);
  621. udelay(hw->eeprom.delay_usec);
  622. }
  623. /* Stop requesting EEPROM access */
  624. if (hw->mac_type > e1000_82544) {
  625. eecd &= ~E1000_EECD_REQ;
  626. E1000_WRITE_REG(hw, EECD, eecd);
  627. }
  628. e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
  629. }
  630. /******************************************************************************
  631. * Reads a 16 bit word from the EEPROM.
  632. *
  633. * hw - Struct containing variables accessed by shared code
  634. *****************************************************************************/
  635. static int32_t
  636. e1000_spi_eeprom_ready(struct e1000_hw *hw)
  637. {
  638. uint16_t retry_count = 0;
  639. uint8_t spi_stat_reg;
  640. DEBUGFUNC();
  641. /* Read "Status Register" repeatedly until the LSB is cleared. The
  642. * EEPROM will signal that the command has been completed by clearing
  643. * bit 0 of the internal status register. If it's not cleared within
  644. * 5 milliseconds, then error out.
  645. */
  646. retry_count = 0;
  647. do {
  648. e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
  649. hw->eeprom.opcode_bits);
  650. spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
  651. if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
  652. break;
  653. udelay(5);
  654. retry_count += 5;
  655. e1000_standby_eeprom(hw);
  656. } while (retry_count < EEPROM_MAX_RETRY_SPI);
  657. /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
  658. * only 0-5mSec on 5V devices)
  659. */
  660. if (retry_count >= EEPROM_MAX_RETRY_SPI) {
  661. DEBUGOUT("SPI EEPROM Status error\n");
  662. return -E1000_ERR_EEPROM;
  663. }
  664. return E1000_SUCCESS;
  665. }
  666. /******************************************************************************
  667. * Reads a 16 bit word from the EEPROM.
  668. *
  669. * hw - Struct containing variables accessed by shared code
  670. * offset - offset of word in the EEPROM to read
  671. * data - word read from the EEPROM
  672. *****************************************************************************/
  673. static int32_t
  674. e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  675. uint16_t words, uint16_t *data)
  676. {
  677. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  678. uint32_t i = 0;
  679. DEBUGFUNC();
  680. /* If eeprom is not yet detected, do so now */
  681. if (eeprom->word_size == 0)
  682. e1000_init_eeprom_params(hw);
  683. /* A check for invalid values: offset too large, too many words,
  684. * and not enough words.
  685. */
  686. if ((offset >= eeprom->word_size) ||
  687. (words > eeprom->word_size - offset) ||
  688. (words == 0)) {
  689. DEBUGOUT("\"words\" parameter out of bounds."
  690. "Words = %d, size = %d\n", offset, eeprom->word_size);
  691. return -E1000_ERR_EEPROM;
  692. }
  693. /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
  694. * directly. In this case, we need to acquire the EEPROM so that
  695. * FW or other port software does not interrupt.
  696. */
  697. if (e1000_is_onboard_nvm_eeprom(hw) == true &&
  698. hw->eeprom.use_eerd == false) {
  699. /* Prepare the EEPROM for bit-bang reading */
  700. if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  701. return -E1000_ERR_EEPROM;
  702. }
  703. /* Eerd register EEPROM access requires no eeprom aquire/release */
  704. if (eeprom->use_eerd == true)
  705. return e1000_read_eeprom_eerd(hw, offset, words, data);
  706. /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
  707. * acquired the EEPROM at this point, so any returns should relase it */
  708. if (eeprom->type == e1000_eeprom_spi) {
  709. uint16_t word_in;
  710. uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
  711. if (e1000_spi_eeprom_ready(hw)) {
  712. e1000_release_eeprom(hw);
  713. return -E1000_ERR_EEPROM;
  714. }
  715. e1000_standby_eeprom(hw);
  716. /* Some SPI eeproms use the 8th address bit embedded in
  717. * the opcode */
  718. if ((eeprom->address_bits == 8) && (offset >= 128))
  719. read_opcode |= EEPROM_A8_OPCODE_SPI;
  720. /* Send the READ command (opcode + addr) */
  721. e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
  722. e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
  723. eeprom->address_bits);
  724. /* Read the data. The address of the eeprom internally
  725. * increments with each byte (spi) being read, saving on the
  726. * overhead of eeprom setup and tear-down. The address
  727. * counter will roll over if reading beyond the size of
  728. * the eeprom, thus allowing the entire memory to be read
  729. * starting from any offset. */
  730. for (i = 0; i < words; i++) {
  731. word_in = e1000_shift_in_ee_bits(hw, 16);
  732. data[i] = (word_in >> 8) | (word_in << 8);
  733. }
  734. } else if (eeprom->type == e1000_eeprom_microwire) {
  735. for (i = 0; i < words; i++) {
  736. /* Send the READ command (opcode + addr) */
  737. e1000_shift_out_ee_bits(hw,
  738. EEPROM_READ_OPCODE_MICROWIRE,
  739. eeprom->opcode_bits);
  740. e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
  741. eeprom->address_bits);
  742. /* Read the data. For microwire, each word requires
  743. * the overhead of eeprom setup and tear-down. */
  744. data[i] = e1000_shift_in_ee_bits(hw, 16);
  745. e1000_standby_eeprom(hw);
  746. }
  747. }
  748. /* End this read operation */
  749. e1000_release_eeprom(hw);
  750. return E1000_SUCCESS;
  751. }
  752. /******************************************************************************
  753. * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
  754. * @hw: pointer to the HW structure
  755. * @offset: offset within the Shadow Ram to be written to
  756. * @words: number of words to write
  757. * @data: 16 bit word(s) to be written to the Shadow Ram
  758. *
  759. * Writes data to Shadow Ram at offset using EEWR register.
  760. *
  761. * If e1000_update_eeprom_checksum_i210 is not called after this function, the
  762. * Shadow Ram will most likely contain an invalid checksum.
  763. *****************************************************************************/
  764. static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
  765. uint16_t words, uint16_t *data)
  766. {
  767. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  768. uint32_t i, k, eewr = 0;
  769. uint32_t attempts = 100000;
  770. int32_t ret_val = 0;
  771. /* A check for invalid values: offset too large, too many words,
  772. * too many words for the offset, and not enough words.
  773. */
  774. if ((offset >= eeprom->word_size) ||
  775. (words > (eeprom->word_size - offset)) || (words == 0)) {
  776. DEBUGOUT("nvm parameter(s) out of bounds\n");
  777. ret_val = -E1000_ERR_EEPROM;
  778. goto out;
  779. }
  780. for (i = 0; i < words; i++) {
  781. eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
  782. | (data[i] << E1000_EEPROM_RW_REG_DATA) |
  783. E1000_EEPROM_RW_REG_START;
  784. E1000_WRITE_REG(hw, I210_EEWR, eewr);
  785. for (k = 0; k < attempts; k++) {
  786. if (E1000_EEPROM_RW_REG_DONE &
  787. E1000_READ_REG(hw, I210_EEWR)) {
  788. ret_val = 0;
  789. break;
  790. }
  791. udelay(5);
  792. }
  793. if (ret_val) {
  794. DEBUGOUT("Shadow RAM write EEWR timed out\n");
  795. break;
  796. }
  797. }
  798. out:
  799. return ret_val;
  800. }
  801. /******************************************************************************
  802. * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
  803. * @hw: pointer to the HW structure
  804. *
  805. *****************************************************************************/
  806. static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
  807. {
  808. int32_t ret_val = -E1000_ERR_EEPROM;
  809. uint32_t i, reg;
  810. for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
  811. reg = E1000_READ_REG(hw, EECD);
  812. if (reg & E1000_EECD_FLUDONE_I210) {
  813. ret_val = 0;
  814. break;
  815. }
  816. udelay(5);
  817. }
  818. return ret_val;
  819. }
  820. /******************************************************************************
  821. * e1000_update_flash_i210 - Commit EEPROM to the flash
  822. * @hw: pointer to the HW structure
  823. *
  824. *****************************************************************************/
  825. static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
  826. {
  827. int32_t ret_val = 0;
  828. uint32_t flup;
  829. ret_val = e1000_pool_flash_update_done_i210(hw);
  830. if (ret_val == -E1000_ERR_EEPROM) {
  831. DEBUGOUT("Flash update time out\n");
  832. goto out;
  833. }
  834. flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
  835. E1000_WRITE_REG(hw, EECD, flup);
  836. ret_val = e1000_pool_flash_update_done_i210(hw);
  837. if (ret_val)
  838. DEBUGOUT("Flash update time out\n");
  839. else
  840. DEBUGOUT("Flash update complete\n");
  841. out:
  842. return ret_val;
  843. }
  844. /******************************************************************************
  845. * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
  846. * @hw: pointer to the HW structure
  847. *
  848. * Updates the EEPROM checksum by reading/adding each word of the EEPROM
  849. * up to the checksum. Then calculates the EEPROM checksum and writes the
  850. * value to the EEPROM. Next commit EEPROM data onto the Flash.
  851. *****************************************************************************/
  852. static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
  853. {
  854. int32_t ret_val = 0;
  855. uint16_t checksum = 0;
  856. uint16_t i, nvm_data;
  857. /* Read the first word from the EEPROM. If this times out or fails, do
  858. * not continue or we could be in for a very long wait while every
  859. * EEPROM read fails
  860. */
  861. ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
  862. if (ret_val) {
  863. DEBUGOUT("EEPROM read failed\n");
  864. goto out;
  865. }
  866. if (!(e1000_get_hw_eeprom_semaphore(hw))) {
  867. /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
  868. * because we do not want to take the synchronization
  869. * semaphores twice here.
  870. */
  871. for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
  872. ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
  873. if (ret_val) {
  874. e1000_put_hw_eeprom_semaphore(hw);
  875. DEBUGOUT("EEPROM Read Error while updating checksum.\n");
  876. goto out;
  877. }
  878. checksum += nvm_data;
  879. }
  880. checksum = (uint16_t)EEPROM_SUM - checksum;
  881. ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
  882. &checksum);
  883. if (ret_val) {
  884. e1000_put_hw_eeprom_semaphore(hw);
  885. DEBUGOUT("EEPROM Write Error while updating checksum.\n");
  886. goto out;
  887. }
  888. e1000_put_hw_eeprom_semaphore(hw);
  889. ret_val = e1000_update_flash_i210(hw);
  890. } else {
  891. ret_val = -E1000_ERR_SWFW_SYNC;
  892. }
  893. out:
  894. return ret_val;
  895. }
  896. /******************************************************************************
  897. * Verifies that the EEPROM has a valid checksum
  898. *
  899. * hw - Struct containing variables accessed by shared code
  900. *
  901. * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  902. * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  903. * valid.
  904. *****************************************************************************/
  905. static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
  906. {
  907. uint16_t i, checksum, checksum_reg, *buf;
  908. DEBUGFUNC();
  909. /* Allocate a temporary buffer */
  910. buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
  911. if (!buf) {
  912. E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
  913. return -E1000_ERR_EEPROM;
  914. }
  915. /* Read the EEPROM */
  916. if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
  917. E1000_ERR(hw, "Unable to read EEPROM!\n");
  918. return -E1000_ERR_EEPROM;
  919. }
  920. /* Compute the checksum */
  921. checksum = 0;
  922. for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
  923. checksum += buf[i];
  924. checksum = ((uint16_t)EEPROM_SUM) - checksum;
  925. checksum_reg = buf[i];
  926. /* Verify it! */
  927. if (checksum == checksum_reg)
  928. return 0;
  929. /* Hrm, verification failed, print an error */
  930. E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
  931. E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
  932. checksum_reg, checksum);
  933. return -E1000_ERR_EEPROM;
  934. }
  935. #endif /* CONFIG_E1000_NO_NVM */
  936. /*****************************************************************************
  937. * Set PHY to class A mode
  938. * Assumes the following operations will follow to enable the new class mode.
  939. * 1. Do a PHY soft reset
  940. * 2. Restart auto-negotiation or force link.
  941. *
  942. * hw - Struct containing variables accessed by shared code
  943. ****************************************************************************/
  944. static int32_t
  945. e1000_set_phy_mode(struct e1000_hw *hw)
  946. {
  947. #ifndef CONFIG_E1000_NO_NVM
  948. int32_t ret_val;
  949. uint16_t eeprom_data;
  950. DEBUGFUNC();
  951. if ((hw->mac_type == e1000_82545_rev_3) &&
  952. (hw->media_type == e1000_media_type_copper)) {
  953. ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
  954. 1, &eeprom_data);
  955. if (ret_val)
  956. return ret_val;
  957. if ((eeprom_data != EEPROM_RESERVED_WORD) &&
  958. (eeprom_data & EEPROM_PHY_CLASS_A)) {
  959. ret_val = e1000_write_phy_reg(hw,
  960. M88E1000_PHY_PAGE_SELECT, 0x000B);
  961. if (ret_val)
  962. return ret_val;
  963. ret_val = e1000_write_phy_reg(hw,
  964. M88E1000_PHY_GEN_CONTROL, 0x8104);
  965. if (ret_val)
  966. return ret_val;
  967. hw->phy_reset_disable = false;
  968. }
  969. }
  970. #endif
  971. return E1000_SUCCESS;
  972. }
  973. #ifndef CONFIG_E1000_NO_NVM
  974. /***************************************************************************
  975. *
  976. * Obtaining software semaphore bit (SMBI) before resetting PHY.
  977. *
  978. * hw: Struct containing variables accessed by shared code
  979. *
  980. * returns: - E1000_ERR_RESET if fail to obtain semaphore.
  981. * E1000_SUCCESS at any other case.
  982. *
  983. ***************************************************************************/
  984. static int32_t
  985. e1000_get_software_semaphore(struct e1000_hw *hw)
  986. {
  987. int32_t timeout = hw->eeprom.word_size + 1;
  988. uint32_t swsm;
  989. DEBUGFUNC();
  990. if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
  991. return E1000_SUCCESS;
  992. while (timeout) {
  993. swsm = E1000_READ_REG(hw, SWSM);
  994. /* If SMBI bit cleared, it is now set and we hold
  995. * the semaphore */
  996. if (!(swsm & E1000_SWSM_SMBI))
  997. break;
  998. mdelay(1);
  999. timeout--;
  1000. }
  1001. if (!timeout) {
  1002. DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
  1003. return -E1000_ERR_RESET;
  1004. }
  1005. return E1000_SUCCESS;
  1006. }
  1007. #endif
  1008. /***************************************************************************
  1009. * This function clears HW semaphore bits.
  1010. *
  1011. * hw: Struct containing variables accessed by shared code
  1012. *
  1013. * returns: - None.
  1014. *
  1015. ***************************************************************************/
  1016. static void
  1017. e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
  1018. {
  1019. #ifndef CONFIG_E1000_NO_NVM
  1020. uint32_t swsm;
  1021. DEBUGFUNC();
  1022. if (!hw->eeprom_semaphore_present)
  1023. return;
  1024. swsm = E1000_READ_REG(hw, SWSM);
  1025. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1026. /* Release both semaphores. */
  1027. swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
  1028. } else
  1029. swsm &= ~(E1000_SWSM_SWESMBI);
  1030. E1000_WRITE_REG(hw, SWSM, swsm);
  1031. #endif
  1032. }
  1033. /***************************************************************************
  1034. *
  1035. * Using the combination of SMBI and SWESMBI semaphore bits when resetting
  1036. * adapter or Eeprom access.
  1037. *
  1038. * hw: Struct containing variables accessed by shared code
  1039. *
  1040. * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
  1041. * E1000_SUCCESS at any other case.
  1042. *
  1043. ***************************************************************************/
  1044. static int32_t
  1045. e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
  1046. {
  1047. #ifndef CONFIG_E1000_NO_NVM
  1048. int32_t timeout;
  1049. uint32_t swsm;
  1050. DEBUGFUNC();
  1051. if (!hw->eeprom_semaphore_present)
  1052. return E1000_SUCCESS;
  1053. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1054. /* Get the SW semaphore. */
  1055. if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
  1056. return -E1000_ERR_EEPROM;
  1057. }
  1058. /* Get the FW semaphore. */
  1059. timeout = hw->eeprom.word_size + 1;
  1060. while (timeout) {
  1061. swsm = E1000_READ_REG(hw, SWSM);
  1062. swsm |= E1000_SWSM_SWESMBI;
  1063. E1000_WRITE_REG(hw, SWSM, swsm);
  1064. /* if we managed to set the bit we got the semaphore. */
  1065. swsm = E1000_READ_REG(hw, SWSM);
  1066. if (swsm & E1000_SWSM_SWESMBI)
  1067. break;
  1068. udelay(50);
  1069. timeout--;
  1070. }
  1071. if (!timeout) {
  1072. /* Release semaphores */
  1073. e1000_put_hw_eeprom_semaphore(hw);
  1074. DEBUGOUT("Driver can't access the Eeprom - "
  1075. "SWESMBI bit is set.\n");
  1076. return -E1000_ERR_EEPROM;
  1077. }
  1078. #endif
  1079. return E1000_SUCCESS;
  1080. }
  1081. /* Take ownership of the PHY */
  1082. static int32_t
  1083. e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
  1084. {
  1085. uint32_t swfw_sync = 0;
  1086. uint32_t swmask = mask;
  1087. uint32_t fwmask = mask << 16;
  1088. int32_t timeout = 200;
  1089. DEBUGFUNC();
  1090. while (timeout) {
  1091. if (e1000_get_hw_eeprom_semaphore(hw))
  1092. return -E1000_ERR_SWFW_SYNC;
  1093. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1094. if (!(swfw_sync & (fwmask | swmask)))
  1095. break;
  1096. /* firmware currently using resource (fwmask) */
  1097. /* or other software thread currently using resource (swmask) */
  1098. e1000_put_hw_eeprom_semaphore(hw);
  1099. mdelay(5);
  1100. timeout--;
  1101. }
  1102. if (!timeout) {
  1103. DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
  1104. return -E1000_ERR_SWFW_SYNC;
  1105. }
  1106. swfw_sync |= swmask;
  1107. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1108. e1000_put_hw_eeprom_semaphore(hw);
  1109. return E1000_SUCCESS;
  1110. }
  1111. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
  1112. {
  1113. uint32_t swfw_sync = 0;
  1114. DEBUGFUNC();
  1115. while (e1000_get_hw_eeprom_semaphore(hw))
  1116. ; /* Empty */
  1117. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1118. swfw_sync &= ~mask;
  1119. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1120. e1000_put_hw_eeprom_semaphore(hw);
  1121. }
  1122. static bool e1000_is_second_port(struct e1000_hw *hw)
  1123. {
  1124. switch (hw->mac_type) {
  1125. case e1000_80003es2lan:
  1126. case e1000_82546:
  1127. case e1000_82571:
  1128. if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  1129. return true;
  1130. /* Fallthrough */
  1131. default:
  1132. return false;
  1133. }
  1134. }
  1135. #ifndef CONFIG_E1000_NO_NVM
  1136. /******************************************************************************
  1137. * Reads the adapter's MAC address from the EEPROM
  1138. *
  1139. * hw - Struct containing variables accessed by shared code
  1140. * enetaddr - buffering where the MAC address will be stored
  1141. *****************************************************************************/
  1142. static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
  1143. unsigned char enetaddr[6])
  1144. {
  1145. uint16_t offset;
  1146. uint16_t eeprom_data;
  1147. int i;
  1148. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1149. offset = i >> 1;
  1150. if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  1151. DEBUGOUT("EEPROM Read Error\n");
  1152. return -E1000_ERR_EEPROM;
  1153. }
  1154. enetaddr[i] = eeprom_data & 0xff;
  1155. enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
  1156. }
  1157. return 0;
  1158. }
  1159. /******************************************************************************
  1160. * Reads the adapter's MAC address from the RAL/RAH registers
  1161. *
  1162. * hw - Struct containing variables accessed by shared code
  1163. * enetaddr - buffering where the MAC address will be stored
  1164. *****************************************************************************/
  1165. static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
  1166. unsigned char enetaddr[6])
  1167. {
  1168. uint16_t offset, tmp;
  1169. uint32_t reg_data = 0;
  1170. int i;
  1171. if (hw->mac_type != e1000_igb)
  1172. return -E1000_ERR_MAC_TYPE;
  1173. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1174. offset = i >> 1;
  1175. if (offset == 0)
  1176. reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
  1177. else if (offset == 1)
  1178. reg_data >>= 16;
  1179. else if (offset == 2)
  1180. reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
  1181. tmp = reg_data & 0xffff;
  1182. enetaddr[i] = tmp & 0xff;
  1183. enetaddr[i + 1] = (tmp >> 8) & 0xff;
  1184. }
  1185. return 0;
  1186. }
  1187. /******************************************************************************
  1188. * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  1189. * second function of dual function devices
  1190. *
  1191. * hw - Struct containing variables accessed by shared code
  1192. * enetaddr - buffering where the MAC address will be stored
  1193. *****************************************************************************/
  1194. static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
  1195. {
  1196. int ret_val;
  1197. if (hw->mac_type == e1000_igb) {
  1198. /* i210 preloads MAC address into RAL/RAH registers */
  1199. ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
  1200. } else {
  1201. ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
  1202. }
  1203. if (ret_val)
  1204. return ret_val;
  1205. /* Invert the last bit if this is the second device */
  1206. if (e1000_is_second_port(hw))
  1207. enetaddr[5] ^= 1;
  1208. return 0;
  1209. }
  1210. #endif
  1211. /******************************************************************************
  1212. * Initializes receive address filters.
  1213. *
  1214. * hw - Struct containing variables accessed by shared code
  1215. *
  1216. * Places the MAC address in receive address register 0 and clears the rest
  1217. * of the receive addresss registers. Clears the multicast table. Assumes
  1218. * the receiver is in reset when the routine is called.
  1219. *****************************************************************************/
  1220. static void
  1221. e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
  1222. {
  1223. uint32_t i;
  1224. uint32_t addr_low;
  1225. uint32_t addr_high;
  1226. DEBUGFUNC();
  1227. /* Setup the receive address. */
  1228. DEBUGOUT("Programming MAC Address into RAR[0]\n");
  1229. addr_low = (enetaddr[0] |
  1230. (enetaddr[1] << 8) |
  1231. (enetaddr[2] << 16) | (enetaddr[3] << 24));
  1232. addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
  1233. E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
  1234. E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
  1235. /* Zero out the other 15 receive addresses. */
  1236. DEBUGOUT("Clearing RAR[1-15]\n");
  1237. for (i = 1; i < E1000_RAR_ENTRIES; i++) {
  1238. E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  1239. E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  1240. }
  1241. }
  1242. /******************************************************************************
  1243. * Clears the VLAN filer table
  1244. *
  1245. * hw - Struct containing variables accessed by shared code
  1246. *****************************************************************************/
  1247. static void
  1248. e1000_clear_vfta(struct e1000_hw *hw)
  1249. {
  1250. uint32_t offset;
  1251. for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
  1252. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
  1253. }
  1254. /******************************************************************************
  1255. * Set the mac type member in the hw struct.
  1256. *
  1257. * hw - Struct containing variables accessed by shared code
  1258. *****************************************************************************/
  1259. int32_t
  1260. e1000_set_mac_type(struct e1000_hw *hw)
  1261. {
  1262. DEBUGFUNC();
  1263. switch (hw->device_id) {
  1264. case E1000_DEV_ID_82542:
  1265. switch (hw->revision_id) {
  1266. case E1000_82542_2_0_REV_ID:
  1267. hw->mac_type = e1000_82542_rev2_0;
  1268. break;
  1269. case E1000_82542_2_1_REV_ID:
  1270. hw->mac_type = e1000_82542_rev2_1;
  1271. break;
  1272. default:
  1273. /* Invalid 82542 revision ID */
  1274. return -E1000_ERR_MAC_TYPE;
  1275. }
  1276. break;
  1277. case E1000_DEV_ID_82543GC_FIBER:
  1278. case E1000_DEV_ID_82543GC_COPPER:
  1279. hw->mac_type = e1000_82543;
  1280. break;
  1281. case E1000_DEV_ID_82544EI_COPPER:
  1282. case E1000_DEV_ID_82544EI_FIBER:
  1283. case E1000_DEV_ID_82544GC_COPPER:
  1284. case E1000_DEV_ID_82544GC_LOM:
  1285. hw->mac_type = e1000_82544;
  1286. break;
  1287. case E1000_DEV_ID_82540EM:
  1288. case E1000_DEV_ID_82540EM_LOM:
  1289. case E1000_DEV_ID_82540EP:
  1290. case E1000_DEV_ID_82540EP_LOM:
  1291. case E1000_DEV_ID_82540EP_LP:
  1292. hw->mac_type = e1000_82540;
  1293. break;
  1294. case E1000_DEV_ID_82545EM_COPPER:
  1295. case E1000_DEV_ID_82545EM_FIBER:
  1296. hw->mac_type = e1000_82545;
  1297. break;
  1298. case E1000_DEV_ID_82545GM_COPPER:
  1299. case E1000_DEV_ID_82545GM_FIBER:
  1300. case E1000_DEV_ID_82545GM_SERDES:
  1301. hw->mac_type = e1000_82545_rev_3;
  1302. break;
  1303. case E1000_DEV_ID_82546EB_COPPER:
  1304. case E1000_DEV_ID_82546EB_FIBER:
  1305. case E1000_DEV_ID_82546EB_QUAD_COPPER:
  1306. hw->mac_type = e1000_82546;
  1307. break;
  1308. case E1000_DEV_ID_82546GB_COPPER:
  1309. case E1000_DEV_ID_82546GB_FIBER:
  1310. case E1000_DEV_ID_82546GB_SERDES:
  1311. case E1000_DEV_ID_82546GB_PCIE:
  1312. case E1000_DEV_ID_82546GB_QUAD_COPPER:
  1313. case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
  1314. hw->mac_type = e1000_82546_rev_3;
  1315. break;
  1316. case E1000_DEV_ID_82541EI:
  1317. case E1000_DEV_ID_82541EI_MOBILE:
  1318. case E1000_DEV_ID_82541ER_LOM:
  1319. hw->mac_type = e1000_82541;
  1320. break;
  1321. case E1000_DEV_ID_82541ER:
  1322. case E1000_DEV_ID_82541GI:
  1323. case E1000_DEV_ID_82541GI_LF:
  1324. case E1000_DEV_ID_82541GI_MOBILE:
  1325. hw->mac_type = e1000_82541_rev_2;
  1326. break;
  1327. case E1000_DEV_ID_82547EI:
  1328. case E1000_DEV_ID_82547EI_MOBILE:
  1329. hw->mac_type = e1000_82547;
  1330. break;
  1331. case E1000_DEV_ID_82547GI:
  1332. hw->mac_type = e1000_82547_rev_2;
  1333. break;
  1334. case E1000_DEV_ID_82571EB_COPPER:
  1335. case E1000_DEV_ID_82571EB_FIBER:
  1336. case E1000_DEV_ID_82571EB_SERDES:
  1337. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  1338. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  1339. case E1000_DEV_ID_82571EB_QUAD_COPPER:
  1340. case E1000_DEV_ID_82571PT_QUAD_COPPER:
  1341. case E1000_DEV_ID_82571EB_QUAD_FIBER:
  1342. case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
  1343. hw->mac_type = e1000_82571;
  1344. break;
  1345. case E1000_DEV_ID_82572EI_COPPER:
  1346. case E1000_DEV_ID_82572EI_FIBER:
  1347. case E1000_DEV_ID_82572EI_SERDES:
  1348. case E1000_DEV_ID_82572EI:
  1349. hw->mac_type = e1000_82572;
  1350. break;
  1351. case E1000_DEV_ID_82573E:
  1352. case E1000_DEV_ID_82573E_IAMT:
  1353. case E1000_DEV_ID_82573L:
  1354. hw->mac_type = e1000_82573;
  1355. break;
  1356. case E1000_DEV_ID_82574L:
  1357. hw->mac_type = e1000_82574;
  1358. break;
  1359. case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
  1360. case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
  1361. case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
  1362. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  1363. hw->mac_type = e1000_80003es2lan;
  1364. break;
  1365. case E1000_DEV_ID_ICH8_IGP_M_AMT:
  1366. case E1000_DEV_ID_ICH8_IGP_AMT:
  1367. case E1000_DEV_ID_ICH8_IGP_C:
  1368. case E1000_DEV_ID_ICH8_IFE:
  1369. case E1000_DEV_ID_ICH8_IFE_GT:
  1370. case E1000_DEV_ID_ICH8_IFE_G:
  1371. case E1000_DEV_ID_ICH8_IGP_M:
  1372. hw->mac_type = e1000_ich8lan;
  1373. break;
  1374. case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
  1375. case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
  1376. case PCI_DEVICE_ID_INTEL_I210_COPPER:
  1377. case PCI_DEVICE_ID_INTEL_I211_COPPER:
  1378. case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
  1379. case PCI_DEVICE_ID_INTEL_I210_SERDES:
  1380. case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
  1381. case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
  1382. hw->mac_type = e1000_igb;
  1383. break;
  1384. default:
  1385. /* Should never have loaded on this device */
  1386. return -E1000_ERR_MAC_TYPE;
  1387. }
  1388. return E1000_SUCCESS;
  1389. }
  1390. /******************************************************************************
  1391. * Reset the transmit and receive units; mask and clear all interrupts.
  1392. *
  1393. * hw - Struct containing variables accessed by shared code
  1394. *****************************************************************************/
  1395. void
  1396. e1000_reset_hw(struct e1000_hw *hw)
  1397. {
  1398. uint32_t ctrl;
  1399. uint32_t ctrl_ext;
  1400. uint32_t manc;
  1401. uint32_t pba = 0;
  1402. uint32_t reg;
  1403. DEBUGFUNC();
  1404. /* get the correct pba value for both PCI and PCIe*/
  1405. if (hw->mac_type < e1000_82571)
  1406. pba = E1000_DEFAULT_PCI_PBA;
  1407. else
  1408. pba = E1000_DEFAULT_PCIE_PBA;
  1409. /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  1410. if (hw->mac_type == e1000_82542_rev2_0) {
  1411. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1412. #ifdef CONFIG_DM_ETH
  1413. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1414. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1415. #else
  1416. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1417. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1418. #endif
  1419. }
  1420. /* Clear interrupt mask to stop board from generating interrupts */
  1421. DEBUGOUT("Masking off all interrupts\n");
  1422. if (hw->mac_type == e1000_igb)
  1423. E1000_WRITE_REG(hw, I210_IAM, 0);
  1424. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1425. /* Disable the Transmit and Receive units. Then delay to allow
  1426. * any pending transactions to complete before we hit the MAC with
  1427. * the global reset.
  1428. */
  1429. E1000_WRITE_REG(hw, RCTL, 0);
  1430. E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
  1431. E1000_WRITE_FLUSH(hw);
  1432. if (hw->mac_type == e1000_igb) {
  1433. E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT);
  1434. E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT);
  1435. }
  1436. /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
  1437. hw->tbi_compatibility_on = false;
  1438. /* Delay to allow any outstanding PCI transactions to complete before
  1439. * resetting the device
  1440. */
  1441. mdelay(10);
  1442. /* Issue a global reset to the MAC. This will reset the chip's
  1443. * transmit, receive, DMA, and link units. It will not effect
  1444. * the current PCI configuration. The global reset bit is self-
  1445. * clearing, and should clear within a microsecond.
  1446. */
  1447. DEBUGOUT("Issuing a global reset to MAC\n");
  1448. ctrl = E1000_READ_REG(hw, CTRL);
  1449. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  1450. /* Force a reload from the EEPROM if necessary */
  1451. if (hw->mac_type == e1000_igb) {
  1452. mdelay(20);
  1453. reg = E1000_READ_REG(hw, STATUS);
  1454. if (reg & E1000_STATUS_PF_RST_DONE)
  1455. DEBUGOUT("PF OK\n");
  1456. reg = E1000_READ_REG(hw, I210_EECD);
  1457. if (reg & E1000_EECD_AUTO_RD)
  1458. DEBUGOUT("EEC OK\n");
  1459. } else if (hw->mac_type < e1000_82540) {
  1460. /* Wait for reset to complete */
  1461. udelay(10);
  1462. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1463. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  1464. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1465. E1000_WRITE_FLUSH(hw);
  1466. /* Wait for EEPROM reload */
  1467. mdelay(2);
  1468. } else {
  1469. /* Wait for EEPROM reload (it happens automatically) */
  1470. mdelay(4);
  1471. /* Dissable HW ARPs on ASF enabled adapters */
  1472. manc = E1000_READ_REG(hw, MANC);
  1473. manc &= ~(E1000_MANC_ARP_EN);
  1474. E1000_WRITE_REG(hw, MANC, manc);
  1475. }
  1476. /* Clear interrupt mask to stop board from generating interrupts */
  1477. DEBUGOUT("Masking off all interrupts\n");
  1478. if (hw->mac_type == e1000_igb)
  1479. E1000_WRITE_REG(hw, I210_IAM, 0);
  1480. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1481. /* Clear any pending interrupt events. */
  1482. E1000_READ_REG(hw, ICR);
  1483. /* If MWI was previously enabled, reenable it. */
  1484. if (hw->mac_type == e1000_82542_rev2_0) {
  1485. #ifdef CONFIG_DM_ETH
  1486. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1487. #else
  1488. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1489. #endif
  1490. }
  1491. if (hw->mac_type != e1000_igb)
  1492. E1000_WRITE_REG(hw, PBA, pba);
  1493. }
  1494. /******************************************************************************
  1495. *
  1496. * Initialize a number of hardware-dependent bits
  1497. *
  1498. * hw: Struct containing variables accessed by shared code
  1499. *
  1500. * This function contains hardware limitation workarounds for PCI-E adapters
  1501. *
  1502. *****************************************************************************/
  1503. static void
  1504. e1000_initialize_hardware_bits(struct e1000_hw *hw)
  1505. {
  1506. if ((hw->mac_type >= e1000_82571) &&
  1507. (!hw->initialize_hw_bits_disable)) {
  1508. /* Settings common to all PCI-express silicon */
  1509. uint32_t reg_ctrl, reg_ctrl_ext;
  1510. uint32_t reg_tarc0, reg_tarc1;
  1511. uint32_t reg_tctl;
  1512. uint32_t reg_txdctl, reg_txdctl1;
  1513. /* link autonegotiation/sync workarounds */
  1514. reg_tarc0 = E1000_READ_REG(hw, TARC0);
  1515. reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  1516. /* Enable not-done TX descriptor counting */
  1517. reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  1518. reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
  1519. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  1520. reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
  1521. reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
  1522. E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
  1523. switch (hw->mac_type) {
  1524. case e1000_igb: /* IGB is cool */
  1525. return;
  1526. case e1000_82571:
  1527. case e1000_82572:
  1528. /* Clear PHY TX compatible mode bits */
  1529. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1530. reg_tarc1 &= ~((1 << 30)|(1 << 29));
  1531. /* link autonegotiation/sync workarounds */
  1532. reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
  1533. /* TX ring control fixes */
  1534. reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
  1535. /* Multiple read bit is reversed polarity */
  1536. reg_tctl = E1000_READ_REG(hw, TCTL);
  1537. if (reg_tctl & E1000_TCTL_MULR)
  1538. reg_tarc1 &= ~(1 << 28);
  1539. else
  1540. reg_tarc1 |= (1 << 28);
  1541. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1542. break;
  1543. case e1000_82573:
  1544. case e1000_82574:
  1545. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1546. reg_ctrl_ext &= ~(1 << 23);
  1547. reg_ctrl_ext |= (1 << 22);
  1548. /* TX byte count fix */
  1549. reg_ctrl = E1000_READ_REG(hw, CTRL);
  1550. reg_ctrl &= ~(1 << 29);
  1551. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1552. E1000_WRITE_REG(hw, CTRL, reg_ctrl);
  1553. break;
  1554. case e1000_80003es2lan:
  1555. /* improve small packet performace for fiber/serdes */
  1556. if ((hw->media_type == e1000_media_type_fiber)
  1557. || (hw->media_type ==
  1558. e1000_media_type_internal_serdes)) {
  1559. reg_tarc0 &= ~(1 << 20);
  1560. }
  1561. /* Multiple read bit is reversed polarity */
  1562. reg_tctl = E1000_READ_REG(hw, TCTL);
  1563. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1564. if (reg_tctl & E1000_TCTL_MULR)
  1565. reg_tarc1 &= ~(1 << 28);
  1566. else
  1567. reg_tarc1 |= (1 << 28);
  1568. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1569. break;
  1570. case e1000_ich8lan:
  1571. /* Reduce concurrent DMA requests to 3 from 4 */
  1572. if ((hw->revision_id < 3) ||
  1573. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1574. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
  1575. reg_tarc0 |= ((1 << 29)|(1 << 28));
  1576. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1577. reg_ctrl_ext |= (1 << 22);
  1578. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1579. /* workaround TX hang with TSO=on */
  1580. reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
  1581. /* Multiple read bit is reversed polarity */
  1582. reg_tctl = E1000_READ_REG(hw, TCTL);
  1583. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1584. if (reg_tctl & E1000_TCTL_MULR)
  1585. reg_tarc1 &= ~(1 << 28);
  1586. else
  1587. reg_tarc1 |= (1 << 28);
  1588. /* workaround TX hang with TSO=on */
  1589. reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
  1590. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1591. break;
  1592. default:
  1593. break;
  1594. }
  1595. E1000_WRITE_REG(hw, TARC0, reg_tarc0);
  1596. }
  1597. }
  1598. /******************************************************************************
  1599. * Performs basic configuration of the adapter.
  1600. *
  1601. * hw - Struct containing variables accessed by shared code
  1602. *
  1603. * Assumes that the controller has previously been reset and is in a
  1604. * post-reset uninitialized state. Initializes the receive address registers,
  1605. * multicast table, and VLAN filter table. Calls routines to setup link
  1606. * configuration and flow control settings. Clears all on-chip counters. Leaves
  1607. * the transmit and receive units disabled and uninitialized.
  1608. *****************************************************************************/
  1609. static int
  1610. e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
  1611. {
  1612. uint32_t ctrl;
  1613. uint32_t i;
  1614. int32_t ret_val;
  1615. uint16_t pcix_cmd_word;
  1616. uint16_t pcix_stat_hi_word;
  1617. uint16_t cmd_mmrbc;
  1618. uint16_t stat_mmrbc;
  1619. uint32_t mta_size;
  1620. uint32_t reg_data;
  1621. uint32_t ctrl_ext;
  1622. DEBUGFUNC();
  1623. /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
  1624. if ((hw->mac_type == e1000_ich8lan) &&
  1625. ((hw->revision_id < 3) ||
  1626. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1627. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
  1628. reg_data = E1000_READ_REG(hw, STATUS);
  1629. reg_data &= ~0x80000000;
  1630. E1000_WRITE_REG(hw, STATUS, reg_data);
  1631. }
  1632. /* Do not need initialize Identification LED */
  1633. /* Set the media type and TBI compatibility */
  1634. e1000_set_media_type(hw);
  1635. /* Must be called after e1000_set_media_type
  1636. * because media_type is used */
  1637. e1000_initialize_hardware_bits(hw);
  1638. /* Disabling VLAN filtering. */
  1639. DEBUGOUT("Initializing the IEEE VLAN\n");
  1640. /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
  1641. if (hw->mac_type != e1000_ich8lan) {
  1642. if (hw->mac_type < e1000_82545_rev_3)
  1643. E1000_WRITE_REG(hw, VET, 0);
  1644. e1000_clear_vfta(hw);
  1645. }
  1646. /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  1647. if (hw->mac_type == e1000_82542_rev2_0) {
  1648. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1649. #ifdef CONFIG_DM_ETH
  1650. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1651. hw->
  1652. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1653. #else
  1654. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1655. hw->
  1656. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1657. #endif
  1658. E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
  1659. E1000_WRITE_FLUSH(hw);
  1660. mdelay(5);
  1661. }
  1662. /* Setup the receive address. This involves initializing all of the Receive
  1663. * Address Registers (RARs 0 - 15).
  1664. */
  1665. e1000_init_rx_addrs(hw, enetaddr);
  1666. /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  1667. if (hw->mac_type == e1000_82542_rev2_0) {
  1668. E1000_WRITE_REG(hw, RCTL, 0);
  1669. E1000_WRITE_FLUSH(hw);
  1670. mdelay(1);
  1671. #ifdef CONFIG_DM_ETH
  1672. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1673. #else
  1674. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1675. #endif
  1676. }
  1677. /* Zero out the Multicast HASH table */
  1678. DEBUGOUT("Zeroing the MTA\n");
  1679. mta_size = E1000_MC_TBL_SIZE;
  1680. if (hw->mac_type == e1000_ich8lan)
  1681. mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
  1682. for (i = 0; i < mta_size; i++) {
  1683. E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  1684. /* use write flush to prevent Memory Write Block (MWB) from
  1685. * occuring when accessing our register space */
  1686. E1000_WRITE_FLUSH(hw);
  1687. }
  1688. switch (hw->mac_type) {
  1689. case e1000_82545_rev_3:
  1690. case e1000_82546_rev_3:
  1691. case e1000_igb:
  1692. break;
  1693. default:
  1694. /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  1695. if (hw->bus_type == e1000_bus_type_pcix) {
  1696. #ifdef CONFIG_DM_ETH
  1697. dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1698. &pcix_cmd_word);
  1699. dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1700. &pcix_stat_hi_word);
  1701. #else
  1702. pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1703. &pcix_cmd_word);
  1704. pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1705. &pcix_stat_hi_word);
  1706. #endif
  1707. cmd_mmrbc =
  1708. (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
  1709. PCIX_COMMAND_MMRBC_SHIFT;
  1710. stat_mmrbc =
  1711. (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
  1712. PCIX_STATUS_HI_MMRBC_SHIFT;
  1713. if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
  1714. stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  1715. if (cmd_mmrbc > stat_mmrbc) {
  1716. pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
  1717. pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
  1718. #ifdef CONFIG_DM_ETH
  1719. dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1720. pcix_cmd_word);
  1721. #else
  1722. pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1723. pcix_cmd_word);
  1724. #endif
  1725. }
  1726. }
  1727. break;
  1728. }
  1729. /* More time needed for PHY to initialize */
  1730. if (hw->mac_type == e1000_ich8lan)
  1731. mdelay(15);
  1732. if (hw->mac_type == e1000_igb)
  1733. mdelay(15);
  1734. /* Call a subroutine to configure the link and setup flow control. */
  1735. ret_val = e1000_setup_link(hw);
  1736. /* Set the transmit descriptor write-back policy */
  1737. if (hw->mac_type > e1000_82544) {
  1738. ctrl = E1000_READ_REG(hw, TXDCTL);
  1739. ctrl =
  1740. (ctrl & ~E1000_TXDCTL_WTHRESH) |
  1741. E1000_TXDCTL_FULL_TX_DESC_WB;
  1742. E1000_WRITE_REG(hw, TXDCTL, ctrl);
  1743. }
  1744. /* Set the receive descriptor write back policy */
  1745. if (hw->mac_type >= e1000_82571) {
  1746. ctrl = E1000_READ_REG(hw, RXDCTL);
  1747. ctrl =
  1748. (ctrl & ~E1000_RXDCTL_WTHRESH) |
  1749. E1000_RXDCTL_FULL_RX_DESC_WB;
  1750. E1000_WRITE_REG(hw, RXDCTL, ctrl);
  1751. }
  1752. switch (hw->mac_type) {
  1753. default:
  1754. break;
  1755. case e1000_80003es2lan:
  1756. /* Enable retransmit on late collisions */
  1757. reg_data = E1000_READ_REG(hw, TCTL);
  1758. reg_data |= E1000_TCTL_RTLC;
  1759. E1000_WRITE_REG(hw, TCTL, reg_data);
  1760. /* Configure Gigabit Carry Extend Padding */
  1761. reg_data = E1000_READ_REG(hw, TCTL_EXT);
  1762. reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  1763. reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
  1764. E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
  1765. /* Configure Transmit Inter-Packet Gap */
  1766. reg_data = E1000_READ_REG(hw, TIPG);
  1767. reg_data &= ~E1000_TIPG_IPGT_MASK;
  1768. reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  1769. E1000_WRITE_REG(hw, TIPG, reg_data);
  1770. reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
  1771. reg_data &= ~0x00100000;
  1772. E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
  1773. /* Fall through */
  1774. case e1000_82571:
  1775. case e1000_82572:
  1776. case e1000_ich8lan:
  1777. ctrl = E1000_READ_REG(hw, TXDCTL1);
  1778. ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
  1779. | E1000_TXDCTL_FULL_TX_DESC_WB;
  1780. E1000_WRITE_REG(hw, TXDCTL1, ctrl);
  1781. break;
  1782. case e1000_82573:
  1783. case e1000_82574:
  1784. reg_data = E1000_READ_REG(hw, GCR);
  1785. reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
  1786. E1000_WRITE_REG(hw, GCR, reg_data);
  1787. case e1000_igb:
  1788. break;
  1789. }
  1790. if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
  1791. hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
  1792. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1793. /* Relaxed ordering must be disabled to avoid a parity
  1794. * error crash in a PCI slot. */
  1795. ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  1796. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1797. }
  1798. return ret_val;
  1799. }
  1800. /******************************************************************************
  1801. * Configures flow control and link settings.
  1802. *
  1803. * hw - Struct containing variables accessed by shared code
  1804. *
  1805. * Determines which flow control settings to use. Calls the apropriate media-
  1806. * specific link configuration function. Configures the flow control settings.
  1807. * Assuming the adapter has a valid link partner, a valid link should be
  1808. * established. Assumes the hardware has previously been reset and the
  1809. * transmitter and receiver are not enabled.
  1810. *****************************************************************************/
  1811. static int
  1812. e1000_setup_link(struct e1000_hw *hw)
  1813. {
  1814. int32_t ret_val;
  1815. #ifndef CONFIG_E1000_NO_NVM
  1816. uint32_t ctrl_ext;
  1817. uint16_t eeprom_data;
  1818. #endif
  1819. DEBUGFUNC();
  1820. /* In the case of the phy reset being blocked, we already have a link.
  1821. * We do not have to set it up again. */
  1822. if (e1000_check_phy_reset_block(hw))
  1823. return E1000_SUCCESS;
  1824. #ifndef CONFIG_E1000_NO_NVM
  1825. /* Read and store word 0x0F of the EEPROM. This word contains bits
  1826. * that determine the hardware's default PAUSE (flow control) mode,
  1827. * a bit that determines whether the HW defaults to enabling or
  1828. * disabling auto-negotiation, and the direction of the
  1829. * SW defined pins. If there is no SW over-ride of the flow
  1830. * control setting, then the variable hw->fc will
  1831. * be initialized based on a value in the EEPROM.
  1832. */
  1833. if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
  1834. &eeprom_data) < 0) {
  1835. DEBUGOUT("EEPROM Read Error\n");
  1836. return -E1000_ERR_EEPROM;
  1837. }
  1838. #endif
  1839. if (hw->fc == e1000_fc_default) {
  1840. switch (hw->mac_type) {
  1841. case e1000_ich8lan:
  1842. case e1000_82573:
  1843. case e1000_82574:
  1844. case e1000_igb:
  1845. hw->fc = e1000_fc_full;
  1846. break;
  1847. default:
  1848. #ifndef CONFIG_E1000_NO_NVM
  1849. ret_val = e1000_read_eeprom(hw,
  1850. EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
  1851. if (ret_val) {
  1852. DEBUGOUT("EEPROM Read Error\n");
  1853. return -E1000_ERR_EEPROM;
  1854. }
  1855. if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
  1856. hw->fc = e1000_fc_none;
  1857. else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
  1858. EEPROM_WORD0F_ASM_DIR)
  1859. hw->fc = e1000_fc_tx_pause;
  1860. else
  1861. #endif
  1862. hw->fc = e1000_fc_full;
  1863. break;
  1864. }
  1865. }
  1866. /* We want to save off the original Flow Control configuration just
  1867. * in case we get disconnected and then reconnected into a different
  1868. * hub or switch with different Flow Control capabilities.
  1869. */
  1870. if (hw->mac_type == e1000_82542_rev2_0)
  1871. hw->fc &= (~e1000_fc_tx_pause);
  1872. if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
  1873. hw->fc &= (~e1000_fc_rx_pause);
  1874. hw->original_fc = hw->fc;
  1875. DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
  1876. #ifndef CONFIG_E1000_NO_NVM
  1877. /* Take the 4 bits from EEPROM word 0x0F that determine the initial
  1878. * polarity value for the SW controlled pins, and setup the
  1879. * Extended Device Control reg with that info.
  1880. * This is needed because one of the SW controlled pins is used for
  1881. * signal detection. So this should be done before e1000_setup_pcs_link()
  1882. * or e1000_phy_setup() is called.
  1883. */
  1884. if (hw->mac_type == e1000_82543) {
  1885. ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
  1886. SWDPIO__EXT_SHIFT);
  1887. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1888. }
  1889. #endif
  1890. /* Call the necessary subroutine to configure the link. */
  1891. ret_val = (hw->media_type == e1000_media_type_fiber) ?
  1892. e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
  1893. if (ret_val < 0) {
  1894. return ret_val;
  1895. }
  1896. /* Initialize the flow control address, type, and PAUSE timer
  1897. * registers to their default values. This is done even if flow
  1898. * control is disabled, because it does not hurt anything to
  1899. * initialize these registers.
  1900. */
  1901. DEBUGOUT("Initializing the Flow Control address, type"
  1902. "and timer regs\n");
  1903. /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
  1904. if (hw->mac_type != e1000_ich8lan) {
  1905. E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
  1906. E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  1907. E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
  1908. }
  1909. E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
  1910. /* Set the flow control receive threshold registers. Normally,
  1911. * these registers will be set to a default threshold that may be
  1912. * adjusted later by the driver's runtime code. However, if the
  1913. * ability to transmit pause frames in not enabled, then these
  1914. * registers will be set to 0.
  1915. */
  1916. if (!(hw->fc & e1000_fc_tx_pause)) {
  1917. E1000_WRITE_REG(hw, FCRTL, 0);
  1918. E1000_WRITE_REG(hw, FCRTH, 0);
  1919. } else {
  1920. /* We need to set up the Receive Threshold high and low water marks
  1921. * as well as (optionally) enabling the transmission of XON frames.
  1922. */
  1923. if (hw->fc_send_xon) {
  1924. E1000_WRITE_REG(hw, FCRTL,
  1925. (hw->fc_low_water | E1000_FCRTL_XONE));
  1926. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1927. } else {
  1928. E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
  1929. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1930. }
  1931. }
  1932. return ret_val;
  1933. }
  1934. /******************************************************************************
  1935. * Sets up link for a fiber based adapter
  1936. *
  1937. * hw - Struct containing variables accessed by shared code
  1938. *
  1939. * Manipulates Physical Coding Sublayer functions in order to configure
  1940. * link. Assumes the hardware has been previously reset and the transmitter
  1941. * and receiver are not enabled.
  1942. *****************************************************************************/
  1943. static int
  1944. e1000_setup_fiber_link(struct e1000_hw *hw)
  1945. {
  1946. uint32_t ctrl;
  1947. uint32_t status;
  1948. uint32_t txcw = 0;
  1949. uint32_t i;
  1950. uint32_t signal;
  1951. int32_t ret_val;
  1952. DEBUGFUNC();
  1953. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  1954. * set when the optics detect a signal. On older adapters, it will be
  1955. * cleared when there is a signal
  1956. */
  1957. ctrl = E1000_READ_REG(hw, CTRL);
  1958. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  1959. signal = E1000_CTRL_SWDPIN1;
  1960. else
  1961. signal = 0;
  1962. printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
  1963. ctrl);
  1964. /* Take the link out of reset */
  1965. ctrl &= ~(E1000_CTRL_LRST);
  1966. e1000_config_collision_dist(hw);
  1967. /* Check for a software override of the flow control settings, and setup
  1968. * the device accordingly. If auto-negotiation is enabled, then software
  1969. * will have to set the "PAUSE" bits to the correct value in the Tranmsit
  1970. * Config Word Register (TXCW) and re-start auto-negotiation. However, if
  1971. * auto-negotiation is disabled, then software will have to manually
  1972. * configure the two flow control enable bits in the CTRL register.
  1973. *
  1974. * The possible values of the "fc" parameter are:
  1975. * 0: Flow control is completely disabled
  1976. * 1: Rx flow control is enabled (we can receive pause frames, but
  1977. * not send pause frames).
  1978. * 2: Tx flow control is enabled (we can send pause frames but we do
  1979. * not support receiving pause frames).
  1980. * 3: Both Rx and TX flow control (symmetric) are enabled.
  1981. */
  1982. switch (hw->fc) {
  1983. case e1000_fc_none:
  1984. /* Flow control is completely disabled by a software over-ride. */
  1985. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
  1986. break;
  1987. case e1000_fc_rx_pause:
  1988. /* RX Flow control is enabled and TX Flow control is disabled by a
  1989. * software over-ride. Since there really isn't a way to advertise
  1990. * that we are capable of RX Pause ONLY, we will advertise that we
  1991. * support both symmetric and asymmetric RX PAUSE. Later, we will
  1992. * disable the adapter's ability to send PAUSE frames.
  1993. */
  1994. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  1995. break;
  1996. case e1000_fc_tx_pause:
  1997. /* TX Flow control is enabled, and RX Flow control is disabled, by a
  1998. * software over-ride.
  1999. */
  2000. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
  2001. break;
  2002. case e1000_fc_full:
  2003. /* Flow control (both RX and TX) is enabled by a software over-ride. */
  2004. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  2005. break;
  2006. default:
  2007. DEBUGOUT("Flow control param set incorrectly\n");
  2008. return -E1000_ERR_CONFIG;
  2009. break;
  2010. }
  2011. /* Since auto-negotiation is enabled, take the link out of reset (the link
  2012. * will be in reset, because we previously reset the chip). This will
  2013. * restart auto-negotiation. If auto-neogtiation is successful then the
  2014. * link-up status bit will be set and the flow control enable bits (RFCE
  2015. * and TFCE) will be set according to their negotiated value.
  2016. */
  2017. DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
  2018. E1000_WRITE_REG(hw, TXCW, txcw);
  2019. E1000_WRITE_REG(hw, CTRL, ctrl);
  2020. E1000_WRITE_FLUSH(hw);
  2021. hw->txcw = txcw;
  2022. mdelay(1);
  2023. /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
  2024. * indication in the Device Status Register. Time-out if a link isn't
  2025. * seen in 500 milliseconds seconds (Auto-negotiation should complete in
  2026. * less than 500 milliseconds even if the other end is doing it in SW).
  2027. */
  2028. if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
  2029. DEBUGOUT("Looking for Link\n");
  2030. for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
  2031. mdelay(10);
  2032. status = E1000_READ_REG(hw, STATUS);
  2033. if (status & E1000_STATUS_LU)
  2034. break;
  2035. }
  2036. if (i == (LINK_UP_TIMEOUT / 10)) {
  2037. /* AutoNeg failed to achieve a link, so we'll call
  2038. * e1000_check_for_link. This routine will force the link up if we
  2039. * detect a signal. This will allow us to communicate with
  2040. * non-autonegotiating link partners.
  2041. */
  2042. DEBUGOUT("Never got a valid link from auto-neg!!!\n");
  2043. hw->autoneg_failed = 1;
  2044. ret_val = e1000_check_for_link(hw);
  2045. if (ret_val < 0) {
  2046. DEBUGOUT("Error while checking for link\n");
  2047. return ret_val;
  2048. }
  2049. hw->autoneg_failed = 0;
  2050. } else {
  2051. hw->autoneg_failed = 0;
  2052. DEBUGOUT("Valid Link Found\n");
  2053. }
  2054. } else {
  2055. DEBUGOUT("No Signal Detected\n");
  2056. return -E1000_ERR_NOLINK;
  2057. }
  2058. return 0;
  2059. }
  2060. /******************************************************************************
  2061. * Make sure we have a valid PHY and change PHY mode before link setup.
  2062. *
  2063. * hw - Struct containing variables accessed by shared code
  2064. ******************************************************************************/
  2065. static int32_t
  2066. e1000_copper_link_preconfig(struct e1000_hw *hw)
  2067. {
  2068. uint32_t ctrl;
  2069. int32_t ret_val;
  2070. uint16_t phy_data;
  2071. DEBUGFUNC();
  2072. ctrl = E1000_READ_REG(hw, CTRL);
  2073. /* With 82543, we need to force speed and duplex on the MAC equal to what
  2074. * the PHY speed and duplex configuration is. In addition, we need to
  2075. * perform a hardware reset on the PHY to take it out of reset.
  2076. */
  2077. if (hw->mac_type > e1000_82543) {
  2078. ctrl |= E1000_CTRL_SLU;
  2079. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  2080. E1000_WRITE_REG(hw, CTRL, ctrl);
  2081. } else {
  2082. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
  2083. | E1000_CTRL_SLU);
  2084. E1000_WRITE_REG(hw, CTRL, ctrl);
  2085. ret_val = e1000_phy_hw_reset(hw);
  2086. if (ret_val)
  2087. return ret_val;
  2088. }
  2089. /* Make sure we have a valid PHY */
  2090. ret_val = e1000_detect_gig_phy(hw);
  2091. if (ret_val) {
  2092. DEBUGOUT("Error, did not detect valid phy.\n");
  2093. return ret_val;
  2094. }
  2095. DEBUGOUT("Phy ID = %x\n", hw->phy_id);
  2096. /* Set PHY to class A mode (if necessary) */
  2097. ret_val = e1000_set_phy_mode(hw);
  2098. if (ret_val)
  2099. return ret_val;
  2100. if ((hw->mac_type == e1000_82545_rev_3) ||
  2101. (hw->mac_type == e1000_82546_rev_3)) {
  2102. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2103. &phy_data);
  2104. phy_data |= 0x00000008;
  2105. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2106. phy_data);
  2107. }
  2108. if (hw->mac_type <= e1000_82543 ||
  2109. hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
  2110. hw->mac_type == e1000_82541_rev_2
  2111. || hw->mac_type == e1000_82547_rev_2)
  2112. hw->phy_reset_disable = false;
  2113. return E1000_SUCCESS;
  2114. }
  2115. /*****************************************************************************
  2116. *
  2117. * This function sets the lplu state according to the active flag. When
  2118. * activating lplu this function also disables smart speed and vise versa.
  2119. * lplu will not be activated unless the device autonegotiation advertisment
  2120. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2121. * hw: Struct containing variables accessed by shared code
  2122. * active - true to enable lplu false to disable lplu.
  2123. *
  2124. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2125. * E1000_SUCCESS at any other case.
  2126. *
  2127. ****************************************************************************/
  2128. static int32_t
  2129. e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
  2130. {
  2131. uint32_t phy_ctrl = 0;
  2132. int32_t ret_val;
  2133. uint16_t phy_data;
  2134. DEBUGFUNC();
  2135. if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
  2136. && hw->phy_type != e1000_phy_igp_3)
  2137. return E1000_SUCCESS;
  2138. /* During driver activity LPLU should not be used or it will attain link
  2139. * from the lowest speeds starting from 10Mbps. The capability is used
  2140. * for Dx transitions and states */
  2141. if (hw->mac_type == e1000_82541_rev_2
  2142. || hw->mac_type == e1000_82547_rev_2) {
  2143. ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2144. &phy_data);
  2145. if (ret_val)
  2146. return ret_val;
  2147. } else if (hw->mac_type == e1000_ich8lan) {
  2148. /* MAC writes into PHY register based on the state transition
  2149. * and start auto-negotiation. SW driver can overwrite the
  2150. * settings in CSR PHY power control E1000_PHY_CTRL register. */
  2151. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2152. } else {
  2153. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2154. &phy_data);
  2155. if (ret_val)
  2156. return ret_val;
  2157. }
  2158. if (!active) {
  2159. if (hw->mac_type == e1000_82541_rev_2 ||
  2160. hw->mac_type == e1000_82547_rev_2) {
  2161. phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
  2162. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2163. phy_data);
  2164. if (ret_val)
  2165. return ret_val;
  2166. } else {
  2167. if (hw->mac_type == e1000_ich8lan) {
  2168. phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
  2169. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2170. } else {
  2171. phy_data &= ~IGP02E1000_PM_D3_LPLU;
  2172. ret_val = e1000_write_phy_reg(hw,
  2173. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2174. if (ret_val)
  2175. return ret_val;
  2176. }
  2177. }
  2178. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2179. * Dx states where the power conservation is most important. During
  2180. * driver activity we should enable SmartSpeed, so performance is
  2181. * maintained. */
  2182. if (hw->smart_speed == e1000_smart_speed_on) {
  2183. ret_val = e1000_read_phy_reg(hw,
  2184. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2185. if (ret_val)
  2186. return ret_val;
  2187. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2188. ret_val = e1000_write_phy_reg(hw,
  2189. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2190. if (ret_val)
  2191. return ret_val;
  2192. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2193. ret_val = e1000_read_phy_reg(hw,
  2194. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2195. if (ret_val)
  2196. return ret_val;
  2197. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2198. ret_val = e1000_write_phy_reg(hw,
  2199. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2200. if (ret_val)
  2201. return ret_val;
  2202. }
  2203. } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
  2204. || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
  2205. (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
  2206. if (hw->mac_type == e1000_82541_rev_2 ||
  2207. hw->mac_type == e1000_82547_rev_2) {
  2208. phy_data |= IGP01E1000_GMII_FLEX_SPD;
  2209. ret_val = e1000_write_phy_reg(hw,
  2210. IGP01E1000_GMII_FIFO, phy_data);
  2211. if (ret_val)
  2212. return ret_val;
  2213. } else {
  2214. if (hw->mac_type == e1000_ich8lan) {
  2215. phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
  2216. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2217. } else {
  2218. phy_data |= IGP02E1000_PM_D3_LPLU;
  2219. ret_val = e1000_write_phy_reg(hw,
  2220. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2221. if (ret_val)
  2222. return ret_val;
  2223. }
  2224. }
  2225. /* When LPLU is enabled we should disable SmartSpeed */
  2226. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2227. &phy_data);
  2228. if (ret_val)
  2229. return ret_val;
  2230. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2231. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2232. phy_data);
  2233. if (ret_val)
  2234. return ret_val;
  2235. }
  2236. return E1000_SUCCESS;
  2237. }
  2238. /*****************************************************************************
  2239. *
  2240. * This function sets the lplu d0 state according to the active flag. When
  2241. * activating lplu this function also disables smart speed and vise versa.
  2242. * lplu will not be activated unless the device autonegotiation advertisment
  2243. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2244. * hw: Struct containing variables accessed by shared code
  2245. * active - true to enable lplu false to disable lplu.
  2246. *
  2247. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2248. * E1000_SUCCESS at any other case.
  2249. *
  2250. ****************************************************************************/
  2251. static int32_t
  2252. e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
  2253. {
  2254. uint32_t phy_ctrl = 0;
  2255. int32_t ret_val;
  2256. uint16_t phy_data;
  2257. DEBUGFUNC();
  2258. if (hw->mac_type <= e1000_82547_rev_2)
  2259. return E1000_SUCCESS;
  2260. if (hw->mac_type == e1000_ich8lan) {
  2261. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2262. } else if (hw->mac_type == e1000_igb) {
  2263. phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
  2264. } else {
  2265. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2266. &phy_data);
  2267. if (ret_val)
  2268. return ret_val;
  2269. }
  2270. if (!active) {
  2271. if (hw->mac_type == e1000_ich8lan) {
  2272. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2273. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2274. } else if (hw->mac_type == e1000_igb) {
  2275. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2276. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2277. } else {
  2278. phy_data &= ~IGP02E1000_PM_D0_LPLU;
  2279. ret_val = e1000_write_phy_reg(hw,
  2280. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2281. if (ret_val)
  2282. return ret_val;
  2283. }
  2284. if (hw->mac_type == e1000_igb)
  2285. return E1000_SUCCESS;
  2286. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2287. * Dx states where the power conservation is most important. During
  2288. * driver activity we should enable SmartSpeed, so performance is
  2289. * maintained. */
  2290. if (hw->smart_speed == e1000_smart_speed_on) {
  2291. ret_val = e1000_read_phy_reg(hw,
  2292. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2293. if (ret_val)
  2294. return ret_val;
  2295. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2296. ret_val = e1000_write_phy_reg(hw,
  2297. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2298. if (ret_val)
  2299. return ret_val;
  2300. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2301. ret_val = e1000_read_phy_reg(hw,
  2302. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2303. if (ret_val)
  2304. return ret_val;
  2305. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2306. ret_val = e1000_write_phy_reg(hw,
  2307. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2308. if (ret_val)
  2309. return ret_val;
  2310. }
  2311. } else {
  2312. if (hw->mac_type == e1000_ich8lan) {
  2313. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2314. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2315. } else if (hw->mac_type == e1000_igb) {
  2316. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2317. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2318. } else {
  2319. phy_data |= IGP02E1000_PM_D0_LPLU;
  2320. ret_val = e1000_write_phy_reg(hw,
  2321. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2322. if (ret_val)
  2323. return ret_val;
  2324. }
  2325. if (hw->mac_type == e1000_igb)
  2326. return E1000_SUCCESS;
  2327. /* When LPLU is enabled we should disable SmartSpeed */
  2328. ret_val = e1000_read_phy_reg(hw,
  2329. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2330. if (ret_val)
  2331. return ret_val;
  2332. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2333. ret_val = e1000_write_phy_reg(hw,
  2334. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2335. if (ret_val)
  2336. return ret_val;
  2337. }
  2338. return E1000_SUCCESS;
  2339. }
  2340. /********************************************************************
  2341. * Copper link setup for e1000_phy_igp series.
  2342. *
  2343. * hw - Struct containing variables accessed by shared code
  2344. *********************************************************************/
  2345. static int32_t
  2346. e1000_copper_link_igp_setup(struct e1000_hw *hw)
  2347. {
  2348. uint32_t led_ctrl;
  2349. int32_t ret_val;
  2350. uint16_t phy_data;
  2351. DEBUGFUNC();
  2352. if (hw->phy_reset_disable)
  2353. return E1000_SUCCESS;
  2354. ret_val = e1000_phy_reset(hw);
  2355. if (ret_val) {
  2356. DEBUGOUT("Error Resetting the PHY\n");
  2357. return ret_val;
  2358. }
  2359. /* Wait 15ms for MAC to configure PHY from eeprom settings */
  2360. mdelay(15);
  2361. if (hw->mac_type != e1000_ich8lan) {
  2362. /* Configure activity LED after PHY reset */
  2363. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  2364. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  2365. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  2366. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  2367. }
  2368. /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
  2369. if (hw->phy_type == e1000_phy_igp) {
  2370. /* disable lplu d3 during driver init */
  2371. ret_val = e1000_set_d3_lplu_state(hw, false);
  2372. if (ret_val) {
  2373. DEBUGOUT("Error Disabling LPLU D3\n");
  2374. return ret_val;
  2375. }
  2376. }
  2377. /* disable lplu d0 during driver init */
  2378. ret_val = e1000_set_d0_lplu_state(hw, false);
  2379. if (ret_val) {
  2380. DEBUGOUT("Error Disabling LPLU D0\n");
  2381. return ret_val;
  2382. }
  2383. /* Configure mdi-mdix settings */
  2384. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  2385. if (ret_val)
  2386. return ret_val;
  2387. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  2388. hw->dsp_config_state = e1000_dsp_config_disabled;
  2389. /* Force MDI for earlier revs of the IGP PHY */
  2390. phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
  2391. | IGP01E1000_PSCR_FORCE_MDI_MDIX);
  2392. hw->mdix = 1;
  2393. } else {
  2394. hw->dsp_config_state = e1000_dsp_config_enabled;
  2395. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  2396. switch (hw->mdix) {
  2397. case 1:
  2398. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2399. break;
  2400. case 2:
  2401. phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2402. break;
  2403. case 0:
  2404. default:
  2405. phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
  2406. break;
  2407. }
  2408. }
  2409. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  2410. if (ret_val)
  2411. return ret_val;
  2412. /* set auto-master slave resolution settings */
  2413. if (hw->autoneg) {
  2414. e1000_ms_type phy_ms_setting = hw->master_slave;
  2415. if (hw->ffe_config_state == e1000_ffe_config_active)
  2416. hw->ffe_config_state = e1000_ffe_config_enabled;
  2417. if (hw->dsp_config_state == e1000_dsp_config_activated)
  2418. hw->dsp_config_state = e1000_dsp_config_enabled;
  2419. /* when autonegotiation advertisment is only 1000Mbps then we
  2420. * should disable SmartSpeed and enable Auto MasterSlave
  2421. * resolution as hardware default. */
  2422. if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
  2423. /* Disable SmartSpeed */
  2424. ret_val = e1000_read_phy_reg(hw,
  2425. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2426. if (ret_val)
  2427. return ret_val;
  2428. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2429. ret_val = e1000_write_phy_reg(hw,
  2430. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2431. if (ret_val)
  2432. return ret_val;
  2433. /* Set auto Master/Slave resolution process */
  2434. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2435. &phy_data);
  2436. if (ret_val)
  2437. return ret_val;
  2438. phy_data &= ~CR_1000T_MS_ENABLE;
  2439. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  2440. phy_data);
  2441. if (ret_val)
  2442. return ret_val;
  2443. }
  2444. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
  2445. if (ret_val)
  2446. return ret_val;
  2447. /* load defaults for future use */
  2448. hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
  2449. ((phy_data & CR_1000T_MS_VALUE) ?
  2450. e1000_ms_force_master :
  2451. e1000_ms_force_slave) :
  2452. e1000_ms_auto;
  2453. switch (phy_ms_setting) {
  2454. case e1000_ms_force_master:
  2455. phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  2456. break;
  2457. case e1000_ms_force_slave:
  2458. phy_data |= CR_1000T_MS_ENABLE;
  2459. phy_data &= ~(CR_1000T_MS_VALUE);
  2460. break;
  2461. case e1000_ms_auto:
  2462. phy_data &= ~CR_1000T_MS_ENABLE;
  2463. default:
  2464. break;
  2465. }
  2466. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
  2467. if (ret_val)
  2468. return ret_val;
  2469. }
  2470. return E1000_SUCCESS;
  2471. }
  2472. /*****************************************************************************
  2473. * This function checks the mode of the firmware.
  2474. *
  2475. * returns - true when the mode is IAMT or false.
  2476. ****************************************************************************/
  2477. bool
  2478. e1000_check_mng_mode(struct e1000_hw *hw)
  2479. {
  2480. uint32_t fwsm;
  2481. DEBUGFUNC();
  2482. fwsm = E1000_READ_REG(hw, FWSM);
  2483. if (hw->mac_type == e1000_ich8lan) {
  2484. if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2485. (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2486. return true;
  2487. } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2488. (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2489. return true;
  2490. return false;
  2491. }
  2492. static int32_t
  2493. e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
  2494. {
  2495. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2496. uint32_t reg_val;
  2497. DEBUGFUNC();
  2498. if (e1000_is_second_port(hw))
  2499. swfw = E1000_SWFW_PHY1_SM;
  2500. if (e1000_swfw_sync_acquire(hw, swfw))
  2501. return -E1000_ERR_SWFW_SYNC;
  2502. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
  2503. & E1000_KUMCTRLSTA_OFFSET) | data;
  2504. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2505. udelay(2);
  2506. return E1000_SUCCESS;
  2507. }
  2508. static int32_t
  2509. e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
  2510. {
  2511. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2512. uint32_t reg_val;
  2513. DEBUGFUNC();
  2514. if (e1000_is_second_port(hw))
  2515. swfw = E1000_SWFW_PHY1_SM;
  2516. if (e1000_swfw_sync_acquire(hw, swfw)) {
  2517. debug("%s[%i]\n", __func__, __LINE__);
  2518. return -E1000_ERR_SWFW_SYNC;
  2519. }
  2520. /* Write register address */
  2521. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
  2522. E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
  2523. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2524. udelay(2);
  2525. /* Read the data returned */
  2526. reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
  2527. *data = (uint16_t)reg_val;
  2528. return E1000_SUCCESS;
  2529. }
  2530. /********************************************************************
  2531. * Copper link setup for e1000_phy_gg82563 series.
  2532. *
  2533. * hw - Struct containing variables accessed by shared code
  2534. *********************************************************************/
  2535. static int32_t
  2536. e1000_copper_link_ggp_setup(struct e1000_hw *hw)
  2537. {
  2538. int32_t ret_val;
  2539. uint16_t phy_data;
  2540. uint32_t reg_data;
  2541. DEBUGFUNC();
  2542. if (!hw->phy_reset_disable) {
  2543. /* Enable CRS on TX for half-duplex operation. */
  2544. ret_val = e1000_read_phy_reg(hw,
  2545. GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  2546. if (ret_val)
  2547. return ret_val;
  2548. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  2549. /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
  2550. phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
  2551. ret_val = e1000_write_phy_reg(hw,
  2552. GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  2553. if (ret_val)
  2554. return ret_val;
  2555. /* Options:
  2556. * MDI/MDI-X = 0 (default)
  2557. * 0 - Auto for all speeds
  2558. * 1 - MDI mode
  2559. * 2 - MDI-X mode
  2560. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2561. */
  2562. ret_val = e1000_read_phy_reg(hw,
  2563. GG82563_PHY_SPEC_CTRL, &phy_data);
  2564. if (ret_val)
  2565. return ret_val;
  2566. phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  2567. switch (hw->mdix) {
  2568. case 1:
  2569. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  2570. break;
  2571. case 2:
  2572. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  2573. break;
  2574. case 0:
  2575. default:
  2576. phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  2577. break;
  2578. }
  2579. /* Options:
  2580. * disable_polarity_correction = 0 (default)
  2581. * Automatic Correction for Reversed Cable Polarity
  2582. * 0 - Disabled
  2583. * 1 - Enabled
  2584. */
  2585. phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  2586. ret_val = e1000_write_phy_reg(hw,
  2587. GG82563_PHY_SPEC_CTRL, phy_data);
  2588. if (ret_val)
  2589. return ret_val;
  2590. /* SW Reset the PHY so all changes take effect */
  2591. ret_val = e1000_phy_reset(hw);
  2592. if (ret_val) {
  2593. DEBUGOUT("Error Resetting the PHY\n");
  2594. return ret_val;
  2595. }
  2596. } /* phy_reset_disable */
  2597. if (hw->mac_type == e1000_80003es2lan) {
  2598. /* Bypass RX and TX FIFO's */
  2599. ret_val = e1000_write_kmrn_reg(hw,
  2600. E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
  2601. E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
  2602. | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
  2603. if (ret_val)
  2604. return ret_val;
  2605. ret_val = e1000_read_phy_reg(hw,
  2606. GG82563_PHY_SPEC_CTRL_2, &phy_data);
  2607. if (ret_val)
  2608. return ret_val;
  2609. phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
  2610. ret_val = e1000_write_phy_reg(hw,
  2611. GG82563_PHY_SPEC_CTRL_2, phy_data);
  2612. if (ret_val)
  2613. return ret_val;
  2614. reg_data = E1000_READ_REG(hw, CTRL_EXT);
  2615. reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
  2616. E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
  2617. ret_val = e1000_read_phy_reg(hw,
  2618. GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
  2619. if (ret_val)
  2620. return ret_val;
  2621. /* Do not init these registers when the HW is in IAMT mode, since the
  2622. * firmware will have already initialized them. We only initialize
  2623. * them if the HW is not in IAMT mode.
  2624. */
  2625. if (e1000_check_mng_mode(hw) == false) {
  2626. /* Enable Electrical Idle on the PHY */
  2627. phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
  2628. ret_val = e1000_write_phy_reg(hw,
  2629. GG82563_PHY_PWR_MGMT_CTRL, phy_data);
  2630. if (ret_val)
  2631. return ret_val;
  2632. ret_val = e1000_read_phy_reg(hw,
  2633. GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
  2634. if (ret_val)
  2635. return ret_val;
  2636. phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  2637. ret_val = e1000_write_phy_reg(hw,
  2638. GG82563_PHY_KMRN_MODE_CTRL, phy_data);
  2639. if (ret_val)
  2640. return ret_val;
  2641. }
  2642. /* Workaround: Disable padding in Kumeran interface in the MAC
  2643. * and in the PHY to avoid CRC errors.
  2644. */
  2645. ret_val = e1000_read_phy_reg(hw,
  2646. GG82563_PHY_INBAND_CTRL, &phy_data);
  2647. if (ret_val)
  2648. return ret_val;
  2649. phy_data |= GG82563_ICR_DIS_PADDING;
  2650. ret_val = e1000_write_phy_reg(hw,
  2651. GG82563_PHY_INBAND_CTRL, phy_data);
  2652. if (ret_val)
  2653. return ret_val;
  2654. }
  2655. return E1000_SUCCESS;
  2656. }
  2657. /********************************************************************
  2658. * Copper link setup for e1000_phy_m88 series.
  2659. *
  2660. * hw - Struct containing variables accessed by shared code
  2661. *********************************************************************/
  2662. static int32_t
  2663. e1000_copper_link_mgp_setup(struct e1000_hw *hw)
  2664. {
  2665. int32_t ret_val;
  2666. uint16_t phy_data;
  2667. DEBUGFUNC();
  2668. if (hw->phy_reset_disable)
  2669. return E1000_SUCCESS;
  2670. /* Enable CRS on TX. This must be set for half-duplex operation. */
  2671. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  2672. if (ret_val)
  2673. return ret_val;
  2674. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  2675. /* Options:
  2676. * MDI/MDI-X = 0 (default)
  2677. * 0 - Auto for all speeds
  2678. * 1 - MDI mode
  2679. * 2 - MDI-X mode
  2680. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2681. */
  2682. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  2683. switch (hw->mdix) {
  2684. case 1:
  2685. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  2686. break;
  2687. case 2:
  2688. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  2689. break;
  2690. case 3:
  2691. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  2692. break;
  2693. case 0:
  2694. default:
  2695. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  2696. break;
  2697. }
  2698. /* Options:
  2699. * disable_polarity_correction = 0 (default)
  2700. * Automatic Correction for Reversed Cable Polarity
  2701. * 0 - Disabled
  2702. * 1 - Enabled
  2703. */
  2704. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  2705. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  2706. if (ret_val)
  2707. return ret_val;
  2708. if (hw->phy_revision < M88E1011_I_REV_4) {
  2709. /* Force TX_CLK in the Extended PHY Specific Control Register
  2710. * to 25MHz clock.
  2711. */
  2712. ret_val = e1000_read_phy_reg(hw,
  2713. M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  2714. if (ret_val)
  2715. return ret_val;
  2716. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  2717. if ((hw->phy_revision == E1000_REVISION_2) &&
  2718. (hw->phy_id == M88E1111_I_PHY_ID)) {
  2719. /* Vidalia Phy, set the downshift counter to 5x */
  2720. phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
  2721. phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  2722. ret_val = e1000_write_phy_reg(hw,
  2723. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2724. if (ret_val)
  2725. return ret_val;
  2726. } else {
  2727. /* Configure Master and Slave downshift values */
  2728. phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
  2729. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  2730. phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
  2731. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  2732. ret_val = e1000_write_phy_reg(hw,
  2733. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2734. if (ret_val)
  2735. return ret_val;
  2736. }
  2737. }
  2738. /* SW Reset the PHY so all changes take effect */
  2739. ret_val = e1000_phy_reset(hw);
  2740. if (ret_val) {
  2741. DEBUGOUT("Error Resetting the PHY\n");
  2742. return ret_val;
  2743. }
  2744. return E1000_SUCCESS;
  2745. }
  2746. /********************************************************************
  2747. * Setup auto-negotiation and flow control advertisements,
  2748. * and then perform auto-negotiation.
  2749. *
  2750. * hw - Struct containing variables accessed by shared code
  2751. *********************************************************************/
  2752. static int32_t
  2753. e1000_copper_link_autoneg(struct e1000_hw *hw)
  2754. {
  2755. int32_t ret_val;
  2756. uint16_t phy_data;
  2757. DEBUGFUNC();
  2758. /* Perform some bounds checking on the hw->autoneg_advertised
  2759. * parameter. If this variable is zero, then set it to the default.
  2760. */
  2761. hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2762. /* If autoneg_advertised is zero, we assume it was not defaulted
  2763. * by the calling code so we set to advertise full capability.
  2764. */
  2765. if (hw->autoneg_advertised == 0)
  2766. hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2767. /* IFE phy only supports 10/100 */
  2768. if (hw->phy_type == e1000_phy_ife)
  2769. hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
  2770. DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  2771. ret_val = e1000_phy_setup_autoneg(hw);
  2772. if (ret_val) {
  2773. DEBUGOUT("Error Setting up Auto-Negotiation\n");
  2774. return ret_val;
  2775. }
  2776. DEBUGOUT("Restarting Auto-Neg\n");
  2777. /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  2778. * the Auto Neg Restart bit in the PHY control register.
  2779. */
  2780. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  2781. if (ret_val)
  2782. return ret_val;
  2783. phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  2784. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  2785. if (ret_val)
  2786. return ret_val;
  2787. /* Does the user want to wait for Auto-Neg to complete here, or
  2788. * check at a later time (for example, callback routine).
  2789. */
  2790. /* If we do not wait for autonegtation to complete I
  2791. * do not see a valid link status.
  2792. * wait_autoneg_complete = 1 .
  2793. */
  2794. if (hw->wait_autoneg_complete) {
  2795. ret_val = e1000_wait_autoneg(hw);
  2796. if (ret_val) {
  2797. DEBUGOUT("Error while waiting for autoneg"
  2798. "to complete\n");
  2799. return ret_val;
  2800. }
  2801. }
  2802. hw->get_link_status = true;
  2803. return E1000_SUCCESS;
  2804. }
  2805. /******************************************************************************
  2806. * Config the MAC and the PHY after link is up.
  2807. * 1) Set up the MAC to the current PHY speed/duplex
  2808. * if we are on 82543. If we
  2809. * are on newer silicon, we only need to configure
  2810. * collision distance in the Transmit Control Register.
  2811. * 2) Set up flow control on the MAC to that established with
  2812. * the link partner.
  2813. * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
  2814. *
  2815. * hw - Struct containing variables accessed by shared code
  2816. ******************************************************************************/
  2817. static int32_t
  2818. e1000_copper_link_postconfig(struct e1000_hw *hw)
  2819. {
  2820. int32_t ret_val;
  2821. DEBUGFUNC();
  2822. if (hw->mac_type >= e1000_82544) {
  2823. e1000_config_collision_dist(hw);
  2824. } else {
  2825. ret_val = e1000_config_mac_to_phy(hw);
  2826. if (ret_val) {
  2827. DEBUGOUT("Error configuring MAC to PHY settings\n");
  2828. return ret_val;
  2829. }
  2830. }
  2831. ret_val = e1000_config_fc_after_link_up(hw);
  2832. if (ret_val) {
  2833. DEBUGOUT("Error Configuring Flow Control\n");
  2834. return ret_val;
  2835. }
  2836. return E1000_SUCCESS;
  2837. }
  2838. /******************************************************************************
  2839. * Detects which PHY is present and setup the speed and duplex
  2840. *
  2841. * hw - Struct containing variables accessed by shared code
  2842. ******************************************************************************/
  2843. static int
  2844. e1000_setup_copper_link(struct e1000_hw *hw)
  2845. {
  2846. int32_t ret_val;
  2847. uint16_t i;
  2848. uint16_t phy_data;
  2849. uint16_t reg_data;
  2850. DEBUGFUNC();
  2851. switch (hw->mac_type) {
  2852. case e1000_80003es2lan:
  2853. case e1000_ich8lan:
  2854. /* Set the mac to wait the maximum time between each
  2855. * iteration and increase the max iterations when
  2856. * polling the phy; this fixes erroneous timeouts at 10Mbps. */
  2857. ret_val = e1000_write_kmrn_reg(hw,
  2858. GG82563_REG(0x34, 4), 0xFFFF);
  2859. if (ret_val)
  2860. return ret_val;
  2861. ret_val = e1000_read_kmrn_reg(hw,
  2862. GG82563_REG(0x34, 9), &reg_data);
  2863. if (ret_val)
  2864. return ret_val;
  2865. reg_data |= 0x3F;
  2866. ret_val = e1000_write_kmrn_reg(hw,
  2867. GG82563_REG(0x34, 9), reg_data);
  2868. if (ret_val)
  2869. return ret_val;
  2870. default:
  2871. break;
  2872. }
  2873. /* Check if it is a valid PHY and set PHY mode if necessary. */
  2874. ret_val = e1000_copper_link_preconfig(hw);
  2875. if (ret_val)
  2876. return ret_val;
  2877. switch (hw->mac_type) {
  2878. case e1000_80003es2lan:
  2879. /* Kumeran registers are written-only */
  2880. reg_data =
  2881. E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
  2882. reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
  2883. ret_val = e1000_write_kmrn_reg(hw,
  2884. E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
  2885. if (ret_val)
  2886. return ret_val;
  2887. break;
  2888. default:
  2889. break;
  2890. }
  2891. if (hw->phy_type == e1000_phy_igp ||
  2892. hw->phy_type == e1000_phy_igp_3 ||
  2893. hw->phy_type == e1000_phy_igp_2) {
  2894. ret_val = e1000_copper_link_igp_setup(hw);
  2895. if (ret_val)
  2896. return ret_val;
  2897. } else if (hw->phy_type == e1000_phy_m88 ||
  2898. hw->phy_type == e1000_phy_igb) {
  2899. ret_val = e1000_copper_link_mgp_setup(hw);
  2900. if (ret_val)
  2901. return ret_val;
  2902. } else if (hw->phy_type == e1000_phy_gg82563) {
  2903. ret_val = e1000_copper_link_ggp_setup(hw);
  2904. if (ret_val)
  2905. return ret_val;
  2906. }
  2907. /* always auto */
  2908. /* Setup autoneg and flow control advertisement
  2909. * and perform autonegotiation */
  2910. ret_val = e1000_copper_link_autoneg(hw);
  2911. if (ret_val)
  2912. return ret_val;
  2913. /* Check link status. Wait up to 100 microseconds for link to become
  2914. * valid.
  2915. */
  2916. for (i = 0; i < 10; i++) {
  2917. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2918. if (ret_val)
  2919. return ret_val;
  2920. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2921. if (ret_val)
  2922. return ret_val;
  2923. if (phy_data & MII_SR_LINK_STATUS) {
  2924. /* Config the MAC and PHY after link is up */
  2925. ret_val = e1000_copper_link_postconfig(hw);
  2926. if (ret_val)
  2927. return ret_val;
  2928. DEBUGOUT("Valid link established!!!\n");
  2929. return E1000_SUCCESS;
  2930. }
  2931. udelay(10);
  2932. }
  2933. DEBUGOUT("Unable to establish link!!!\n");
  2934. return E1000_SUCCESS;
  2935. }
  2936. /******************************************************************************
  2937. * Configures PHY autoneg and flow control advertisement settings
  2938. *
  2939. * hw - Struct containing variables accessed by shared code
  2940. ******************************************************************************/
  2941. int32_t
  2942. e1000_phy_setup_autoneg(struct e1000_hw *hw)
  2943. {
  2944. int32_t ret_val;
  2945. uint16_t mii_autoneg_adv_reg;
  2946. uint16_t mii_1000t_ctrl_reg;
  2947. DEBUGFUNC();
  2948. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  2949. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
  2950. if (ret_val)
  2951. return ret_val;
  2952. if (hw->phy_type != e1000_phy_ife) {
  2953. /* Read the MII 1000Base-T Control Register (Address 9). */
  2954. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2955. &mii_1000t_ctrl_reg);
  2956. if (ret_val)
  2957. return ret_val;
  2958. } else
  2959. mii_1000t_ctrl_reg = 0;
  2960. /* Need to parse both autoneg_advertised and fc and set up
  2961. * the appropriate PHY registers. First we will parse for
  2962. * autoneg_advertised software override. Since we can advertise
  2963. * a plethora of combinations, we need to check each bit
  2964. * individually.
  2965. */
  2966. /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  2967. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  2968. * the 1000Base-T Control Register (Address 9).
  2969. */
  2970. mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
  2971. mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
  2972. DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
  2973. /* Do we want to advertise 10 Mb Half Duplex? */
  2974. if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
  2975. DEBUGOUT("Advertise 10mb Half duplex\n");
  2976. mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  2977. }
  2978. /* Do we want to advertise 10 Mb Full Duplex? */
  2979. if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
  2980. DEBUGOUT("Advertise 10mb Full duplex\n");
  2981. mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  2982. }
  2983. /* Do we want to advertise 100 Mb Half Duplex? */
  2984. if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
  2985. DEBUGOUT("Advertise 100mb Half duplex\n");
  2986. mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  2987. }
  2988. /* Do we want to advertise 100 Mb Full Duplex? */
  2989. if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
  2990. DEBUGOUT("Advertise 100mb Full duplex\n");
  2991. mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  2992. }
  2993. /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  2994. if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
  2995. DEBUGOUT
  2996. ("Advertise 1000mb Half duplex requested, request denied!\n");
  2997. }
  2998. /* Do we want to advertise 1000 Mb Full Duplex? */
  2999. if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
  3000. DEBUGOUT("Advertise 1000mb Full duplex\n");
  3001. mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  3002. }
  3003. /* Check for a software override of the flow control settings, and
  3004. * setup the PHY advertisement registers accordingly. If
  3005. * auto-negotiation is enabled, then software will have to set the
  3006. * "PAUSE" bits to the correct value in the Auto-Negotiation
  3007. * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
  3008. *
  3009. * The possible values of the "fc" parameter are:
  3010. * 0: Flow control is completely disabled
  3011. * 1: Rx flow control is enabled (we can receive pause frames
  3012. * but not send pause frames).
  3013. * 2: Tx flow control is enabled (we can send pause frames
  3014. * but we do not support receiving pause frames).
  3015. * 3: Both Rx and TX flow control (symmetric) are enabled.
  3016. * other: No software override. The flow control configuration
  3017. * in the EEPROM is used.
  3018. */
  3019. switch (hw->fc) {
  3020. case e1000_fc_none: /* 0 */
  3021. /* Flow control (RX & TX) is completely disabled by a
  3022. * software over-ride.
  3023. */
  3024. mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3025. break;
  3026. case e1000_fc_rx_pause: /* 1 */
  3027. /* RX Flow control is enabled, and TX Flow control is
  3028. * disabled, by a software over-ride.
  3029. */
  3030. /* Since there really isn't a way to advertise that we are
  3031. * capable of RX Pause ONLY, we will advertise that we
  3032. * support both symmetric and asymmetric RX PAUSE. Later
  3033. * (in e1000_config_fc_after_link_up) we will disable the
  3034. *hw's ability to send PAUSE frames.
  3035. */
  3036. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3037. break;
  3038. case e1000_fc_tx_pause: /* 2 */
  3039. /* TX Flow control is enabled, and RX Flow control is
  3040. * disabled, by a software over-ride.
  3041. */
  3042. mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  3043. mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  3044. break;
  3045. case e1000_fc_full: /* 3 */
  3046. /* Flow control (both RX and TX) is enabled by a software
  3047. * over-ride.
  3048. */
  3049. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3050. break;
  3051. default:
  3052. DEBUGOUT("Flow control param set incorrectly\n");
  3053. return -E1000_ERR_CONFIG;
  3054. }
  3055. ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
  3056. if (ret_val)
  3057. return ret_val;
  3058. DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  3059. if (hw->phy_type != e1000_phy_ife) {
  3060. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  3061. mii_1000t_ctrl_reg);
  3062. if (ret_val)
  3063. return ret_val;
  3064. }
  3065. return E1000_SUCCESS;
  3066. }
  3067. /******************************************************************************
  3068. * Sets the collision distance in the Transmit Control register
  3069. *
  3070. * hw - Struct containing variables accessed by shared code
  3071. *
  3072. * Link should have been established previously. Reads the speed and duplex
  3073. * information from the Device Status register.
  3074. ******************************************************************************/
  3075. static void
  3076. e1000_config_collision_dist(struct e1000_hw *hw)
  3077. {
  3078. uint32_t tctl, coll_dist;
  3079. DEBUGFUNC();
  3080. if (hw->mac_type < e1000_82543)
  3081. coll_dist = E1000_COLLISION_DISTANCE_82542;
  3082. else
  3083. coll_dist = E1000_COLLISION_DISTANCE;
  3084. tctl = E1000_READ_REG(hw, TCTL);
  3085. tctl &= ~E1000_TCTL_COLD;
  3086. tctl |= coll_dist << E1000_COLD_SHIFT;
  3087. E1000_WRITE_REG(hw, TCTL, tctl);
  3088. E1000_WRITE_FLUSH(hw);
  3089. }
  3090. /******************************************************************************
  3091. * Sets MAC speed and duplex settings to reflect the those in the PHY
  3092. *
  3093. * hw - Struct containing variables accessed by shared code
  3094. * mii_reg - data to write to the MII control register
  3095. *
  3096. * The contents of the PHY register containing the needed information need to
  3097. * be passed in.
  3098. ******************************************************************************/
  3099. static int
  3100. e1000_config_mac_to_phy(struct e1000_hw *hw)
  3101. {
  3102. uint32_t ctrl;
  3103. uint16_t phy_data;
  3104. DEBUGFUNC();
  3105. /* Read the Device Control Register and set the bits to Force Speed
  3106. * and Duplex.
  3107. */
  3108. ctrl = E1000_READ_REG(hw, CTRL);
  3109. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  3110. ctrl &= ~(E1000_CTRL_ILOS);
  3111. ctrl |= (E1000_CTRL_SPD_SEL);
  3112. /* Set up duplex in the Device Control and Transmit Control
  3113. * registers depending on negotiated values.
  3114. */
  3115. if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
  3116. DEBUGOUT("PHY Read Error\n");
  3117. return -E1000_ERR_PHY;
  3118. }
  3119. if (phy_data & M88E1000_PSSR_DPLX)
  3120. ctrl |= E1000_CTRL_FD;
  3121. else
  3122. ctrl &= ~E1000_CTRL_FD;
  3123. e1000_config_collision_dist(hw);
  3124. /* Set up speed in the Device Control register depending on
  3125. * negotiated values.
  3126. */
  3127. if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  3128. ctrl |= E1000_CTRL_SPD_1000;
  3129. else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  3130. ctrl |= E1000_CTRL_SPD_100;
  3131. /* Write the configured values back to the Device Control Reg. */
  3132. E1000_WRITE_REG(hw, CTRL, ctrl);
  3133. return 0;
  3134. }
  3135. /******************************************************************************
  3136. * Forces the MAC's flow control settings.
  3137. *
  3138. * hw - Struct containing variables accessed by shared code
  3139. *
  3140. * Sets the TFCE and RFCE bits in the device control register to reflect
  3141. * the adapter settings. TFCE and RFCE need to be explicitly set by
  3142. * software when a Copper PHY is used because autonegotiation is managed
  3143. * by the PHY rather than the MAC. Software must also configure these
  3144. * bits when link is forced on a fiber connection.
  3145. *****************************************************************************/
  3146. static int
  3147. e1000_force_mac_fc(struct e1000_hw *hw)
  3148. {
  3149. uint32_t ctrl;
  3150. DEBUGFUNC();
  3151. /* Get the current configuration of the Device Control Register */
  3152. ctrl = E1000_READ_REG(hw, CTRL);
  3153. /* Because we didn't get link via the internal auto-negotiation
  3154. * mechanism (we either forced link or we got link via PHY
  3155. * auto-neg), we have to manually enable/disable transmit an
  3156. * receive flow control.
  3157. *
  3158. * The "Case" statement below enables/disable flow control
  3159. * according to the "hw->fc" parameter.
  3160. *
  3161. * The possible values of the "fc" parameter are:
  3162. * 0: Flow control is completely disabled
  3163. * 1: Rx flow control is enabled (we can receive pause
  3164. * frames but not send pause frames).
  3165. * 2: Tx flow control is enabled (we can send pause frames
  3166. * frames but we do not receive pause frames).
  3167. * 3: Both Rx and TX flow control (symmetric) is enabled.
  3168. * other: No other values should be possible at this point.
  3169. */
  3170. switch (hw->fc) {
  3171. case e1000_fc_none:
  3172. ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  3173. break;
  3174. case e1000_fc_rx_pause:
  3175. ctrl &= (~E1000_CTRL_TFCE);
  3176. ctrl |= E1000_CTRL_RFCE;
  3177. break;
  3178. case e1000_fc_tx_pause:
  3179. ctrl &= (~E1000_CTRL_RFCE);
  3180. ctrl |= E1000_CTRL_TFCE;
  3181. break;
  3182. case e1000_fc_full:
  3183. ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  3184. break;
  3185. default:
  3186. DEBUGOUT("Flow control param set incorrectly\n");
  3187. return -E1000_ERR_CONFIG;
  3188. }
  3189. /* Disable TX Flow Control for 82542 (rev 2.0) */
  3190. if (hw->mac_type == e1000_82542_rev2_0)
  3191. ctrl &= (~E1000_CTRL_TFCE);
  3192. E1000_WRITE_REG(hw, CTRL, ctrl);
  3193. return 0;
  3194. }
  3195. /******************************************************************************
  3196. * Configures flow control settings after link is established
  3197. *
  3198. * hw - Struct containing variables accessed by shared code
  3199. *
  3200. * Should be called immediately after a valid link has been established.
  3201. * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  3202. * and autonegotiation is enabled, the MAC flow control settings will be set
  3203. * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
  3204. * and RFCE bits will be automaticaly set to the negotiated flow control mode.
  3205. *****************************************************************************/
  3206. static int32_t
  3207. e1000_config_fc_after_link_up(struct e1000_hw *hw)
  3208. {
  3209. int32_t ret_val;
  3210. uint16_t mii_status_reg;
  3211. uint16_t mii_nway_adv_reg;
  3212. uint16_t mii_nway_lp_ability_reg;
  3213. uint16_t speed;
  3214. uint16_t duplex;
  3215. DEBUGFUNC();
  3216. /* Check for the case where we have fiber media and auto-neg failed
  3217. * so we had to force link. In this case, we need to force the
  3218. * configuration of the MAC to match the "fc" parameter.
  3219. */
  3220. if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
  3221. || ((hw->media_type == e1000_media_type_internal_serdes)
  3222. && (hw->autoneg_failed))
  3223. || ((hw->media_type == e1000_media_type_copper)
  3224. && (!hw->autoneg))) {
  3225. ret_val = e1000_force_mac_fc(hw);
  3226. if (ret_val < 0) {
  3227. DEBUGOUT("Error forcing flow control settings\n");
  3228. return ret_val;
  3229. }
  3230. }
  3231. /* Check for the case where we have copper media and auto-neg is
  3232. * enabled. In this case, we need to check and see if Auto-Neg
  3233. * has completed, and if so, how the PHY and link partner has
  3234. * flow control configured.
  3235. */
  3236. if (hw->media_type == e1000_media_type_copper) {
  3237. /* Read the MII Status Register and check to see if AutoNeg
  3238. * has completed. We read this twice because this reg has
  3239. * some "sticky" (latched) bits.
  3240. */
  3241. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3242. DEBUGOUT("PHY Read Error\n");
  3243. return -E1000_ERR_PHY;
  3244. }
  3245. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3246. DEBUGOUT("PHY Read Error\n");
  3247. return -E1000_ERR_PHY;
  3248. }
  3249. if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  3250. /* The AutoNeg process has completed, so we now need to
  3251. * read both the Auto Negotiation Advertisement Register
  3252. * (Address 4) and the Auto_Negotiation Base Page Ability
  3253. * Register (Address 5) to determine how flow control was
  3254. * negotiated.
  3255. */
  3256. if (e1000_read_phy_reg
  3257. (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
  3258. DEBUGOUT("PHY Read Error\n");
  3259. return -E1000_ERR_PHY;
  3260. }
  3261. if (e1000_read_phy_reg
  3262. (hw, PHY_LP_ABILITY,
  3263. &mii_nway_lp_ability_reg) < 0) {
  3264. DEBUGOUT("PHY Read Error\n");
  3265. return -E1000_ERR_PHY;
  3266. }
  3267. /* Two bits in the Auto Negotiation Advertisement Register
  3268. * (Address 4) and two bits in the Auto Negotiation Base
  3269. * Page Ability Register (Address 5) determine flow control
  3270. * for both the PHY and the link partner. The following
  3271. * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  3272. * 1999, describes these PAUSE resolution bits and how flow
  3273. * control is determined based upon these settings.
  3274. * NOTE: DC = Don't Care
  3275. *
  3276. * LOCAL DEVICE | LINK PARTNER
  3277. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  3278. *-------|---------|-------|---------|--------------------
  3279. * 0 | 0 | DC | DC | e1000_fc_none
  3280. * 0 | 1 | 0 | DC | e1000_fc_none
  3281. * 0 | 1 | 1 | 0 | e1000_fc_none
  3282. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3283. * 1 | 0 | 0 | DC | e1000_fc_none
  3284. * 1 | DC | 1 | DC | e1000_fc_full
  3285. * 1 | 1 | 0 | 0 | e1000_fc_none
  3286. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3287. *
  3288. */
  3289. /* Are both PAUSE bits set to 1? If so, this implies
  3290. * Symmetric Flow Control is enabled at both ends. The
  3291. * ASM_DIR bits are irrelevant per the spec.
  3292. *
  3293. * For Symmetric Flow Control:
  3294. *
  3295. * LOCAL DEVICE | LINK PARTNER
  3296. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3297. *-------|---------|-------|---------|--------------------
  3298. * 1 | DC | 1 | DC | e1000_fc_full
  3299. *
  3300. */
  3301. if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3302. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  3303. /* Now we need to check if the user selected RX ONLY
  3304. * of pause frames. In this case, we had to advertise
  3305. * FULL flow control because we could not advertise RX
  3306. * ONLY. Hence, we must now check to see if we need to
  3307. * turn OFF the TRANSMISSION of PAUSE frames.
  3308. */
  3309. if (hw->original_fc == e1000_fc_full) {
  3310. hw->fc = e1000_fc_full;
  3311. DEBUGOUT("Flow Control = FULL.\r\n");
  3312. } else {
  3313. hw->fc = e1000_fc_rx_pause;
  3314. DEBUGOUT
  3315. ("Flow Control = RX PAUSE frames only.\r\n");
  3316. }
  3317. }
  3318. /* For receiving PAUSE frames ONLY.
  3319. *
  3320. * LOCAL DEVICE | LINK PARTNER
  3321. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3322. *-------|---------|-------|---------|--------------------
  3323. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3324. *
  3325. */
  3326. else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3327. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3328. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3329. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3330. {
  3331. hw->fc = e1000_fc_tx_pause;
  3332. DEBUGOUT
  3333. ("Flow Control = TX PAUSE frames only.\r\n");
  3334. }
  3335. /* For transmitting PAUSE frames ONLY.
  3336. *
  3337. * LOCAL DEVICE | LINK PARTNER
  3338. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3339. *-------|---------|-------|---------|--------------------
  3340. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3341. *
  3342. */
  3343. else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3344. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3345. !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3346. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3347. {
  3348. hw->fc = e1000_fc_rx_pause;
  3349. DEBUGOUT
  3350. ("Flow Control = RX PAUSE frames only.\r\n");
  3351. }
  3352. /* Per the IEEE spec, at this point flow control should be
  3353. * disabled. However, we want to consider that we could
  3354. * be connected to a legacy switch that doesn't advertise
  3355. * desired flow control, but can be forced on the link
  3356. * partner. So if we advertised no flow control, that is
  3357. * what we will resolve to. If we advertised some kind of
  3358. * receive capability (Rx Pause Only or Full Flow Control)
  3359. * and the link partner advertised none, we will configure
  3360. * ourselves to enable Rx Flow Control only. We can do
  3361. * this safely for two reasons: If the link partner really
  3362. * didn't want flow control enabled, and we enable Rx, no
  3363. * harm done since we won't be receiving any PAUSE frames
  3364. * anyway. If the intent on the link partner was to have
  3365. * flow control enabled, then by us enabling RX only, we
  3366. * can at least receive pause frames and process them.
  3367. * This is a good idea because in most cases, since we are
  3368. * predominantly a server NIC, more times than not we will
  3369. * be asked to delay transmission of packets than asking
  3370. * our link partner to pause transmission of frames.
  3371. */
  3372. else if (hw->original_fc == e1000_fc_none ||
  3373. hw->original_fc == e1000_fc_tx_pause) {
  3374. hw->fc = e1000_fc_none;
  3375. DEBUGOUT("Flow Control = NONE.\r\n");
  3376. } else {
  3377. hw->fc = e1000_fc_rx_pause;
  3378. DEBUGOUT
  3379. ("Flow Control = RX PAUSE frames only.\r\n");
  3380. }
  3381. /* Now we need to do one last check... If we auto-
  3382. * negotiated to HALF DUPLEX, flow control should not be
  3383. * enabled per IEEE 802.3 spec.
  3384. */
  3385. e1000_get_speed_and_duplex(hw, &speed, &duplex);
  3386. if (duplex == HALF_DUPLEX)
  3387. hw->fc = e1000_fc_none;
  3388. /* Now we call a subroutine to actually force the MAC
  3389. * controller to use the correct flow control settings.
  3390. */
  3391. ret_val = e1000_force_mac_fc(hw);
  3392. if (ret_val < 0) {
  3393. DEBUGOUT
  3394. ("Error forcing flow control settings\n");
  3395. return ret_val;
  3396. }
  3397. } else {
  3398. DEBUGOUT
  3399. ("Copper PHY and Auto Neg has not completed.\r\n");
  3400. }
  3401. }
  3402. return E1000_SUCCESS;
  3403. }
  3404. /******************************************************************************
  3405. * Checks to see if the link status of the hardware has changed.
  3406. *
  3407. * hw - Struct containing variables accessed by shared code
  3408. *
  3409. * Called by any function that needs to check the link status of the adapter.
  3410. *****************************************************************************/
  3411. static int
  3412. e1000_check_for_link(struct e1000_hw *hw)
  3413. {
  3414. uint32_t rxcw;
  3415. uint32_t ctrl;
  3416. uint32_t status;
  3417. uint32_t rctl;
  3418. uint32_t signal;
  3419. int32_t ret_val;
  3420. uint16_t phy_data;
  3421. uint16_t lp_capability;
  3422. DEBUGFUNC();
  3423. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  3424. * set when the optics detect a signal. On older adapters, it will be
  3425. * cleared when there is a signal
  3426. */
  3427. ctrl = E1000_READ_REG(hw, CTRL);
  3428. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  3429. signal = E1000_CTRL_SWDPIN1;
  3430. else
  3431. signal = 0;
  3432. status = E1000_READ_REG(hw, STATUS);
  3433. rxcw = E1000_READ_REG(hw, RXCW);
  3434. DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
  3435. /* If we have a copper PHY then we only want to go out to the PHY
  3436. * registers to see if Auto-Neg has completed and/or if our link
  3437. * status has changed. The get_link_status flag will be set if we
  3438. * receive a Link Status Change interrupt or we have Rx Sequence
  3439. * Errors.
  3440. */
  3441. if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
  3442. /* First we want to see if the MII Status Register reports
  3443. * link. If so, then we want to get the current speed/duplex
  3444. * of the PHY.
  3445. * Read the register twice since the link bit is sticky.
  3446. */
  3447. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3448. DEBUGOUT("PHY Read Error\n");
  3449. return -E1000_ERR_PHY;
  3450. }
  3451. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3452. DEBUGOUT("PHY Read Error\n");
  3453. return -E1000_ERR_PHY;
  3454. }
  3455. if (phy_data & MII_SR_LINK_STATUS) {
  3456. hw->get_link_status = false;
  3457. } else {
  3458. /* No link detected */
  3459. return -E1000_ERR_NOLINK;
  3460. }
  3461. /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
  3462. * have Si on board that is 82544 or newer, Auto
  3463. * Speed Detection takes care of MAC speed/duplex
  3464. * configuration. So we only need to configure Collision
  3465. * Distance in the MAC. Otherwise, we need to force
  3466. * speed/duplex on the MAC to the current PHY speed/duplex
  3467. * settings.
  3468. */
  3469. if (hw->mac_type >= e1000_82544)
  3470. e1000_config_collision_dist(hw);
  3471. else {
  3472. ret_val = e1000_config_mac_to_phy(hw);
  3473. if (ret_val < 0) {
  3474. DEBUGOUT
  3475. ("Error configuring MAC to PHY settings\n");
  3476. return ret_val;
  3477. }
  3478. }
  3479. /* Configure Flow Control now that Auto-Neg has completed. First, we
  3480. * need to restore the desired flow control settings because we may
  3481. * have had to re-autoneg with a different link partner.
  3482. */
  3483. ret_val = e1000_config_fc_after_link_up(hw);
  3484. if (ret_val < 0) {
  3485. DEBUGOUT("Error configuring flow control\n");
  3486. return ret_val;
  3487. }
  3488. /* At this point we know that we are on copper and we have
  3489. * auto-negotiated link. These are conditions for checking the link
  3490. * parter capability register. We use the link partner capability to
  3491. * determine if TBI Compatibility needs to be turned on or off. If
  3492. * the link partner advertises any speed in addition to Gigabit, then
  3493. * we assume that they are GMII-based, and TBI compatibility is not
  3494. * needed. If no other speeds are advertised, we assume the link
  3495. * partner is TBI-based, and we turn on TBI Compatibility.
  3496. */
  3497. if (hw->tbi_compatibility_en) {
  3498. if (e1000_read_phy_reg
  3499. (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
  3500. DEBUGOUT("PHY Read Error\n");
  3501. return -E1000_ERR_PHY;
  3502. }
  3503. if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
  3504. NWAY_LPAR_10T_FD_CAPS |
  3505. NWAY_LPAR_100TX_HD_CAPS |
  3506. NWAY_LPAR_100TX_FD_CAPS |
  3507. NWAY_LPAR_100T4_CAPS)) {
  3508. /* If our link partner advertises anything in addition to
  3509. * gigabit, we do not need to enable TBI compatibility.
  3510. */
  3511. if (hw->tbi_compatibility_on) {
  3512. /* If we previously were in the mode, turn it off. */
  3513. rctl = E1000_READ_REG(hw, RCTL);
  3514. rctl &= ~E1000_RCTL_SBP;
  3515. E1000_WRITE_REG(hw, RCTL, rctl);
  3516. hw->tbi_compatibility_on = false;
  3517. }
  3518. } else {
  3519. /* If TBI compatibility is was previously off, turn it on. For
  3520. * compatibility with a TBI link partner, we will store bad
  3521. * packets. Some frames have an additional byte on the end and
  3522. * will look like CRC errors to to the hardware.
  3523. */
  3524. if (!hw->tbi_compatibility_on) {
  3525. hw->tbi_compatibility_on = true;
  3526. rctl = E1000_READ_REG(hw, RCTL);
  3527. rctl |= E1000_RCTL_SBP;
  3528. E1000_WRITE_REG(hw, RCTL, rctl);
  3529. }
  3530. }
  3531. }
  3532. }
  3533. /* If we don't have link (auto-negotiation failed or link partner cannot
  3534. * auto-negotiate), the cable is plugged in (we have signal), and our
  3535. * link partner is not trying to auto-negotiate with us (we are receiving
  3536. * idles or data), we need to force link up. We also need to give
  3537. * auto-negotiation time to complete, in case the cable was just plugged
  3538. * in. The autoneg_failed flag does this.
  3539. */
  3540. else if ((hw->media_type == e1000_media_type_fiber) &&
  3541. (!(status & E1000_STATUS_LU)) &&
  3542. ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
  3543. (!(rxcw & E1000_RXCW_C))) {
  3544. if (hw->autoneg_failed == 0) {
  3545. hw->autoneg_failed = 1;
  3546. return 0;
  3547. }
  3548. DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
  3549. /* Disable auto-negotiation in the TXCW register */
  3550. E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
  3551. /* Force link-up and also force full-duplex. */
  3552. ctrl = E1000_READ_REG(hw, CTRL);
  3553. ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
  3554. E1000_WRITE_REG(hw, CTRL, ctrl);
  3555. /* Configure Flow Control after forcing link up. */
  3556. ret_val = e1000_config_fc_after_link_up(hw);
  3557. if (ret_val < 0) {
  3558. DEBUGOUT("Error configuring flow control\n");
  3559. return ret_val;
  3560. }
  3561. }
  3562. /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
  3563. * auto-negotiation in the TXCW register and disable forced link in the
  3564. * Device Control register in an attempt to auto-negotiate with our link
  3565. * partner.
  3566. */
  3567. else if ((hw->media_type == e1000_media_type_fiber) &&
  3568. (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
  3569. DEBUGOUT
  3570. ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
  3571. E1000_WRITE_REG(hw, TXCW, hw->txcw);
  3572. E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  3573. }
  3574. return 0;
  3575. }
  3576. /******************************************************************************
  3577. * Configure the MAC-to-PHY interface for 10/100Mbps
  3578. *
  3579. * hw - Struct containing variables accessed by shared code
  3580. ******************************************************************************/
  3581. static int32_t
  3582. e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
  3583. {
  3584. int32_t ret_val = E1000_SUCCESS;
  3585. uint32_t tipg;
  3586. uint16_t reg_data;
  3587. DEBUGFUNC();
  3588. reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
  3589. ret_val = e1000_write_kmrn_reg(hw,
  3590. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3591. if (ret_val)
  3592. return ret_val;
  3593. /* Configure Transmit Inter-Packet Gap */
  3594. tipg = E1000_READ_REG(hw, TIPG);
  3595. tipg &= ~E1000_TIPG_IPGT_MASK;
  3596. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
  3597. E1000_WRITE_REG(hw, TIPG, tipg);
  3598. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3599. if (ret_val)
  3600. return ret_val;
  3601. if (duplex == HALF_DUPLEX)
  3602. reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
  3603. else
  3604. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3605. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3606. return ret_val;
  3607. }
  3608. static int32_t
  3609. e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
  3610. {
  3611. int32_t ret_val = E1000_SUCCESS;
  3612. uint16_t reg_data;
  3613. uint32_t tipg;
  3614. DEBUGFUNC();
  3615. reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
  3616. ret_val = e1000_write_kmrn_reg(hw,
  3617. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3618. if (ret_val)
  3619. return ret_val;
  3620. /* Configure Transmit Inter-Packet Gap */
  3621. tipg = E1000_READ_REG(hw, TIPG);
  3622. tipg &= ~E1000_TIPG_IPGT_MASK;
  3623. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  3624. E1000_WRITE_REG(hw, TIPG, tipg);
  3625. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3626. if (ret_val)
  3627. return ret_val;
  3628. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3629. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3630. return ret_val;
  3631. }
  3632. /******************************************************************************
  3633. * Detects the current speed and duplex settings of the hardware.
  3634. *
  3635. * hw - Struct containing variables accessed by shared code
  3636. * speed - Speed of the connection
  3637. * duplex - Duplex setting of the connection
  3638. *****************************************************************************/
  3639. static int
  3640. e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
  3641. uint16_t *duplex)
  3642. {
  3643. uint32_t status;
  3644. int32_t ret_val;
  3645. uint16_t phy_data;
  3646. DEBUGFUNC();
  3647. if (hw->mac_type >= e1000_82543) {
  3648. status = E1000_READ_REG(hw, STATUS);
  3649. if (status & E1000_STATUS_SPEED_1000) {
  3650. *speed = SPEED_1000;
  3651. DEBUGOUT("1000 Mbs, ");
  3652. } else if (status & E1000_STATUS_SPEED_100) {
  3653. *speed = SPEED_100;
  3654. DEBUGOUT("100 Mbs, ");
  3655. } else {
  3656. *speed = SPEED_10;
  3657. DEBUGOUT("10 Mbs, ");
  3658. }
  3659. if (status & E1000_STATUS_FD) {
  3660. *duplex = FULL_DUPLEX;
  3661. DEBUGOUT("Full Duplex\r\n");
  3662. } else {
  3663. *duplex = HALF_DUPLEX;
  3664. DEBUGOUT(" Half Duplex\r\n");
  3665. }
  3666. } else {
  3667. DEBUGOUT("1000 Mbs, Full Duplex\r\n");
  3668. *speed = SPEED_1000;
  3669. *duplex = FULL_DUPLEX;
  3670. }
  3671. /* IGP01 PHY may advertise full duplex operation after speed downgrade
  3672. * even if it is operating at half duplex. Here we set the duplex
  3673. * settings to match the duplex in the link partner's capabilities.
  3674. */
  3675. if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
  3676. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
  3677. if (ret_val)
  3678. return ret_val;
  3679. if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
  3680. *duplex = HALF_DUPLEX;
  3681. else {
  3682. ret_val = e1000_read_phy_reg(hw,
  3683. PHY_LP_ABILITY, &phy_data);
  3684. if (ret_val)
  3685. return ret_val;
  3686. if ((*speed == SPEED_100 &&
  3687. !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
  3688. || (*speed == SPEED_10
  3689. && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
  3690. *duplex = HALF_DUPLEX;
  3691. }
  3692. }
  3693. if ((hw->mac_type == e1000_80003es2lan) &&
  3694. (hw->media_type == e1000_media_type_copper)) {
  3695. if (*speed == SPEED_1000)
  3696. ret_val = e1000_configure_kmrn_for_1000(hw);
  3697. else
  3698. ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
  3699. if (ret_val)
  3700. return ret_val;
  3701. }
  3702. return E1000_SUCCESS;
  3703. }
  3704. /******************************************************************************
  3705. * Blocks until autoneg completes or times out (~4.5 seconds)
  3706. *
  3707. * hw - Struct containing variables accessed by shared code
  3708. ******************************************************************************/
  3709. static int
  3710. e1000_wait_autoneg(struct e1000_hw *hw)
  3711. {
  3712. uint16_t i;
  3713. uint16_t phy_data;
  3714. DEBUGFUNC();
  3715. DEBUGOUT("Waiting for Auto-Neg to complete.\n");
  3716. /* We will wait for autoneg to complete or timeout to expire. */
  3717. for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
  3718. /* Read the MII Status Register and wait for Auto-Neg
  3719. * Complete bit to be set.
  3720. */
  3721. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3722. DEBUGOUT("PHY Read Error\n");
  3723. return -E1000_ERR_PHY;
  3724. }
  3725. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3726. DEBUGOUT("PHY Read Error\n");
  3727. return -E1000_ERR_PHY;
  3728. }
  3729. if (phy_data & MII_SR_AUTONEG_COMPLETE) {
  3730. DEBUGOUT("Auto-Neg complete.\n");
  3731. return 0;
  3732. }
  3733. mdelay(100);
  3734. }
  3735. DEBUGOUT("Auto-Neg timedout.\n");
  3736. return -E1000_ERR_TIMEOUT;
  3737. }
  3738. /******************************************************************************
  3739. * Raises the Management Data Clock
  3740. *
  3741. * hw - Struct containing variables accessed by shared code
  3742. * ctrl - Device control register's current value
  3743. ******************************************************************************/
  3744. static void
  3745. e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3746. {
  3747. /* Raise the clock input to the Management Data Clock (by setting the MDC
  3748. * bit), and then delay 2 microseconds.
  3749. */
  3750. E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  3751. E1000_WRITE_FLUSH(hw);
  3752. udelay(2);
  3753. }
  3754. /******************************************************************************
  3755. * Lowers the Management Data Clock
  3756. *
  3757. * hw - Struct containing variables accessed by shared code
  3758. * ctrl - Device control register's current value
  3759. ******************************************************************************/
  3760. static void
  3761. e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3762. {
  3763. /* Lower the clock input to the Management Data Clock (by clearing the MDC
  3764. * bit), and then delay 2 microseconds.
  3765. */
  3766. E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  3767. E1000_WRITE_FLUSH(hw);
  3768. udelay(2);
  3769. }
  3770. /******************************************************************************
  3771. * Shifts data bits out to the PHY
  3772. *
  3773. * hw - Struct containing variables accessed by shared code
  3774. * data - Data to send out to the PHY
  3775. * count - Number of bits to shift out
  3776. *
  3777. * Bits are shifted out in MSB to LSB order.
  3778. ******************************************************************************/
  3779. static void
  3780. e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
  3781. {
  3782. uint32_t ctrl;
  3783. uint32_t mask;
  3784. /* We need to shift "count" number of bits out to the PHY. So, the value
  3785. * in the "data" parameter will be shifted out to the PHY one bit at a
  3786. * time. In order to do this, "data" must be broken down into bits.
  3787. */
  3788. mask = 0x01;
  3789. mask <<= (count - 1);
  3790. ctrl = E1000_READ_REG(hw, CTRL);
  3791. /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
  3792. ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
  3793. while (mask) {
  3794. /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
  3795. * then raising and lowering the Management Data Clock. A "0" is
  3796. * shifted out to the PHY by setting the MDIO bit to "0" and then
  3797. * raising and lowering the clock.
  3798. */
  3799. if (data & mask)
  3800. ctrl |= E1000_CTRL_MDIO;
  3801. else
  3802. ctrl &= ~E1000_CTRL_MDIO;
  3803. E1000_WRITE_REG(hw, CTRL, ctrl);
  3804. E1000_WRITE_FLUSH(hw);
  3805. udelay(2);
  3806. e1000_raise_mdi_clk(hw, &ctrl);
  3807. e1000_lower_mdi_clk(hw, &ctrl);
  3808. mask = mask >> 1;
  3809. }
  3810. }
  3811. /******************************************************************************
  3812. * Shifts data bits in from the PHY
  3813. *
  3814. * hw - Struct containing variables accessed by shared code
  3815. *
  3816. * Bits are shifted in in MSB to LSB order.
  3817. ******************************************************************************/
  3818. static uint16_t
  3819. e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  3820. {
  3821. uint32_t ctrl;
  3822. uint16_t data = 0;
  3823. uint8_t i;
  3824. /* In order to read a register from the PHY, we need to shift in a total
  3825. * of 18 bits from the PHY. The first two bit (turnaround) times are used
  3826. * to avoid contention on the MDIO pin when a read operation is performed.
  3827. * These two bits are ignored by us and thrown away. Bits are "shifted in"
  3828. * by raising the input to the Management Data Clock (setting the MDC bit),
  3829. * and then reading the value of the MDIO bit.
  3830. */
  3831. ctrl = E1000_READ_REG(hw, CTRL);
  3832. /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  3833. ctrl &= ~E1000_CTRL_MDIO_DIR;
  3834. ctrl &= ~E1000_CTRL_MDIO;
  3835. E1000_WRITE_REG(hw, CTRL, ctrl);
  3836. E1000_WRITE_FLUSH(hw);
  3837. /* Raise and Lower the clock before reading in the data. This accounts for
  3838. * the turnaround bits. The first clock occurred when we clocked out the
  3839. * last bit of the Register Address.
  3840. */
  3841. e1000_raise_mdi_clk(hw, &ctrl);
  3842. e1000_lower_mdi_clk(hw, &ctrl);
  3843. for (data = 0, i = 0; i < 16; i++) {
  3844. data = data << 1;
  3845. e1000_raise_mdi_clk(hw, &ctrl);
  3846. ctrl = E1000_READ_REG(hw, CTRL);
  3847. /* Check to see if we shifted in a "1". */
  3848. if (ctrl & E1000_CTRL_MDIO)
  3849. data |= 1;
  3850. e1000_lower_mdi_clk(hw, &ctrl);
  3851. }
  3852. e1000_raise_mdi_clk(hw, &ctrl);
  3853. e1000_lower_mdi_clk(hw, &ctrl);
  3854. return data;
  3855. }
  3856. /*****************************************************************************
  3857. * Reads the value from a PHY register
  3858. *
  3859. * hw - Struct containing variables accessed by shared code
  3860. * reg_addr - address of the PHY register to read
  3861. ******************************************************************************/
  3862. static int
  3863. e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
  3864. {
  3865. uint32_t i;
  3866. uint32_t mdic = 0;
  3867. const uint32_t phy_addr = 1;
  3868. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3869. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3870. return -E1000_ERR_PARAM;
  3871. }
  3872. if (hw->mac_type > e1000_82543) {
  3873. /* Set up Op-code, Phy Address, and register address in the MDI
  3874. * Control register. The MAC will take care of interfacing with the
  3875. * PHY to retrieve the desired data.
  3876. */
  3877. mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  3878. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3879. (E1000_MDIC_OP_READ));
  3880. E1000_WRITE_REG(hw, MDIC, mdic);
  3881. /* Poll the ready bit to see if the MDI read completed */
  3882. for (i = 0; i < 64; i++) {
  3883. udelay(10);
  3884. mdic = E1000_READ_REG(hw, MDIC);
  3885. if (mdic & E1000_MDIC_READY)
  3886. break;
  3887. }
  3888. if (!(mdic & E1000_MDIC_READY)) {
  3889. DEBUGOUT("MDI Read did not complete\n");
  3890. return -E1000_ERR_PHY;
  3891. }
  3892. if (mdic & E1000_MDIC_ERROR) {
  3893. DEBUGOUT("MDI Error\n");
  3894. return -E1000_ERR_PHY;
  3895. }
  3896. *phy_data = (uint16_t) mdic;
  3897. } else {
  3898. /* We must first send a preamble through the MDIO pin to signal the
  3899. * beginning of an MII instruction. This is done by sending 32
  3900. * consecutive "1" bits.
  3901. */
  3902. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3903. /* Now combine the next few fields that are required for a read
  3904. * operation. We use this method instead of calling the
  3905. * e1000_shift_out_mdi_bits routine five different times. The format of
  3906. * a MII read instruction consists of a shift out of 14 bits and is
  3907. * defined as follows:
  3908. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
  3909. * followed by a shift in of 18 bits. This first two bits shifted in
  3910. * are TurnAround bits used to avoid contention on the MDIO pin when a
  3911. * READ operation is performed. These two bits are thrown away
  3912. * followed by a shift in of 16 bits which contains the desired data.
  3913. */
  3914. mdic = ((reg_addr) | (phy_addr << 5) |
  3915. (PHY_OP_READ << 10) | (PHY_SOF << 12));
  3916. e1000_shift_out_mdi_bits(hw, mdic, 14);
  3917. /* Now that we've shifted out the read command to the MII, we need to
  3918. * "shift in" the 16-bit value (18 total bits) of the requested PHY
  3919. * register address.
  3920. */
  3921. *phy_data = e1000_shift_in_mdi_bits(hw);
  3922. }
  3923. return 0;
  3924. }
  3925. /******************************************************************************
  3926. * Writes a value to a PHY register
  3927. *
  3928. * hw - Struct containing variables accessed by shared code
  3929. * reg_addr - address of the PHY register to write
  3930. * data - data to write to the PHY
  3931. ******************************************************************************/
  3932. static int
  3933. e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
  3934. {
  3935. uint32_t i;
  3936. uint32_t mdic = 0;
  3937. const uint32_t phy_addr = 1;
  3938. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3939. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3940. return -E1000_ERR_PARAM;
  3941. }
  3942. if (hw->mac_type > e1000_82543) {
  3943. /* Set up Op-code, Phy Address, register address, and data intended
  3944. * for the PHY register in the MDI Control register. The MAC will take
  3945. * care of interfacing with the PHY to send the desired data.
  3946. */
  3947. mdic = (((uint32_t) phy_data) |
  3948. (reg_addr << E1000_MDIC_REG_SHIFT) |
  3949. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3950. (E1000_MDIC_OP_WRITE));
  3951. E1000_WRITE_REG(hw, MDIC, mdic);
  3952. /* Poll the ready bit to see if the MDI read completed */
  3953. for (i = 0; i < 64; i++) {
  3954. udelay(10);
  3955. mdic = E1000_READ_REG(hw, MDIC);
  3956. if (mdic & E1000_MDIC_READY)
  3957. break;
  3958. }
  3959. if (!(mdic & E1000_MDIC_READY)) {
  3960. DEBUGOUT("MDI Write did not complete\n");
  3961. return -E1000_ERR_PHY;
  3962. }
  3963. } else {
  3964. /* We'll need to use the SW defined pins to shift the write command
  3965. * out to the PHY. We first send a preamble to the PHY to signal the
  3966. * beginning of the MII instruction. This is done by sending 32
  3967. * consecutive "1" bits.
  3968. */
  3969. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3970. /* Now combine the remaining required fields that will indicate a
  3971. * write operation. We use this method instead of calling the
  3972. * e1000_shift_out_mdi_bits routine for each field in the command. The
  3973. * format of a MII write instruction is as follows:
  3974. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
  3975. */
  3976. mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
  3977. (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
  3978. mdic <<= 16;
  3979. mdic |= (uint32_t) phy_data;
  3980. e1000_shift_out_mdi_bits(hw, mdic, 32);
  3981. }
  3982. return 0;
  3983. }
  3984. /******************************************************************************
  3985. * Checks if PHY reset is blocked due to SOL/IDER session, for example.
  3986. * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
  3987. * the caller to figure out how to deal with it.
  3988. *
  3989. * hw - Struct containing variables accessed by shared code
  3990. *
  3991. * returns: - E1000_BLK_PHY_RESET
  3992. * E1000_SUCCESS
  3993. *
  3994. *****************************************************************************/
  3995. int32_t
  3996. e1000_check_phy_reset_block(struct e1000_hw *hw)
  3997. {
  3998. uint32_t manc = 0;
  3999. uint32_t fwsm = 0;
  4000. if (hw->mac_type == e1000_ich8lan) {
  4001. fwsm = E1000_READ_REG(hw, FWSM);
  4002. return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
  4003. : E1000_BLK_PHY_RESET;
  4004. }
  4005. if (hw->mac_type > e1000_82547_rev_2)
  4006. manc = E1000_READ_REG(hw, MANC);
  4007. return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
  4008. E1000_BLK_PHY_RESET : E1000_SUCCESS;
  4009. }
  4010. /***************************************************************************
  4011. * Checks if the PHY configuration is done
  4012. *
  4013. * hw: Struct containing variables accessed by shared code
  4014. *
  4015. * returns: - E1000_ERR_RESET if fail to reset MAC
  4016. * E1000_SUCCESS at any other case.
  4017. *
  4018. ***************************************************************************/
  4019. static int32_t
  4020. e1000_get_phy_cfg_done(struct e1000_hw *hw)
  4021. {
  4022. int32_t timeout = PHY_CFG_TIMEOUT;
  4023. uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
  4024. DEBUGFUNC();
  4025. switch (hw->mac_type) {
  4026. default:
  4027. mdelay(10);
  4028. break;
  4029. case e1000_80003es2lan:
  4030. /* Separate *_CFG_DONE_* bit for each port */
  4031. if (e1000_is_second_port(hw))
  4032. cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
  4033. /* Fall Through */
  4034. case e1000_82571:
  4035. case e1000_82572:
  4036. case e1000_igb:
  4037. while (timeout) {
  4038. if (hw->mac_type == e1000_igb) {
  4039. if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
  4040. break;
  4041. } else {
  4042. if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
  4043. break;
  4044. }
  4045. mdelay(1);
  4046. timeout--;
  4047. }
  4048. if (!timeout) {
  4049. DEBUGOUT("MNG configuration cycle has not "
  4050. "completed.\n");
  4051. return -E1000_ERR_RESET;
  4052. }
  4053. break;
  4054. }
  4055. return E1000_SUCCESS;
  4056. }
  4057. /******************************************************************************
  4058. * Returns the PHY to the power-on reset state
  4059. *
  4060. * hw - Struct containing variables accessed by shared code
  4061. ******************************************************************************/
  4062. int32_t
  4063. e1000_phy_hw_reset(struct e1000_hw *hw)
  4064. {
  4065. uint16_t swfw = E1000_SWFW_PHY0_SM;
  4066. uint32_t ctrl, ctrl_ext;
  4067. uint32_t led_ctrl;
  4068. int32_t ret_val;
  4069. DEBUGFUNC();
  4070. /* In the case of the phy reset being blocked, it's not an error, we
  4071. * simply return success without performing the reset. */
  4072. ret_val = e1000_check_phy_reset_block(hw);
  4073. if (ret_val)
  4074. return E1000_SUCCESS;
  4075. DEBUGOUT("Resetting Phy...\n");
  4076. if (hw->mac_type > e1000_82543) {
  4077. if (e1000_is_second_port(hw))
  4078. swfw = E1000_SWFW_PHY1_SM;
  4079. if (e1000_swfw_sync_acquire(hw, swfw)) {
  4080. DEBUGOUT("Unable to acquire swfw sync\n");
  4081. return -E1000_ERR_SWFW_SYNC;
  4082. }
  4083. /* Read the device control register and assert the E1000_CTRL_PHY_RST
  4084. * bit. Then, take it out of reset.
  4085. */
  4086. ctrl = E1000_READ_REG(hw, CTRL);
  4087. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
  4088. E1000_WRITE_FLUSH(hw);
  4089. if (hw->mac_type < e1000_82571)
  4090. udelay(10);
  4091. else
  4092. udelay(100);
  4093. E1000_WRITE_REG(hw, CTRL, ctrl);
  4094. E1000_WRITE_FLUSH(hw);
  4095. if (hw->mac_type >= e1000_82571)
  4096. mdelay(10);
  4097. } else {
  4098. /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
  4099. * bit to put the PHY into reset. Then, take it out of reset.
  4100. */
  4101. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4102. ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
  4103. ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
  4104. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4105. E1000_WRITE_FLUSH(hw);
  4106. mdelay(10);
  4107. ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
  4108. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4109. E1000_WRITE_FLUSH(hw);
  4110. }
  4111. udelay(150);
  4112. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  4113. /* Configure activity LED after PHY reset */
  4114. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  4115. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  4116. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  4117. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  4118. }
  4119. e1000_swfw_sync_release(hw, swfw);
  4120. /* Wait for FW to finish PHY configuration. */
  4121. ret_val = e1000_get_phy_cfg_done(hw);
  4122. if (ret_val != E1000_SUCCESS)
  4123. return ret_val;
  4124. return ret_val;
  4125. }
  4126. /******************************************************************************
  4127. * IGP phy init script - initializes the GbE PHY
  4128. *
  4129. * hw - Struct containing variables accessed by shared code
  4130. *****************************************************************************/
  4131. static void
  4132. e1000_phy_init_script(struct e1000_hw *hw)
  4133. {
  4134. uint32_t ret_val;
  4135. uint16_t phy_saved_data;
  4136. DEBUGFUNC();
  4137. if (hw->phy_init_script) {
  4138. mdelay(20);
  4139. /* Save off the current value of register 0x2F5B to be
  4140. * restored at the end of this routine. */
  4141. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  4142. /* Disabled the PHY transmitter */
  4143. e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  4144. mdelay(20);
  4145. e1000_write_phy_reg(hw, 0x0000, 0x0140);
  4146. mdelay(5);
  4147. switch (hw->mac_type) {
  4148. case e1000_82541:
  4149. case e1000_82547:
  4150. e1000_write_phy_reg(hw, 0x1F95, 0x0001);
  4151. e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
  4152. e1000_write_phy_reg(hw, 0x1F79, 0x0018);
  4153. e1000_write_phy_reg(hw, 0x1F30, 0x1600);
  4154. e1000_write_phy_reg(hw, 0x1F31, 0x0014);
  4155. e1000_write_phy_reg(hw, 0x1F32, 0x161C);
  4156. e1000_write_phy_reg(hw, 0x1F94, 0x0003);
  4157. e1000_write_phy_reg(hw, 0x1F96, 0x003F);
  4158. e1000_write_phy_reg(hw, 0x2010, 0x0008);
  4159. break;
  4160. case e1000_82541_rev_2:
  4161. case e1000_82547_rev_2:
  4162. e1000_write_phy_reg(hw, 0x1F73, 0x0099);
  4163. break;
  4164. default:
  4165. break;
  4166. }
  4167. e1000_write_phy_reg(hw, 0x0000, 0x3300);
  4168. mdelay(20);
  4169. /* Now enable the transmitter */
  4170. if (!ret_val)
  4171. e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  4172. if (hw->mac_type == e1000_82547) {
  4173. uint16_t fused, fine, coarse;
  4174. /* Move to analog registers page */
  4175. e1000_read_phy_reg(hw,
  4176. IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
  4177. if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
  4178. e1000_read_phy_reg(hw,
  4179. IGP01E1000_ANALOG_FUSE_STATUS, &fused);
  4180. fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
  4181. coarse = fused
  4182. & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
  4183. if (coarse >
  4184. IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
  4185. coarse -=
  4186. IGP01E1000_ANALOG_FUSE_COARSE_10;
  4187. fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
  4188. } else if (coarse
  4189. == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
  4190. fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
  4191. fused = (fused
  4192. & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
  4193. (fine
  4194. & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
  4195. (coarse
  4196. & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
  4197. e1000_write_phy_reg(hw,
  4198. IGP01E1000_ANALOG_FUSE_CONTROL, fused);
  4199. e1000_write_phy_reg(hw,
  4200. IGP01E1000_ANALOG_FUSE_BYPASS,
  4201. IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
  4202. }
  4203. }
  4204. }
  4205. }
  4206. /******************************************************************************
  4207. * Resets the PHY
  4208. *
  4209. * hw - Struct containing variables accessed by shared code
  4210. *
  4211. * Sets bit 15 of the MII Control register
  4212. ******************************************************************************/
  4213. int32_t
  4214. e1000_phy_reset(struct e1000_hw *hw)
  4215. {
  4216. int32_t ret_val;
  4217. uint16_t phy_data;
  4218. DEBUGFUNC();
  4219. /* In the case of the phy reset being blocked, it's not an error, we
  4220. * simply return success without performing the reset. */
  4221. ret_val = e1000_check_phy_reset_block(hw);
  4222. if (ret_val)
  4223. return E1000_SUCCESS;
  4224. switch (hw->phy_type) {
  4225. case e1000_phy_igp:
  4226. case e1000_phy_igp_2:
  4227. case e1000_phy_igp_3:
  4228. case e1000_phy_ife:
  4229. case e1000_phy_igb:
  4230. ret_val = e1000_phy_hw_reset(hw);
  4231. if (ret_val)
  4232. return ret_val;
  4233. break;
  4234. default:
  4235. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  4236. if (ret_val)
  4237. return ret_val;
  4238. phy_data |= MII_CR_RESET;
  4239. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  4240. if (ret_val)
  4241. return ret_val;
  4242. udelay(1);
  4243. break;
  4244. }
  4245. if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
  4246. e1000_phy_init_script(hw);
  4247. return E1000_SUCCESS;
  4248. }
  4249. static int e1000_set_phy_type (struct e1000_hw *hw)
  4250. {
  4251. DEBUGFUNC ();
  4252. if (hw->mac_type == e1000_undefined)
  4253. return -E1000_ERR_PHY_TYPE;
  4254. switch (hw->phy_id) {
  4255. case M88E1000_E_PHY_ID:
  4256. case M88E1000_I_PHY_ID:
  4257. case M88E1011_I_PHY_ID:
  4258. case M88E1111_I_PHY_ID:
  4259. hw->phy_type = e1000_phy_m88;
  4260. break;
  4261. case IGP01E1000_I_PHY_ID:
  4262. if (hw->mac_type == e1000_82541 ||
  4263. hw->mac_type == e1000_82541_rev_2 ||
  4264. hw->mac_type == e1000_82547 ||
  4265. hw->mac_type == e1000_82547_rev_2) {
  4266. hw->phy_type = e1000_phy_igp;
  4267. break;
  4268. }
  4269. case IGP03E1000_E_PHY_ID:
  4270. hw->phy_type = e1000_phy_igp_3;
  4271. break;
  4272. case IFE_E_PHY_ID:
  4273. case IFE_PLUS_E_PHY_ID:
  4274. case IFE_C_E_PHY_ID:
  4275. hw->phy_type = e1000_phy_ife;
  4276. break;
  4277. case GG82563_E_PHY_ID:
  4278. if (hw->mac_type == e1000_80003es2lan) {
  4279. hw->phy_type = e1000_phy_gg82563;
  4280. break;
  4281. }
  4282. case BME1000_E_PHY_ID:
  4283. hw->phy_type = e1000_phy_bm;
  4284. break;
  4285. case I210_I_PHY_ID:
  4286. hw->phy_type = e1000_phy_igb;
  4287. break;
  4288. /* Fall Through */
  4289. default:
  4290. /* Should never have loaded on this device */
  4291. hw->phy_type = e1000_phy_undefined;
  4292. return -E1000_ERR_PHY_TYPE;
  4293. }
  4294. return E1000_SUCCESS;
  4295. }
  4296. /******************************************************************************
  4297. * Probes the expected PHY address for known PHY IDs
  4298. *
  4299. * hw - Struct containing variables accessed by shared code
  4300. ******************************************************************************/
  4301. static int32_t
  4302. e1000_detect_gig_phy(struct e1000_hw *hw)
  4303. {
  4304. int32_t phy_init_status, ret_val;
  4305. uint16_t phy_id_high, phy_id_low;
  4306. bool match = false;
  4307. DEBUGFUNC();
  4308. /* The 82571 firmware may still be configuring the PHY. In this
  4309. * case, we cannot access the PHY until the configuration is done. So
  4310. * we explicitly set the PHY values. */
  4311. if (hw->mac_type == e1000_82571 ||
  4312. hw->mac_type == e1000_82572) {
  4313. hw->phy_id = IGP01E1000_I_PHY_ID;
  4314. hw->phy_type = e1000_phy_igp_2;
  4315. return E1000_SUCCESS;
  4316. }
  4317. /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
  4318. * work- around that forces PHY page 0 to be set or the reads fail.
  4319. * The rest of the code in this routine uses e1000_read_phy_reg to
  4320. * read the PHY ID. So for ESB-2 we need to have this set so our
  4321. * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
  4322. * the routines below will figure this out as well. */
  4323. if (hw->mac_type == e1000_80003es2lan)
  4324. hw->phy_type = e1000_phy_gg82563;
  4325. /* Read the PHY ID Registers to identify which PHY is onboard. */
  4326. ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
  4327. if (ret_val)
  4328. return ret_val;
  4329. hw->phy_id = (uint32_t) (phy_id_high << 16);
  4330. udelay(20);
  4331. ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
  4332. if (ret_val)
  4333. return ret_val;
  4334. hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  4335. hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  4336. switch (hw->mac_type) {
  4337. case e1000_82543:
  4338. if (hw->phy_id == M88E1000_E_PHY_ID)
  4339. match = true;
  4340. break;
  4341. case e1000_82544:
  4342. if (hw->phy_id == M88E1000_I_PHY_ID)
  4343. match = true;
  4344. break;
  4345. case e1000_82540:
  4346. case e1000_82545:
  4347. case e1000_82545_rev_3:
  4348. case e1000_82546:
  4349. case e1000_82546_rev_3:
  4350. if (hw->phy_id == M88E1011_I_PHY_ID)
  4351. match = true;
  4352. break;
  4353. case e1000_82541:
  4354. case e1000_82541_rev_2:
  4355. case e1000_82547:
  4356. case e1000_82547_rev_2:
  4357. if(hw->phy_id == IGP01E1000_I_PHY_ID)
  4358. match = true;
  4359. break;
  4360. case e1000_82573:
  4361. if (hw->phy_id == M88E1111_I_PHY_ID)
  4362. match = true;
  4363. break;
  4364. case e1000_82574:
  4365. if (hw->phy_id == BME1000_E_PHY_ID)
  4366. match = true;
  4367. break;
  4368. case e1000_80003es2lan:
  4369. if (hw->phy_id == GG82563_E_PHY_ID)
  4370. match = true;
  4371. break;
  4372. case e1000_ich8lan:
  4373. if (hw->phy_id == IGP03E1000_E_PHY_ID)
  4374. match = true;
  4375. if (hw->phy_id == IFE_E_PHY_ID)
  4376. match = true;
  4377. if (hw->phy_id == IFE_PLUS_E_PHY_ID)
  4378. match = true;
  4379. if (hw->phy_id == IFE_C_E_PHY_ID)
  4380. match = true;
  4381. break;
  4382. case e1000_igb:
  4383. if (hw->phy_id == I210_I_PHY_ID)
  4384. match = true;
  4385. break;
  4386. default:
  4387. DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
  4388. return -E1000_ERR_CONFIG;
  4389. }
  4390. phy_init_status = e1000_set_phy_type(hw);
  4391. if ((match) && (phy_init_status == E1000_SUCCESS)) {
  4392. DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
  4393. return 0;
  4394. }
  4395. DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
  4396. return -E1000_ERR_PHY;
  4397. }
  4398. /*****************************************************************************
  4399. * Set media type and TBI compatibility.
  4400. *
  4401. * hw - Struct containing variables accessed by shared code
  4402. * **************************************************************************/
  4403. void
  4404. e1000_set_media_type(struct e1000_hw *hw)
  4405. {
  4406. uint32_t status;
  4407. DEBUGFUNC();
  4408. if (hw->mac_type != e1000_82543) {
  4409. /* tbi_compatibility is only valid on 82543 */
  4410. hw->tbi_compatibility_en = false;
  4411. }
  4412. switch (hw->device_id) {
  4413. case E1000_DEV_ID_82545GM_SERDES:
  4414. case E1000_DEV_ID_82546GB_SERDES:
  4415. case E1000_DEV_ID_82571EB_SERDES:
  4416. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  4417. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  4418. case E1000_DEV_ID_82572EI_SERDES:
  4419. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  4420. hw->media_type = e1000_media_type_internal_serdes;
  4421. break;
  4422. default:
  4423. switch (hw->mac_type) {
  4424. case e1000_82542_rev2_0:
  4425. case e1000_82542_rev2_1:
  4426. hw->media_type = e1000_media_type_fiber;
  4427. break;
  4428. case e1000_ich8lan:
  4429. case e1000_82573:
  4430. case e1000_82574:
  4431. case e1000_igb:
  4432. /* The STATUS_TBIMODE bit is reserved or reused
  4433. * for the this device.
  4434. */
  4435. hw->media_type = e1000_media_type_copper;
  4436. break;
  4437. default:
  4438. status = E1000_READ_REG(hw, STATUS);
  4439. if (status & E1000_STATUS_TBIMODE) {
  4440. hw->media_type = e1000_media_type_fiber;
  4441. /* tbi_compatibility not valid on fiber */
  4442. hw->tbi_compatibility_en = false;
  4443. } else {
  4444. hw->media_type = e1000_media_type_copper;
  4445. }
  4446. break;
  4447. }
  4448. }
  4449. }
  4450. /**
  4451. * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  4452. *
  4453. * e1000_sw_init initializes the Adapter private data structure.
  4454. * Fields are initialized based on PCI device information and
  4455. * OS network device settings (MTU size).
  4456. **/
  4457. static int
  4458. e1000_sw_init(struct e1000_hw *hw)
  4459. {
  4460. int result;
  4461. /* PCI config space info */
  4462. #ifdef CONFIG_DM_ETH
  4463. dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4464. dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4465. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4466. &hw->subsystem_vendor_id);
  4467. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4468. dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4469. dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4470. #else
  4471. pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4472. pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4473. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4474. &hw->subsystem_vendor_id);
  4475. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4476. pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4477. pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4478. #endif
  4479. /* identify the MAC */
  4480. result = e1000_set_mac_type(hw);
  4481. if (result) {
  4482. E1000_ERR(hw, "Unknown MAC Type\n");
  4483. return result;
  4484. }
  4485. switch (hw->mac_type) {
  4486. default:
  4487. break;
  4488. case e1000_82541:
  4489. case e1000_82547:
  4490. case e1000_82541_rev_2:
  4491. case e1000_82547_rev_2:
  4492. hw->phy_init_script = 1;
  4493. break;
  4494. }
  4495. /* flow control settings */
  4496. hw->fc_high_water = E1000_FC_HIGH_THRESH;
  4497. hw->fc_low_water = E1000_FC_LOW_THRESH;
  4498. hw->fc_pause_time = E1000_FC_PAUSE_TIME;
  4499. hw->fc_send_xon = 1;
  4500. /* Media type - copper or fiber */
  4501. hw->tbi_compatibility_en = true;
  4502. e1000_set_media_type(hw);
  4503. if (hw->mac_type >= e1000_82543) {
  4504. uint32_t status = E1000_READ_REG(hw, STATUS);
  4505. if (status & E1000_STATUS_TBIMODE) {
  4506. DEBUGOUT("fiber interface\n");
  4507. hw->media_type = e1000_media_type_fiber;
  4508. } else {
  4509. DEBUGOUT("copper interface\n");
  4510. hw->media_type = e1000_media_type_copper;
  4511. }
  4512. } else {
  4513. hw->media_type = e1000_media_type_fiber;
  4514. }
  4515. hw->wait_autoneg_complete = true;
  4516. if (hw->mac_type < e1000_82543)
  4517. hw->report_tx_early = 0;
  4518. else
  4519. hw->report_tx_early = 1;
  4520. return E1000_SUCCESS;
  4521. }
  4522. void
  4523. fill_rx(struct e1000_hw *hw)
  4524. {
  4525. struct e1000_rx_desc *rd;
  4526. unsigned long flush_start, flush_end;
  4527. rx_last = rx_tail;
  4528. rd = rx_base + rx_tail;
  4529. rx_tail = (rx_tail + 1) % 8;
  4530. memset(rd, 0, 16);
  4531. rd->buffer_addr = cpu_to_le64(virt_to_phys(packet));
  4532. /*
  4533. * Make sure there are no stale data in WB over this area, which
  4534. * might get written into the memory while the e1000 also writes
  4535. * into the same memory area.
  4536. */
  4537. invalidate_dcache_range((unsigned long)packet,
  4538. (unsigned long)packet + 4096);
  4539. /* Dump the DMA descriptor into RAM. */
  4540. flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4541. flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4542. flush_dcache_range(flush_start, flush_end);
  4543. E1000_WRITE_REG(hw, RDT, rx_tail);
  4544. }
  4545. /**
  4546. * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  4547. * @adapter: board private structure
  4548. *
  4549. * Configure the Tx unit of the MAC after a reset.
  4550. **/
  4551. static void
  4552. e1000_configure_tx(struct e1000_hw *hw)
  4553. {
  4554. unsigned long tctl;
  4555. unsigned long tipg, tarc;
  4556. uint32_t ipgr1, ipgr2;
  4557. E1000_WRITE_REG(hw, TDBAL, lower_32_bits(virt_to_phys(tx_base)));
  4558. E1000_WRITE_REG(hw, TDBAH, upper_32_bits(virt_to_phys(tx_base)));
  4559. E1000_WRITE_REG(hw, TDLEN, 128);
  4560. /* Setup the HW Tx Head and Tail descriptor pointers */
  4561. E1000_WRITE_REG(hw, TDH, 0);
  4562. E1000_WRITE_REG(hw, TDT, 0);
  4563. tx_tail = 0;
  4564. /* Set the default values for the Tx Inter Packet Gap timer */
  4565. if (hw->mac_type <= e1000_82547_rev_2 &&
  4566. (hw->media_type == e1000_media_type_fiber ||
  4567. hw->media_type == e1000_media_type_internal_serdes))
  4568. tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  4569. else
  4570. tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  4571. /* Set the default values for the Tx Inter Packet Gap timer */
  4572. switch (hw->mac_type) {
  4573. case e1000_82542_rev2_0:
  4574. case e1000_82542_rev2_1:
  4575. tipg = DEFAULT_82542_TIPG_IPGT;
  4576. ipgr1 = DEFAULT_82542_TIPG_IPGR1;
  4577. ipgr2 = DEFAULT_82542_TIPG_IPGR2;
  4578. break;
  4579. case e1000_80003es2lan:
  4580. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4581. ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
  4582. break;
  4583. default:
  4584. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4585. ipgr2 = DEFAULT_82543_TIPG_IPGR2;
  4586. break;
  4587. }
  4588. tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
  4589. tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
  4590. E1000_WRITE_REG(hw, TIPG, tipg);
  4591. /* Program the Transmit Control Register */
  4592. tctl = E1000_READ_REG(hw, TCTL);
  4593. tctl &= ~E1000_TCTL_CT;
  4594. tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
  4595. (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  4596. if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
  4597. tarc = E1000_READ_REG(hw, TARC0);
  4598. /* set the speed mode bit, we'll clear it if we're not at
  4599. * gigabit link later */
  4600. /* git bit can be set to 1*/
  4601. } else if (hw->mac_type == e1000_80003es2lan) {
  4602. tarc = E1000_READ_REG(hw, TARC0);
  4603. tarc |= 1;
  4604. E1000_WRITE_REG(hw, TARC0, tarc);
  4605. tarc = E1000_READ_REG(hw, TARC1);
  4606. tarc |= 1;
  4607. E1000_WRITE_REG(hw, TARC1, tarc);
  4608. }
  4609. e1000_config_collision_dist(hw);
  4610. /* Setup Transmit Descriptor Settings for eop descriptor */
  4611. hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
  4612. /* Need to set up RS bit */
  4613. if (hw->mac_type < e1000_82543)
  4614. hw->txd_cmd |= E1000_TXD_CMD_RPS;
  4615. else
  4616. hw->txd_cmd |= E1000_TXD_CMD_RS;
  4617. if (hw->mac_type == e1000_igb) {
  4618. E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
  4619. uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  4620. reg_txdctl |= 1 << 25;
  4621. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  4622. mdelay(20);
  4623. }
  4624. E1000_WRITE_REG(hw, TCTL, tctl);
  4625. }
  4626. /**
  4627. * e1000_setup_rctl - configure the receive control register
  4628. * @adapter: Board private structure
  4629. **/
  4630. static void
  4631. e1000_setup_rctl(struct e1000_hw *hw)
  4632. {
  4633. uint32_t rctl;
  4634. rctl = E1000_READ_REG(hw, RCTL);
  4635. rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  4636. rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
  4637. | E1000_RCTL_RDMTS_HALF; /* |
  4638. (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
  4639. if (hw->tbi_compatibility_on == 1)
  4640. rctl |= E1000_RCTL_SBP;
  4641. else
  4642. rctl &= ~E1000_RCTL_SBP;
  4643. rctl &= ~(E1000_RCTL_SZ_4096);
  4644. rctl |= E1000_RCTL_SZ_2048;
  4645. rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
  4646. E1000_WRITE_REG(hw, RCTL, rctl);
  4647. }
  4648. /**
  4649. * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  4650. * @adapter: board private structure
  4651. *
  4652. * Configure the Rx unit of the MAC after a reset.
  4653. **/
  4654. static void
  4655. e1000_configure_rx(struct e1000_hw *hw)
  4656. {
  4657. unsigned long rctl, ctrl_ext;
  4658. rx_tail = 0;
  4659. /* make sure receives are disabled while setting up the descriptors */
  4660. rctl = E1000_READ_REG(hw, RCTL);
  4661. E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
  4662. if (hw->mac_type >= e1000_82540) {
  4663. /* Set the interrupt throttling rate. Value is calculated
  4664. * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
  4665. #define MAX_INTS_PER_SEC 8000
  4666. #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
  4667. E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
  4668. }
  4669. if (hw->mac_type >= e1000_82571) {
  4670. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4671. /* Reset delay timers after every interrupt */
  4672. ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
  4673. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4674. E1000_WRITE_FLUSH(hw);
  4675. }
  4676. /* Setup the Base and Length of the Rx Descriptor Ring */
  4677. E1000_WRITE_REG(hw, RDBAL, lower_32_bits(virt_to_phys(rx_base)));
  4678. E1000_WRITE_REG(hw, RDBAH, upper_32_bits(virt_to_phys(rx_base)));
  4679. E1000_WRITE_REG(hw, RDLEN, 128);
  4680. /* Setup the HW Rx Head and Tail Descriptor Pointers */
  4681. E1000_WRITE_REG(hw, RDH, 0);
  4682. E1000_WRITE_REG(hw, RDT, 0);
  4683. /* Enable Receives */
  4684. if (hw->mac_type == e1000_igb) {
  4685. uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
  4686. reg_rxdctl |= 1 << 25;
  4687. E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
  4688. mdelay(20);
  4689. }
  4690. E1000_WRITE_REG(hw, RCTL, rctl);
  4691. fill_rx(hw);
  4692. }
  4693. /**************************************************************************
  4694. POLL - Wait for a frame
  4695. ***************************************************************************/
  4696. static int
  4697. _e1000_poll(struct e1000_hw *hw)
  4698. {
  4699. struct e1000_rx_desc *rd;
  4700. unsigned long inval_start, inval_end;
  4701. uint32_t len;
  4702. /* return true if there's an ethernet packet ready to read */
  4703. rd = rx_base + rx_last;
  4704. /* Re-load the descriptor from RAM. */
  4705. inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4706. inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4707. invalidate_dcache_range(inval_start, inval_end);
  4708. if (!(rd->status & E1000_RXD_STAT_DD))
  4709. return 0;
  4710. /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
  4711. /* Packet received, make sure the data are re-loaded from RAM. */
  4712. len = le16_to_cpu(rd->length);
  4713. invalidate_dcache_range((unsigned long)packet,
  4714. (unsigned long)packet +
  4715. roundup(len, ARCH_DMA_MINALIGN));
  4716. return len;
  4717. }
  4718. static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
  4719. {
  4720. void *nv_packet = (void *)txpacket;
  4721. struct e1000_tx_desc *txp;
  4722. int i = 0;
  4723. unsigned long flush_start, flush_end;
  4724. txp = tx_base + tx_tail;
  4725. tx_tail = (tx_tail + 1) % 8;
  4726. txp->buffer_addr = cpu_to_le64(virt_to_phys(nv_packet));
  4727. txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
  4728. txp->upper.data = 0;
  4729. /* Dump the packet into RAM so e1000 can pick them. */
  4730. flush_dcache_range((unsigned long)nv_packet,
  4731. (unsigned long)nv_packet +
  4732. roundup(length, ARCH_DMA_MINALIGN));
  4733. /* Dump the descriptor into RAM as well. */
  4734. flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
  4735. flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
  4736. flush_dcache_range(flush_start, flush_end);
  4737. E1000_WRITE_REG(hw, TDT, tx_tail);
  4738. E1000_WRITE_FLUSH(hw);
  4739. while (1) {
  4740. invalidate_dcache_range(flush_start, flush_end);
  4741. if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
  4742. break;
  4743. if (i++ > TOUT_LOOP) {
  4744. DEBUGOUT("e1000: tx timeout\n");
  4745. return 0;
  4746. }
  4747. udelay(10); /* give the nic a chance to write to the register */
  4748. }
  4749. return 1;
  4750. }
  4751. static void
  4752. _e1000_disable(struct e1000_hw *hw)
  4753. {
  4754. /* Turn off the ethernet interface */
  4755. E1000_WRITE_REG(hw, RCTL, 0);
  4756. E1000_WRITE_REG(hw, TCTL, 0);
  4757. /* Clear the transmit ring */
  4758. E1000_WRITE_REG(hw, TDH, 0);
  4759. E1000_WRITE_REG(hw, TDT, 0);
  4760. /* Clear the receive ring */
  4761. E1000_WRITE_REG(hw, RDH, 0);
  4762. E1000_WRITE_REG(hw, RDT, 0);
  4763. mdelay(10);
  4764. }
  4765. /*reset function*/
  4766. static inline int
  4767. e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
  4768. {
  4769. e1000_reset_hw(hw);
  4770. if (hw->mac_type >= e1000_82544)
  4771. E1000_WRITE_REG(hw, WUC, 0);
  4772. return e1000_init_hw(hw, enetaddr);
  4773. }
  4774. static int
  4775. _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
  4776. {
  4777. int ret_val = 0;
  4778. ret_val = e1000_reset(hw, enetaddr);
  4779. if (ret_val < 0) {
  4780. if ((ret_val == -E1000_ERR_NOLINK) ||
  4781. (ret_val == -E1000_ERR_TIMEOUT)) {
  4782. E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
  4783. } else {
  4784. E1000_ERR(hw, "Hardware Initialization Failed\n");
  4785. }
  4786. return ret_val;
  4787. }
  4788. e1000_configure_tx(hw);
  4789. e1000_setup_rctl(hw);
  4790. e1000_configure_rx(hw);
  4791. return 0;
  4792. }
  4793. /******************************************************************************
  4794. * Gets the current PCI bus type of hardware
  4795. *
  4796. * hw - Struct containing variables accessed by shared code
  4797. *****************************************************************************/
  4798. void e1000_get_bus_type(struct e1000_hw *hw)
  4799. {
  4800. uint32_t status;
  4801. switch (hw->mac_type) {
  4802. case e1000_82542_rev2_0:
  4803. case e1000_82542_rev2_1:
  4804. hw->bus_type = e1000_bus_type_pci;
  4805. break;
  4806. case e1000_82571:
  4807. case e1000_82572:
  4808. case e1000_82573:
  4809. case e1000_82574:
  4810. case e1000_80003es2lan:
  4811. case e1000_ich8lan:
  4812. case e1000_igb:
  4813. hw->bus_type = e1000_bus_type_pci_express;
  4814. break;
  4815. default:
  4816. status = E1000_READ_REG(hw, STATUS);
  4817. hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  4818. e1000_bus_type_pcix : e1000_bus_type_pci;
  4819. break;
  4820. }
  4821. }
  4822. #ifndef CONFIG_DM_ETH
  4823. /* A list of all registered e1000 devices */
  4824. static LIST_HEAD(e1000_hw_list);
  4825. #endif
  4826. #ifdef CONFIG_DM_ETH
  4827. static int e1000_init_one(struct e1000_hw *hw, int cardnum,
  4828. struct udevice *devno, unsigned char enetaddr[6])
  4829. #else
  4830. static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
  4831. unsigned char enetaddr[6])
  4832. #endif
  4833. {
  4834. u32 val;
  4835. /* Assign the passed-in values */
  4836. #ifdef CONFIG_DM_ETH
  4837. hw->pdev = devno;
  4838. #else
  4839. hw->pdev = devno;
  4840. #endif
  4841. hw->cardnum = cardnum;
  4842. /* Print a debug message with the IO base address */
  4843. #ifdef CONFIG_DM_ETH
  4844. dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
  4845. #else
  4846. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
  4847. #endif
  4848. E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
  4849. /* Try to enable I/O accesses and bus-mastering */
  4850. val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  4851. #ifdef CONFIG_DM_ETH
  4852. dm_pci_write_config32(devno, PCI_COMMAND, val);
  4853. #else
  4854. pci_write_config_dword(devno, PCI_COMMAND, val);
  4855. #endif
  4856. /* Make sure it worked */
  4857. #ifdef CONFIG_DM_ETH
  4858. dm_pci_read_config32(devno, PCI_COMMAND, &val);
  4859. #else
  4860. pci_read_config_dword(devno, PCI_COMMAND, &val);
  4861. #endif
  4862. if (!(val & PCI_COMMAND_MEMORY)) {
  4863. E1000_ERR(hw, "Can't enable I/O memory\n");
  4864. return -ENOSPC;
  4865. }
  4866. if (!(val & PCI_COMMAND_MASTER)) {
  4867. E1000_ERR(hw, "Can't enable bus-mastering\n");
  4868. return -EPERM;
  4869. }
  4870. /* Are these variables needed? */
  4871. hw->fc = e1000_fc_default;
  4872. hw->original_fc = e1000_fc_default;
  4873. hw->autoneg_failed = 0;
  4874. hw->autoneg = 1;
  4875. hw->get_link_status = true;
  4876. #ifndef CONFIG_E1000_NO_NVM
  4877. hw->eeprom_semaphore_present = true;
  4878. #endif
  4879. #ifdef CONFIG_DM_ETH
  4880. hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4881. PCI_REGION_MEM);
  4882. #else
  4883. hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4884. PCI_REGION_MEM);
  4885. #endif
  4886. hw->mac_type = e1000_undefined;
  4887. /* MAC and Phy settings */
  4888. if (e1000_sw_init(hw) < 0) {
  4889. E1000_ERR(hw, "Software init failed\n");
  4890. return -EIO;
  4891. }
  4892. if (e1000_check_phy_reset_block(hw))
  4893. E1000_ERR(hw, "PHY Reset is blocked!\n");
  4894. /* Basic init was OK, reset the hardware and allow SPI access */
  4895. e1000_reset_hw(hw);
  4896. #ifndef CONFIG_E1000_NO_NVM
  4897. /* Validate the EEPROM and get chipset information */
  4898. if (e1000_init_eeprom_params(hw)) {
  4899. E1000_ERR(hw, "EEPROM is invalid!\n");
  4900. return -EINVAL;
  4901. }
  4902. if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
  4903. e1000_validate_eeprom_checksum(hw))
  4904. return -ENXIO;
  4905. e1000_read_mac_addr(hw, enetaddr);
  4906. #endif
  4907. e1000_get_bus_type(hw);
  4908. #ifndef CONFIG_E1000_NO_NVM
  4909. printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
  4910. enetaddr[0], enetaddr[1], enetaddr[2],
  4911. enetaddr[3], enetaddr[4], enetaddr[5]);
  4912. #else
  4913. memset(enetaddr, 0, 6);
  4914. printf("e1000: no NVM\n");
  4915. #endif
  4916. return 0;
  4917. }
  4918. /* Put the name of a device in a string */
  4919. static void e1000_name(char *str, int cardnum)
  4920. {
  4921. sprintf(str, "e1000#%u", cardnum);
  4922. }
  4923. #ifndef CONFIG_DM_ETH
  4924. /**************************************************************************
  4925. TRANSMIT - Transmit a frame
  4926. ***************************************************************************/
  4927. static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
  4928. {
  4929. struct e1000_hw *hw = nic->priv;
  4930. return _e1000_transmit(hw, txpacket, length);
  4931. }
  4932. /**************************************************************************
  4933. DISABLE - Turn off ethernet interface
  4934. ***************************************************************************/
  4935. static void
  4936. e1000_disable(struct eth_device *nic)
  4937. {
  4938. struct e1000_hw *hw = nic->priv;
  4939. _e1000_disable(hw);
  4940. }
  4941. /**************************************************************************
  4942. INIT - set up ethernet interface(s)
  4943. ***************************************************************************/
  4944. static int
  4945. e1000_init(struct eth_device *nic, struct bd_info *bis)
  4946. {
  4947. struct e1000_hw *hw = nic->priv;
  4948. return _e1000_init(hw, nic->enetaddr);
  4949. }
  4950. static int
  4951. e1000_poll(struct eth_device *nic)
  4952. {
  4953. struct e1000_hw *hw = nic->priv;
  4954. int len;
  4955. len = _e1000_poll(hw);
  4956. if (len) {
  4957. net_process_received_packet((uchar *)packet, len);
  4958. fill_rx(hw);
  4959. }
  4960. return len ? 1 : 0;
  4961. }
  4962. #endif /* !CONFIG_DM_ETH */
  4963. #ifdef CONFIG_DM_ETH
  4964. static int e1000_write_hwaddr(struct udevice *dev)
  4965. #else
  4966. static int e1000_write_hwaddr(struct eth_device *dev)
  4967. #endif
  4968. {
  4969. #ifndef CONFIG_E1000_NO_NVM
  4970. unsigned char current_mac[6];
  4971. #ifdef CONFIG_DM_ETH
  4972. struct eth_pdata *plat = dev_get_plat(dev);
  4973. struct e1000_hw *hw = dev_get_priv(dev);
  4974. u8 *mac = plat->enetaddr;
  4975. #else
  4976. struct e1000_hw *hw = dev->priv;
  4977. u8 *mac = dev->enetaddr;
  4978. #endif
  4979. uint16_t data[3];
  4980. int ret_val, i;
  4981. DEBUGOUT("%s: mac=%pM\n", __func__, mac);
  4982. if ((hw->eeprom.type == e1000_eeprom_invm) &&
  4983. !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210))
  4984. return -ENOSYS;
  4985. memset(current_mac, 0, 6);
  4986. /* Read from EEPROM, not from registers, to make sure
  4987. * the address is persistently configured
  4988. */
  4989. ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
  4990. DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
  4991. /* Only write to EEPROM if the given address is different or
  4992. * reading the current address failed
  4993. */
  4994. if (!ret_val && memcmp(current_mac, mac, 6) == 0)
  4995. return 0;
  4996. for (i = 0; i < 3; ++i)
  4997. data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
  4998. ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
  4999. if (!ret_val)
  5000. ret_val = e1000_update_eeprom_checksum_i210(hw);
  5001. return ret_val;
  5002. #else
  5003. return 0;
  5004. #endif
  5005. }
  5006. #ifndef CONFIG_DM_ETH
  5007. /**************************************************************************
  5008. PROBE - Look for an adapter, this routine's visible to the outside
  5009. You should omit the last argument struct pci_device * for a non-PCI NIC
  5010. ***************************************************************************/
  5011. int
  5012. e1000_initialize(struct bd_info * bis)
  5013. {
  5014. unsigned int i;
  5015. pci_dev_t devno;
  5016. int ret;
  5017. DEBUGFUNC();
  5018. /* Find and probe all the matching PCI devices */
  5019. for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
  5020. /*
  5021. * These will never get freed due to errors, this allows us to
  5022. * perform SPI EEPROM programming from U-Boot, for example.
  5023. */
  5024. struct eth_device *nic = malloc(sizeof(*nic));
  5025. struct e1000_hw *hw = malloc(sizeof(*hw));
  5026. if (!nic || !hw) {
  5027. printf("e1000#%u: Out of Memory!\n", i);
  5028. free(nic);
  5029. free(hw);
  5030. continue;
  5031. }
  5032. /* Make sure all of the fields are initially zeroed */
  5033. memset(nic, 0, sizeof(*nic));
  5034. memset(hw, 0, sizeof(*hw));
  5035. nic->priv = hw;
  5036. /* Generate a card name */
  5037. e1000_name(nic->name, i);
  5038. hw->name = nic->name;
  5039. ret = e1000_init_one(hw, i, devno, nic->enetaddr);
  5040. if (ret)
  5041. continue;
  5042. list_add_tail(&hw->list_node, &e1000_hw_list);
  5043. hw->nic = nic;
  5044. /* Set up the function pointers and register the device */
  5045. nic->init = e1000_init;
  5046. nic->recv = e1000_poll;
  5047. nic->send = e1000_transmit;
  5048. nic->halt = e1000_disable;
  5049. nic->write_hwaddr = e1000_write_hwaddr;
  5050. eth_register(nic);
  5051. }
  5052. return i;
  5053. }
  5054. struct e1000_hw *e1000_find_card(unsigned int cardnum)
  5055. {
  5056. struct e1000_hw *hw;
  5057. list_for_each_entry(hw, &e1000_hw_list, list_node)
  5058. if (hw->cardnum == cardnum)
  5059. return hw;
  5060. return NULL;
  5061. }
  5062. #endif /* !CONFIG_DM_ETH */
  5063. #ifdef CONFIG_CMD_E1000
  5064. static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
  5065. char *const argv[])
  5066. {
  5067. unsigned char *mac = NULL;
  5068. #ifdef CONFIG_DM_ETH
  5069. struct eth_pdata *plat;
  5070. struct udevice *dev;
  5071. char name[30];
  5072. int ret;
  5073. #endif
  5074. #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
  5075. struct e1000_hw *hw;
  5076. #endif
  5077. int cardnum;
  5078. if (argc < 3) {
  5079. cmd_usage(cmdtp);
  5080. return 1;
  5081. }
  5082. /* Make sure we can find the requested e1000 card */
  5083. cardnum = dectoul(argv[1], NULL);
  5084. #ifdef CONFIG_DM_ETH
  5085. e1000_name(name, cardnum);
  5086. ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
  5087. if (!ret) {
  5088. plat = dev_get_plat(dev);
  5089. mac = plat->enetaddr;
  5090. }
  5091. #else
  5092. hw = e1000_find_card(cardnum);
  5093. if (hw)
  5094. mac = hw->nic->enetaddr;
  5095. #endif
  5096. if (!mac) {
  5097. printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
  5098. return 1;
  5099. }
  5100. if (!strcmp(argv[2], "print-mac-address")) {
  5101. printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
  5102. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  5103. return 0;
  5104. }
  5105. #ifdef CONFIG_E1000_SPI
  5106. #ifdef CONFIG_DM_ETH
  5107. hw = dev_get_priv(dev);
  5108. #endif
  5109. /* Handle the "SPI" subcommand */
  5110. if (!strcmp(argv[2], "spi"))
  5111. return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
  5112. #endif
  5113. cmd_usage(cmdtp);
  5114. return 1;
  5115. }
  5116. U_BOOT_CMD(
  5117. e1000, 7, 0, do_e1000,
  5118. "Intel e1000 controller management",
  5119. /* */"<card#> print-mac-address\n"
  5120. #ifdef CONFIG_E1000_SPI
  5121. "e1000 <card#> spi show [<offset> [<length>]]\n"
  5122. "e1000 <card#> spi dump <addr> <offset> <length>\n"
  5123. "e1000 <card#> spi program <addr> <offset> <length>\n"
  5124. "e1000 <card#> spi checksum [update]\n"
  5125. #endif
  5126. " - Manage the Intel E1000 PCI device"
  5127. );
  5128. #endif /* not CONFIG_CMD_E1000 */
  5129. #ifdef CONFIG_DM_ETH
  5130. static int e1000_eth_start(struct udevice *dev)
  5131. {
  5132. struct eth_pdata *plat = dev_get_plat(dev);
  5133. struct e1000_hw *hw = dev_get_priv(dev);
  5134. return _e1000_init(hw, plat->enetaddr);
  5135. }
  5136. static void e1000_eth_stop(struct udevice *dev)
  5137. {
  5138. struct e1000_hw *hw = dev_get_priv(dev);
  5139. _e1000_disable(hw);
  5140. }
  5141. static int e1000_eth_send(struct udevice *dev, void *packet, int length)
  5142. {
  5143. struct e1000_hw *hw = dev_get_priv(dev);
  5144. int ret;
  5145. ret = _e1000_transmit(hw, packet, length);
  5146. return ret ? 0 : -ETIMEDOUT;
  5147. }
  5148. static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  5149. {
  5150. struct e1000_hw *hw = dev_get_priv(dev);
  5151. int len;
  5152. len = _e1000_poll(hw);
  5153. if (len)
  5154. *packetp = packet;
  5155. return len ? len : -EAGAIN;
  5156. }
  5157. static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
  5158. {
  5159. struct e1000_hw *hw = dev_get_priv(dev);
  5160. fill_rx(hw);
  5161. return 0;
  5162. }
  5163. static int e1000_eth_probe(struct udevice *dev)
  5164. {
  5165. struct eth_pdata *plat = dev_get_plat(dev);
  5166. struct e1000_hw *hw = dev_get_priv(dev);
  5167. int ret;
  5168. hw->name = dev->name;
  5169. ret = e1000_init_one(hw, trailing_strtol(dev->name),
  5170. dev, plat->enetaddr);
  5171. if (ret < 0) {
  5172. printf(pr_fmt("failed to initialize card: %d\n"), ret);
  5173. return ret;
  5174. }
  5175. return 0;
  5176. }
  5177. static int e1000_eth_bind(struct udevice *dev)
  5178. {
  5179. char name[20];
  5180. /*
  5181. * A simple way to number the devices. When device tree is used this
  5182. * is unnecessary, but when the device is just discovered on the PCI
  5183. * bus we need a name. We could instead have the uclass figure out
  5184. * which devices are different and number them.
  5185. */
  5186. e1000_name(name, num_cards++);
  5187. return device_set_name(dev, name);
  5188. }
  5189. static const struct eth_ops e1000_eth_ops = {
  5190. .start = e1000_eth_start,
  5191. .send = e1000_eth_send,
  5192. .recv = e1000_eth_recv,
  5193. .stop = e1000_eth_stop,
  5194. .free_pkt = e1000_free_pkt,
  5195. .write_hwaddr = e1000_write_hwaddr,
  5196. };
  5197. static const struct udevice_id e1000_eth_ids[] = {
  5198. { .compatible = "intel,e1000" },
  5199. { }
  5200. };
  5201. U_BOOT_DRIVER(eth_e1000) = {
  5202. .name = "eth_e1000",
  5203. .id = UCLASS_ETH,
  5204. .of_match = e1000_eth_ids,
  5205. .bind = e1000_eth_bind,
  5206. .probe = e1000_eth_probe,
  5207. .ops = &e1000_eth_ops,
  5208. .priv_auto = sizeof(struct e1000_hw),
  5209. .plat_auto = sizeof(struct eth_pdata),
  5210. };
  5211. U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
  5212. #endif