mxs_gpio.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 GPIO control code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <asm/global_data.h>
  12. #include <linux/bitops.h>
  13. #include <linux/errno.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/iomux.h>
  16. #include <asm/arch/imx-regs.h>
  17. #if defined(CONFIG_MX23)
  18. #define PINCTRL_BANKS 3
  19. #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
  20. #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
  21. #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
  22. #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
  23. #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
  24. #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
  25. #elif defined(CONFIG_MX28)
  26. #define PINCTRL_BANKS 5
  27. #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
  28. #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
  29. #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
  30. #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
  31. #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
  32. #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
  33. #else
  34. #error "Please select CONFIG_MX23 or CONFIG_MX28"
  35. #endif
  36. #define GPIO_INT_FALL_EDGE 0x0
  37. #define GPIO_INT_LOW_LEV 0x1
  38. #define GPIO_INT_RISE_EDGE 0x2
  39. #define GPIO_INT_HIGH_LEV 0x3
  40. #define GPIO_INT_LEV_MASK (1 << 0)
  41. #define GPIO_INT_POL_MASK (1 << 1)
  42. void mxs_gpio_init(void)
  43. {
  44. int i;
  45. for (i = 0; i < PINCTRL_BANKS; i++) {
  46. writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
  47. writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
  48. /* Use SCT address here to clear the IRQSTAT bits */
  49. writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
  50. }
  51. }
  52. #if !CONFIG_IS_ENABLED(DM_GPIO)
  53. int gpio_get_value(unsigned gpio)
  54. {
  55. uint32_t bank = PAD_BANK(gpio);
  56. uint32_t offset = PINCTRL_DIN(bank);
  57. struct mxs_register_32 *reg =
  58. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  59. return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
  60. }
  61. void gpio_set_value(unsigned gpio, int value)
  62. {
  63. uint32_t bank = PAD_BANK(gpio);
  64. uint32_t offset = PINCTRL_DOUT(bank);
  65. struct mxs_register_32 *reg =
  66. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  67. if (value)
  68. writel(1 << PAD_PIN(gpio), &reg->reg_set);
  69. else
  70. writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  71. }
  72. int gpio_direction_input(unsigned gpio)
  73. {
  74. uint32_t bank = PAD_BANK(gpio);
  75. uint32_t offset = PINCTRL_DOE(bank);
  76. struct mxs_register_32 *reg =
  77. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  78. writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  79. return 0;
  80. }
  81. int gpio_direction_output(unsigned gpio, int value)
  82. {
  83. uint32_t bank = PAD_BANK(gpio);
  84. uint32_t offset = PINCTRL_DOE(bank);
  85. struct mxs_register_32 *reg =
  86. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  87. gpio_set_value(gpio, value);
  88. writel(1 << PAD_PIN(gpio), &reg->reg_set);
  89. return 0;
  90. }
  91. int gpio_request(unsigned gpio, const char *label)
  92. {
  93. if (PAD_BANK(gpio) >= PINCTRL_BANKS)
  94. return -1;
  95. return 0;
  96. }
  97. int gpio_free(unsigned gpio)
  98. {
  99. return 0;
  100. }
  101. int name_to_gpio(const char *name)
  102. {
  103. unsigned bank, pin;
  104. char *end;
  105. bank = dectoul(name, &end);
  106. if (!*end || *end != ':')
  107. return bank;
  108. pin = dectoul(end + 1, NULL);
  109. return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
  110. }
  111. #else /* DM_GPIO */
  112. #include <dm.h>
  113. #include <asm/gpio.h>
  114. #include <dt-structs.h>
  115. #include <asm/arch/gpio.h>
  116. #define MXS_MAX_GPIO_PER_BANK 32
  117. DECLARE_GLOBAL_DATA_PTR;
  118. /*
  119. * According to i.MX28 Reference Manual:
  120. * 'i.MX28 Applications Processor Reference Manual, Rev. 1, 2010'
  121. * The i.MX28 has following number of GPIOs available:
  122. * Bank 0: 0-28 -> 29 PINS
  123. * Bank 1: 0-31 -> 32 PINS
  124. * Bank 2: 0-27 -> 28 PINS
  125. * Bank 3: 0-30 -> 31 PINS
  126. * Bank 4: 0-20 -> 21 PINS
  127. */
  128. struct mxs_gpio_plat {
  129. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  130. struct dtd_fsl_imx23_gpio dtplat;
  131. #endif
  132. unsigned int bank;
  133. int gpio_ranges;
  134. };
  135. struct mxs_gpio_priv {
  136. unsigned int bank;
  137. };
  138. static int mxs_gpio_get_value(struct udevice *dev, unsigned offset)
  139. {
  140. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  141. struct mxs_register_32 *reg =
  142. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  143. PINCTRL_DIN(priv->bank));
  144. return (readl(&reg->reg) >> offset) & 1;
  145. }
  146. static int mxs_gpio_set_value(struct udevice *dev, unsigned offset,
  147. int value)
  148. {
  149. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  150. struct mxs_register_32 *reg =
  151. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  152. PINCTRL_DOUT(priv->bank));
  153. if (value)
  154. writel(BIT(offset), &reg->reg_set);
  155. else
  156. writel(BIT(offset), &reg->reg_clr);
  157. return 0;
  158. }
  159. static int mxs_gpio_direction_input(struct udevice *dev, unsigned offset)
  160. {
  161. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  162. struct mxs_register_32 *reg =
  163. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  164. PINCTRL_DOE(priv->bank));
  165. writel(BIT(offset), &reg->reg_clr);
  166. return 0;
  167. }
  168. static int mxs_gpio_direction_output(struct udevice *dev, unsigned offset,
  169. int value)
  170. {
  171. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  172. struct mxs_register_32 *reg =
  173. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  174. PINCTRL_DOE(priv->bank));
  175. mxs_gpio_set_value(dev, offset, value);
  176. writel(BIT(offset), &reg->reg_set);
  177. return 0;
  178. }
  179. static int mxs_gpio_get_function(struct udevice *dev, unsigned offset)
  180. {
  181. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  182. struct mxs_register_32 *reg =
  183. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  184. PINCTRL_DOE(priv->bank));
  185. bool is_output = !!(readl(&reg->reg) >> offset);
  186. return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
  187. }
  188. static const struct dm_gpio_ops gpio_mxs_ops = {
  189. .direction_input = mxs_gpio_direction_input,
  190. .direction_output = mxs_gpio_direction_output,
  191. .get_value = mxs_gpio_get_value,
  192. .set_value = mxs_gpio_set_value,
  193. .get_function = mxs_gpio_get_function,
  194. };
  195. static int mxs_gpio_probe(struct udevice *dev)
  196. {
  197. struct mxs_gpio_plat *plat = dev_get_plat(dev);
  198. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  199. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  200. char name[16], *str;
  201. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  202. struct dtd_fsl_imx23_gpio *dtplat = &plat->dtplat;
  203. priv->bank = (unsigned int)dtplat->reg[0];
  204. uc_priv->gpio_count = dtplat->gpio_ranges[3];
  205. #else
  206. priv->bank = (unsigned int)plat->bank;
  207. uc_priv->gpio_count = plat->gpio_ranges;
  208. #endif
  209. snprintf(name, sizeof(name), "GPIO%d_", priv->bank);
  210. str = strdup(name);
  211. if (!str)
  212. return -ENOMEM;
  213. uc_priv->bank_name = str;
  214. debug("%s: %s: %d pins base: 0x%x\n", __func__, uc_priv->bank_name,
  215. uc_priv->gpio_count, priv->bank);
  216. return 0;
  217. }
  218. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  219. static int mxs_of_to_plat(struct udevice *dev)
  220. {
  221. struct mxs_gpio_plat *plat = dev_get_plat(dev);
  222. struct fdtdec_phandle_args args;
  223. int node = dev_of_offset(dev);
  224. int ret;
  225. plat->bank = dev_read_addr(dev);
  226. if (plat->bank == FDT_ADDR_T_NONE) {
  227. printf("%s: No 'reg' property defined!\n", __func__);
  228. return -EINVAL;
  229. }
  230. ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
  231. NULL, 3, 0, &args);
  232. if (ret)
  233. printf("%s: 'gpio-ranges' not defined - using default!\n",
  234. __func__);
  235. plat->gpio_ranges = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK;
  236. return 0;
  237. }
  238. static const struct udevice_id mxs_gpio_ids[] = {
  239. { .compatible = "fsl,imx23-gpio" },
  240. { .compatible = "fsl,imx28-gpio" },
  241. { }
  242. };
  243. #endif
  244. U_BOOT_DRIVER(fsl_imx23_gpio) = {
  245. .name = "fsl_imx23_gpio",
  246. .id = UCLASS_GPIO,
  247. .ops = &gpio_mxs_ops,
  248. .probe = mxs_gpio_probe,
  249. .priv_auto = sizeof(struct mxs_gpio_priv),
  250. .plat_auto = sizeof(struct mxs_gpio_plat),
  251. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  252. .of_match = mxs_gpio_ids,
  253. .of_to_plat = mxs_of_to_plat,
  254. #endif
  255. };
  256. DM_DRIVER_ALIAS(fsl_imx23_gpio, fsl_imx28_gpio)
  257. #endif /* DM_GPIO */