odroid.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Samsung Electronics
  4. * Przemyslaw Marczak <p.marczak@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/arch/pinmux.h>
  9. #include <asm/arch/power.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/global_data.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/cpu.h>
  15. #include <dm.h>
  16. #include <env.h>
  17. #include <power/pmic.h>
  18. #include <power/regulator.h>
  19. #include <power/max77686_pmic.h>
  20. #include <errno.h>
  21. #include <mmc.h>
  22. #include <usb.h>
  23. #include <usb/dwc2_udc.h>
  24. #include <samsung/misc.h>
  25. #include "setup.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #ifdef CONFIG_BOARD_TYPES
  28. /* Odroid board types */
  29. enum {
  30. ODROID_TYPE_U3,
  31. ODROID_TYPE_X2,
  32. ODROID_TYPES,
  33. };
  34. void set_board_type(void)
  35. {
  36. /* Set GPA1 pin 1 to HI - enable XCL205 output */
  37. writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
  38. writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
  39. writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
  40. writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
  41. /* Set GPC1 pin 2 to IN - check XCL205 output state */
  42. writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
  43. writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
  44. /* XCL205 - needs some latch time */
  45. sdelay(200000);
  46. /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
  47. if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
  48. gd->board_type = ODROID_TYPE_X2;
  49. else
  50. gd->board_type = ODROID_TYPE_U3;
  51. }
  52. void set_board_revision(void)
  53. {
  54. /*
  55. * Revision already set by set_board_type() because it can be
  56. * executed early.
  57. */
  58. }
  59. const char *get_board_type(void)
  60. {
  61. const char *board_type[] = {"u3", "x2"};
  62. return board_type[gd->board_type];
  63. }
  64. #endif
  65. #ifdef CONFIG_SET_DFU_ALT_INFO
  66. char *get_dfu_alt_system(char *interface, char *devstr)
  67. {
  68. return env_get("dfu_alt_system");
  69. }
  70. char *get_dfu_alt_boot(char *interface, char *devstr)
  71. {
  72. struct mmc *mmc;
  73. char *alt_boot;
  74. int dev_num;
  75. dev_num = dectoul(devstr, NULL);
  76. mmc = find_mmc_device(dev_num);
  77. if (!mmc)
  78. return NULL;
  79. if (mmc_init(mmc))
  80. return NULL;
  81. alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
  82. CONFIG_DFU_ALT_BOOT_EMMC;
  83. return alt_boot;
  84. }
  85. #endif
  86. static void board_clock_init(void)
  87. {
  88. unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
  89. struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
  90. samsung_get_base_clock();
  91. /*
  92. * CMU_CPU clocks src to MPLL
  93. * Bit values: 0 ; 1
  94. * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
  95. * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
  96. * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
  97. * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
  98. */
  99. clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
  100. MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
  101. set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
  102. MUX_MPLL_USER_SEL_C(1);
  103. clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
  104. /* Wait for mux change */
  105. while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
  106. continue;
  107. /* Set APLL to 1000MHz */
  108. clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
  109. set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
  110. clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
  111. /* Wait for PLL to be locked */
  112. while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
  113. continue;
  114. /* Set CMU_CPU clocks src to APLL */
  115. set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
  116. MUX_MPLL_USER_SEL_C(1);
  117. clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
  118. /* Wait for mux change */
  119. while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
  120. continue;
  121. set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
  122. PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
  123. APLL_RATIO(0) | CORE2_RATIO(0);
  124. /*
  125. * Set dividers for MOUTcore = 1000 MHz
  126. * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
  127. * corem0 = armclk / (ratio + 1) = 333 MHz (2)
  128. * corem1 = armclk / (ratio + 1) = 166 MHz (5)
  129. * periph = armclk / (ratio + 1) = 1000 MHz (0)
  130. * atbout = MOUT / (ratio + 1) = 200 MHz (4)
  131. * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
  132. * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
  133. * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
  134. */
  135. clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
  136. PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
  137. APLL_RATIO(7) | CORE2_RATIO(7);
  138. clrsetbits_le32(&clk->div_cpu0, clr, set);
  139. /* Wait for divider ready status */
  140. while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
  141. continue;
  142. /*
  143. * For MOUThpm = 1000 MHz (MOUTapll)
  144. * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
  145. * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
  146. * cores_out = armclk / (ratio + 1) = 200 (4)
  147. */
  148. clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
  149. set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
  150. clrsetbits_le32(&clk->div_cpu1, clr, set);
  151. /* Wait for divider ready status */
  152. while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
  153. continue;
  154. /*
  155. * Set CMU_DMC clocks src to APLL
  156. * Bit values: 0 ; 1
  157. * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
  158. * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
  159. * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
  160. * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
  161. * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
  162. * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
  163. * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
  164. * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
  165. */
  166. clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
  167. MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
  168. MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
  169. MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  170. set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
  171. MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
  172. MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  173. clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
  174. /* Wait for mux change */
  175. while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
  176. continue;
  177. /* Set MPLL to 800MHz */
  178. set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
  179. clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
  180. /* Wait for PLL to be locked */
  181. while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
  182. continue;
  183. /* Switch back CMU_DMC mux */
  184. set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
  185. MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
  186. MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
  187. clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
  188. /* Wait for mux change */
  189. while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
  190. continue;
  191. /* CLK_DIV_DMC0 */
  192. clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
  193. DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
  194. /*
  195. * For:
  196. * MOUTdmc = 800 MHz
  197. * MOUTdphy = 800 MHz
  198. *
  199. * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
  200. * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
  201. * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
  202. * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
  203. * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
  204. * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
  205. */
  206. set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
  207. DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
  208. clrsetbits_le32(&clk->div_dmc0, clr, set);
  209. /* Wait for divider ready status */
  210. while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
  211. continue;
  212. /* CLK_DIV_DMC1 */
  213. clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
  214. C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
  215. /*
  216. * For:
  217. * MOUTg2d = 800 MHz
  218. * MOUTc2c = 800 Mhz
  219. * MOUTpwi = 108 MHz
  220. *
  221. * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
  222. * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
  223. * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
  224. * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
  225. */
  226. set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
  227. C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
  228. clrsetbits_le32(&clk->div_dmc1, clr, set);
  229. /* Wait for divider ready status */
  230. while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
  231. continue;
  232. /* CLK_SRC_PERIL0 */
  233. clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
  234. UART3_SEL(15) | UART4_SEL(15);
  235. /*
  236. * Set CLK_SRC_PERIL0 clocks src to MPLL
  237. * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
  238. * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
  239. * 8(SCLK_VPLL)
  240. *
  241. * Set all to SCLK_MPLL_USER_T
  242. */
  243. set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
  244. UART4_SEL(6);
  245. clrsetbits_le32(&clk->src_peril0, clr, set);
  246. /* CLK_DIV_PERIL0 */
  247. clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
  248. UART3_RATIO(15) | UART4_RATIO(15);
  249. /*
  250. * For MOUTuart0-4: 800MHz
  251. *
  252. * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
  253. */
  254. set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
  255. UART3_RATIO(7) | UART4_RATIO(7);
  256. clrsetbits_le32(&clk->div_peril0, clr, set);
  257. while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
  258. continue;
  259. /* CLK_DIV_FSYS1 */
  260. clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
  261. MMC1_PRE_RATIO(255);
  262. /*
  263. * For MOUTmmc0-3 = 800 MHz (MPLL)
  264. *
  265. * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
  266. * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
  267. * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
  268. * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
  269. */
  270. set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
  271. MMC1_PRE_RATIO(1);
  272. clrsetbits_le32(&clk->div_fsys1, clr, set);
  273. /* Wait for divider ready status */
  274. while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
  275. continue;
  276. /* CLK_DIV_FSYS2 */
  277. clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
  278. MMC3_PRE_RATIO(255);
  279. /*
  280. * For MOUTmmc0-3 = 800 MHz (MPLL)
  281. *
  282. * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
  283. * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
  284. * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
  285. * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
  286. */
  287. set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
  288. MMC3_PRE_RATIO(1);
  289. clrsetbits_le32(&clk->div_fsys2, clr, set);
  290. /* Wait for divider ready status */
  291. while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
  292. continue;
  293. /* CLK_DIV_FSYS3 */
  294. clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
  295. /*
  296. * For MOUTmmc4 = 800 MHz (MPLL)
  297. *
  298. * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
  299. * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
  300. */
  301. set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
  302. clrsetbits_le32(&clk->div_fsys3, clr, set);
  303. /* Wait for divider ready status */
  304. while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
  305. continue;
  306. return;
  307. }
  308. static void board_gpio_init(void)
  309. {
  310. /* eMMC Reset Pin */
  311. gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
  312. gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
  313. gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
  314. gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
  315. /* Enable FAN (Odroid U3) */
  316. gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
  317. gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
  318. gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
  319. gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
  320. /* OTG Vbus output (Odroid U3+) */
  321. gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
  322. gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
  323. gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
  324. gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
  325. /* OTG INT (Odroid U3+) */
  326. gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
  327. gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
  328. gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
  329. gpio_direction_input(EXYNOS4X12_GPIO_X31);
  330. /* Blue LED (Odroid X2/U2/U3) */
  331. gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
  332. gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
  333. #ifdef CONFIG_CMD_USB
  334. /* USB3503A Reference frequency */
  335. gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
  336. /* USB3503A Connect */
  337. gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
  338. /* USB3503A Reset */
  339. gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
  340. #endif
  341. }
  342. int exynos_early_init_f(void)
  343. {
  344. board_clock_init();
  345. return 0;
  346. }
  347. int exynos_init(void)
  348. {
  349. board_gpio_init();
  350. return 0;
  351. }
  352. int exynos_power_init(void)
  353. {
  354. const char *mmc_regulators[] = {
  355. "VDDQ_EMMC_1.8V",
  356. "VDDQ_EMMC_2.8V",
  357. "TFLASH_2.8V",
  358. NULL,
  359. };
  360. if (regulator_list_autoset(mmc_regulators, NULL, true))
  361. pr_err("Unable to init all mmc regulators\n");
  362. return 0;
  363. }
  364. #ifdef CONFIG_USB_GADGET
  365. static int s5pc210_phy_control(int on)
  366. {
  367. struct udevice *dev;
  368. int ret;
  369. ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev);
  370. if (ret) {
  371. pr_err("Regulator get error: %d\n", ret);
  372. return ret;
  373. }
  374. if (on)
  375. return regulator_set_mode(dev, OPMODE_ON);
  376. else
  377. return regulator_set_mode(dev, OPMODE_LPM);
  378. }
  379. struct dwc2_plat_otg_data s5pc210_otg_data = {
  380. .phy_control = s5pc210_phy_control,
  381. .regs_phy = EXYNOS4X12_USBPHY_BASE,
  382. .regs_otg = EXYNOS4X12_USBOTG_BASE,
  383. .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
  384. .usb_flags = PHY0_SLEEP,
  385. };
  386. #endif
  387. #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
  388. static void set_usb3503_ref_clk(void)
  389. {
  390. #ifdef CONFIG_BOARD_TYPES
  391. /*
  392. * gpx3-0 chooses primary (low) or secondary (high) reference clock
  393. * frequencies table. The choice of clock is done through hard-wired
  394. * REF_SEL pins.
  395. * The Odroid Us have reference clock at 24 MHz (00 entry from secondary
  396. * table) and Odroid Xs have it at 26 MHz (01 entry from primary table).
  397. */
  398. if (gd->board_type == ODROID_TYPE_U3)
  399. gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
  400. else
  401. gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
  402. #else
  403. /* Choose Odroid Xs frequency without board types */
  404. gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
  405. #endif /* CONFIG_BOARD_TYPES */
  406. }
  407. int board_usb_init(int index, enum usb_init_type init)
  408. {
  409. #ifdef CONFIG_CMD_USB
  410. struct udevice *dev;
  411. int ret;
  412. set_usb3503_ref_clk();
  413. /* Disconnect, Reset, Connect */
  414. gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
  415. gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
  416. gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
  417. gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
  418. /* Power off and on BUCK8 for LAN9730 */
  419. debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
  420. ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev);
  421. if (ret) {
  422. pr_err("Regulator get error: %d\n", ret);
  423. return ret;
  424. }
  425. ret = regulator_set_enable(dev, true);
  426. if (ret) {
  427. pr_err("Regulator %s enable setting error: %d\n", dev->name, ret);
  428. return ret;
  429. }
  430. ret = regulator_set_value(dev, 750000);
  431. if (ret) {
  432. pr_err("Regulator %s value setting error: %d\n", dev->name, ret);
  433. return ret;
  434. }
  435. ret = regulator_set_value(dev, 3300000);
  436. if (ret) {
  437. pr_err("Regulator %s value setting error: %d\n", dev->name, ret);
  438. return ret;
  439. }
  440. #endif
  441. debug("USB_udc_probe\n");
  442. return dwc2_udc_probe(&s5pc210_otg_data);
  443. }
  444. #endif