gw_ventana.c 31 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Gateworks Corporation
  4. *
  5. * Author: Tim Harvey <tharvey@gateworks.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/mxc_hdmi.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/global_data.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/video.h>
  17. #include <asm/setup.h>
  18. #include <env.h>
  19. #include <hwconfig.h>
  20. #include <linux/ctype.h>
  21. #include <miiphy.h>
  22. #include <mtd_node.h>
  23. #include <linux/delay.h>
  24. #include <power/pmic.h>
  25. #include <fdt_support.h>
  26. #include <jffs2/load_kernel.h>
  27. #include "gsc.h"
  28. #include "common.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. /*
  31. * EEPROM board info struct populated by read_eeprom so that we only have to
  32. * read it once.
  33. */
  34. struct ventana_board_info ventana_info;
  35. static int board_type;
  36. #ifdef CONFIG_USB_EHCI_MX6
  37. /* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
  38. int board_ehci_hcd_init(int port)
  39. {
  40. int gpio;
  41. /* USB HUB is always on P1 */
  42. if (port == 0)
  43. return 0;
  44. /* Reset USB HUB */
  45. switch (board_type) {
  46. case GW53xx:
  47. case GW552x:
  48. case GW5906:
  49. gpio = (IMX_GPIO_NR(1, 9));
  50. break;
  51. case GW54proto:
  52. case GW54xx:
  53. gpio = (IMX_GPIO_NR(1, 16));
  54. break;
  55. default:
  56. return 0;
  57. }
  58. /* request and toggle hub rst */
  59. gpio_request(gpio, "usb_hub_rst#");
  60. gpio_direction_output(gpio, 0);
  61. mdelay(2);
  62. gpio_set_value(gpio, 1);
  63. return 0;
  64. }
  65. #endif /* CONFIG_USB_EHCI_MX6 */
  66. /* configure eth0 PHY board-specific LED behavior */
  67. int board_phy_config(struct phy_device *phydev)
  68. {
  69. unsigned short val;
  70. /* Marvel 88E1510 */
  71. if (phydev->phy_id == 0x1410dd1) {
  72. puts("MV88E1510");
  73. /*
  74. * Page 3, Register 16: LED[2:0] Function Control Register
  75. * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
  76. * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
  77. */
  78. phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
  79. val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
  80. val &= 0xff00;
  81. val |= 0x0017;
  82. phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
  83. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
  84. }
  85. /* TI DP83867 */
  86. else if (phydev->phy_id == 0x2000a231) {
  87. puts("TIDP83867 ");
  88. /* LED configuration */
  89. val = 0;
  90. val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
  91. val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
  92. phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
  93. /* configure register 0x170 for ref CLKOUT */
  94. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
  95. phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
  96. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
  97. val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
  98. val &= ~0x1f00;
  99. val |= 0x0b00; /* chD tx clock*/
  100. phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
  101. }
  102. if (phydev->drv->config)
  103. phydev->drv->config(phydev);
  104. return 0;
  105. }
  106. #ifdef CONFIG_MV88E61XX_SWITCH
  107. int mv88e61xx_hw_reset(struct phy_device *phydev)
  108. {
  109. struct mii_dev *bus = phydev->bus;
  110. /* GPIO[0] output, CLK125 */
  111. debug("enabling RGMII_REFCLK\n");
  112. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  113. 0x1a /*MV_SCRATCH_MISC*/,
  114. (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
  115. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  116. 0x1a /*MV_SCRATCH_MISC*/,
  117. (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
  118. /* RGMII delay - Physical Control register bit[15:14] */
  119. debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
  120. /* forced 1000mbps full-duplex link */
  121. bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
  122. phydev->autoneg = AUTONEG_DISABLE;
  123. phydev->speed = SPEED_1000;
  124. phydev->duplex = DUPLEX_FULL;
  125. /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
  126. bus->write(bus, 0x10, 0, 0x16, 0x8088);
  127. bus->write(bus, 0x11, 0, 0x16, 0x8088);
  128. bus->write(bus, 0x12, 0, 0x16, 0x8088);
  129. bus->write(bus, 0x13, 0, 0x16, 0x8088);
  130. return 0;
  131. }
  132. #endif // CONFIG_MV88E61XX_SWITCH
  133. #if defined(CONFIG_VIDEO_IPUV3)
  134. static void enable_hdmi(struct display_info_t const *dev)
  135. {
  136. imx_enable_hdmi_phy();
  137. }
  138. static int detect_i2c(struct display_info_t const *dev)
  139. {
  140. return i2c_set_bus_num(dev->bus) == 0 &&
  141. i2c_probe(dev->addr) == 0;
  142. }
  143. static void enable_lvds(struct display_info_t const *dev)
  144. {
  145. struct iomuxc *iomux = (struct iomuxc *)
  146. IOMUXC_BASE_ADDR;
  147. /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
  148. u32 reg = readl(&iomux->gpr[2]);
  149. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  150. writel(reg, &iomux->gpr[2]);
  151. /* Enable Backlight */
  152. gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
  153. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  154. gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
  155. SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
  156. gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
  157. }
  158. struct display_info_t const displays[] = {{
  159. /* HDMI Output */
  160. .bus = -1,
  161. .addr = 0,
  162. .pixfmt = IPU_PIX_FMT_RGB24,
  163. .detect = detect_hdmi,
  164. .enable = enable_hdmi,
  165. .mode = {
  166. .name = "HDMI",
  167. .refresh = 60,
  168. .xres = 1024,
  169. .yres = 768,
  170. .pixclock = 15385,
  171. .left_margin = 220,
  172. .right_margin = 40,
  173. .upper_margin = 21,
  174. .lower_margin = 7,
  175. .hsync_len = 60,
  176. .vsync_len = 10,
  177. .sync = FB_SYNC_EXT,
  178. .vmode = FB_VMODE_NONINTERLACED
  179. } }, {
  180. /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
  181. .bus = 2,
  182. .addr = 0x4,
  183. .pixfmt = IPU_PIX_FMT_LVDS666,
  184. .detect = detect_i2c,
  185. .enable = enable_lvds,
  186. .mode = {
  187. .name = "Hannstar-XGA",
  188. .refresh = 60,
  189. .xres = 1024,
  190. .yres = 768,
  191. .pixclock = 15385,
  192. .left_margin = 220,
  193. .right_margin = 40,
  194. .upper_margin = 21,
  195. .lower_margin = 7,
  196. .hsync_len = 60,
  197. .vsync_len = 10,
  198. .sync = FB_SYNC_EXT,
  199. .vmode = FB_VMODE_NONINTERLACED
  200. } }, {
  201. /* DLC700JMG-T-4 */
  202. .bus = 2,
  203. .addr = 0x38,
  204. .detect = NULL,
  205. .enable = enable_lvds,
  206. .pixfmt = IPU_PIX_FMT_LVDS666,
  207. .mode = {
  208. .name = "DLC700JMGT4",
  209. .refresh = 60,
  210. .xres = 1024, /* 1024x600active pixels */
  211. .yres = 600,
  212. .pixclock = 15385, /* 64MHz */
  213. .left_margin = 220,
  214. .right_margin = 40,
  215. .upper_margin = 21,
  216. .lower_margin = 7,
  217. .hsync_len = 60,
  218. .vsync_len = 10,
  219. .sync = FB_SYNC_EXT,
  220. .vmode = FB_VMODE_NONINTERLACED
  221. } }, {
  222. /* DLC0700XDP21LF-C-1 */
  223. .bus = 0,
  224. .addr = 0,
  225. .detect = NULL,
  226. .enable = enable_lvds,
  227. .pixfmt = IPU_PIX_FMT_LVDS666,
  228. .mode = {
  229. .name = "DLC0700XDP21LF",
  230. .refresh = 60,
  231. .xres = 1024, /* 1024x600active pixels */
  232. .yres = 600,
  233. .pixclock = 15385, /* 64MHz */
  234. .left_margin = 220,
  235. .right_margin = 40,
  236. .upper_margin = 21,
  237. .lower_margin = 7,
  238. .hsync_len = 60,
  239. .vsync_len = 10,
  240. .sync = FB_SYNC_EXT,
  241. .vmode = FB_VMODE_NONINTERLACED
  242. } }, {
  243. /* DLC800FIG-T-3 */
  244. .bus = 2,
  245. .addr = 0x14,
  246. .detect = NULL,
  247. .enable = enable_lvds,
  248. .pixfmt = IPU_PIX_FMT_LVDS666,
  249. .mode = {
  250. .name = "DLC800FIGT3",
  251. .refresh = 60,
  252. .xres = 1024, /* 1024x768 active pixels */
  253. .yres = 768,
  254. .pixclock = 15385, /* 64MHz */
  255. .left_margin = 220,
  256. .right_margin = 40,
  257. .upper_margin = 21,
  258. .lower_margin = 7,
  259. .hsync_len = 60,
  260. .vsync_len = 10,
  261. .sync = FB_SYNC_EXT,
  262. .vmode = FB_VMODE_NONINTERLACED
  263. } }, {
  264. .bus = 2,
  265. .addr = 0x5d,
  266. .detect = detect_i2c,
  267. .enable = enable_lvds,
  268. .pixfmt = IPU_PIX_FMT_LVDS666,
  269. .mode = {
  270. .name = "Z101WX01",
  271. .refresh = 60,
  272. .xres = 1280,
  273. .yres = 800,
  274. .pixclock = 15385, /* 64MHz */
  275. .left_margin = 220,
  276. .right_margin = 40,
  277. .upper_margin = 21,
  278. .lower_margin = 7,
  279. .hsync_len = 60,
  280. .vsync_len = 10,
  281. .sync = FB_SYNC_EXT,
  282. .vmode = FB_VMODE_NONINTERLACED
  283. }
  284. },
  285. };
  286. size_t display_count = ARRAY_SIZE(displays);
  287. static void setup_display(void)
  288. {
  289. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  290. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  291. int reg;
  292. enable_ipu_clock();
  293. imx_setup_hdmi();
  294. /* Turn on LDB0,IPU,IPU DI0 clocks */
  295. reg = __raw_readl(&mxc_ccm->CCGR3);
  296. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  297. writel(reg, &mxc_ccm->CCGR3);
  298. /* set LDB0, LDB1 clk select to 011/011 */
  299. reg = readl(&mxc_ccm->cs2cdr);
  300. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  301. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  302. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  303. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  304. writel(reg, &mxc_ccm->cs2cdr);
  305. reg = readl(&mxc_ccm->cscmr2);
  306. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  307. writel(reg, &mxc_ccm->cscmr2);
  308. reg = readl(&mxc_ccm->chsccdr);
  309. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  310. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  311. writel(reg, &mxc_ccm->chsccdr);
  312. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  313. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  314. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  315. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  316. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  317. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  318. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  319. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  320. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  321. writel(reg, &iomux->gpr[2]);
  322. reg = readl(&iomux->gpr[3]);
  323. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  324. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  325. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  326. writel(reg, &iomux->gpr[3]);
  327. /* LVDS Backlight GPIO on LVDS connector - output low */
  328. SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
  329. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  330. }
  331. #endif /* CONFIG_VIDEO_IPUV3 */
  332. /* setup board specific PMIC */
  333. int power_init_board(void)
  334. {
  335. setup_pmic();
  336. return 0;
  337. }
  338. int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
  339. {
  340. if (board_type < GW_UNKNOWN) {
  341. uint pin = gpio_cfg[board_type].pcie_rst;
  342. gpio_request(pin, "pci_rst#");
  343. gpio_direction_output(pin, 0);
  344. mdelay(50);
  345. gpio_direction_output(pin, 1);
  346. }
  347. return 0;
  348. }
  349. /*
  350. * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
  351. * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
  352. * properly and assert reset for 100ms.
  353. */
  354. #define MAX_PCI_DEVS 32
  355. struct pci_dev {
  356. pci_dev_t devfn;
  357. struct udevice *dev;
  358. unsigned short vendor;
  359. unsigned short device;
  360. unsigned short class;
  361. unsigned short busno; /* subbordinate busno */
  362. struct pci_dev *ppar;
  363. };
  364. struct pci_dev pci_devs[MAX_PCI_DEVS];
  365. int pci_devno;
  366. int pci_bridgeno;
  367. void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
  368. {
  369. struct pci_child_plat *pdata = dev_get_parent_plat(udev);
  370. struct pci_dev *pdev = &pci_devs[pci_devno++];
  371. unsigned short vendor = pdata->vendor;
  372. unsigned short device = pdata->device;
  373. unsigned int class = pdata->class;
  374. pci_dev_t dev = dm_pci_get_bdf(udev);
  375. int i;
  376. debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
  377. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
  378. /* store array of devs for later use in device-tree fixup */
  379. pdev->dev = udev;
  380. pdev->devfn = dev;
  381. pdev->vendor = vendor;
  382. pdev->device = device;
  383. pdev->class = class;
  384. pdev->ppar = NULL;
  385. if (class == PCI_CLASS_BRIDGE_PCI)
  386. pdev->busno = ++pci_bridgeno;
  387. else
  388. pdev->busno = 0;
  389. /* fixup RC - it should be 00:00.0 not 00:01.0 */
  390. if (PCI_BUS(dev) == 0)
  391. pdev->devfn = 0;
  392. /* find dev's parent */
  393. for (i = 0; i < pci_devno; i++) {
  394. if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
  395. pdev->ppar = &pci_devs[i];
  396. break;
  397. }
  398. }
  399. /* assert downstream PERST# */
  400. if (vendor == PCI_VENDOR_ID_PLX &&
  401. (device & 0xfff0) == 0x8600 &&
  402. PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
  403. ulong val;
  404. debug("configuring PLX 860X downstream PERST#\n");
  405. pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
  406. val |= 0xaaa8; /* GPIO1-7 outputs */
  407. pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
  408. pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
  409. val |= 0xfe; /* GPIO1-7 output high */
  410. pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
  411. mdelay(100);
  412. }
  413. }
  414. #ifdef CONFIG_SERIAL_TAG
  415. /*
  416. * called when setting up ATAGS before booting kernel
  417. * populate serialnum from the following (in order of priority):
  418. * serial# env var
  419. * eeprom
  420. */
  421. void get_board_serial(struct tag_serialnr *serialnr)
  422. {
  423. char *serial = env_get("serial#");
  424. if (serial) {
  425. serialnr->high = 0;
  426. serialnr->low = dectoul(serial, NULL);
  427. } else if (ventana_info.model[0]) {
  428. serialnr->high = 0;
  429. serialnr->low = ventana_info.serial;
  430. } else {
  431. serialnr->high = 0;
  432. serialnr->low = 0;
  433. }
  434. }
  435. #endif
  436. /*
  437. * Board Support
  438. */
  439. int board_early_init_f(void)
  440. {
  441. #if defined(CONFIG_VIDEO_IPUV3)
  442. setup_display();
  443. #endif
  444. return 0;
  445. }
  446. int dram_init(void)
  447. {
  448. gd->ram_size = imx_ddr_size();
  449. return 0;
  450. }
  451. int board_init(void)
  452. {
  453. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  454. clrsetbits_le32(&iomuxc_regs->gpr[1],
  455. IOMUXC_GPR1_OTG_ID_MASK,
  456. IOMUXC_GPR1_OTG_ID_GPIO1);
  457. /* address of linux boot parameters */
  458. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  459. /* read Gateworks EEPROM into global struct (used later) */
  460. setup_ventana_i2c(0);
  461. board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  462. setup_ventana_i2c(1);
  463. setup_ventana_i2c(2);
  464. setup_iomux_gpio(board_type, &ventana_info);
  465. return 0;
  466. }
  467. int board_fit_config_name_match(const char *name)
  468. {
  469. static char init;
  470. const char *dtb;
  471. char buf[32];
  472. int i = 0;
  473. do {
  474. dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
  475. if (dtb && !strcmp(dtb, name)) {
  476. if (!init++)
  477. printf("DTB: %s\n", name);
  478. return 0;
  479. }
  480. } while (dtb);
  481. return -1;
  482. }
  483. #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
  484. /*
  485. * called during late init (after relocation and after board_init())
  486. * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
  487. * EEPROM read.
  488. */
  489. int checkboard(void)
  490. {
  491. struct ventana_board_info *info = &ventana_info;
  492. unsigned char buf[4];
  493. const char *p;
  494. int quiet; /* Quiet or minimal output mode */
  495. quiet = 0;
  496. p = env_get("quiet");
  497. if (p)
  498. quiet = simple_strtol(p, NULL, 10);
  499. else
  500. env_set("quiet", "0");
  501. puts("\nGateworks Corporation Copyright 2014\n");
  502. if (info->model[0]) {
  503. printf("Model: %s\n", info->model);
  504. printf("MFGDate: %02x-%02x-%02x%02x\n",
  505. info->mfgdate[0], info->mfgdate[1],
  506. info->mfgdate[2], info->mfgdate[3]);
  507. printf("Serial:%d\n", info->serial);
  508. } else {
  509. puts("Invalid EEPROM - board will not function fully\n");
  510. }
  511. if (quiet)
  512. return 0;
  513. /* Display GSC firmware revision/CRC/status */
  514. gsc_info(0);
  515. /* Display RTC */
  516. if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
  517. printf("RTC: %d\n",
  518. buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
  519. }
  520. return 0;
  521. }
  522. #endif
  523. #ifdef CONFIG_CMD_BMODE
  524. /*
  525. * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  526. * see Table 8-11 and Table 5-9
  527. * BOOT_CFG1[7] = 1 (boot from NAND)
  528. * BOOT_CFG1[5] = 0 - raw NAND
  529. * BOOT_CFG1[4] = 0 - default pad settings
  530. * BOOT_CFG1[3:2] = 00 - devices = 1
  531. * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  532. * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  533. * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  534. * BOOT_CFG2[0] = 0 - Reset time 12ms
  535. */
  536. static const struct boot_mode board_boot_modes[] = {
  537. /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  538. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  539. { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
  540. { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
  541. { NULL, 0 },
  542. };
  543. #endif
  544. /* late init */
  545. int misc_init_r(void)
  546. {
  547. struct ventana_board_info *info = &ventana_info;
  548. char buf[256];
  549. int i;
  550. /* set env vars based on EEPROM data */
  551. if (ventana_info.model[0]) {
  552. char str[16], fdt[36];
  553. char *p;
  554. const char *cputype = "";
  555. /*
  556. * FDT name will be prefixed with CPU type. Three versions
  557. * will be created each increasingly generic and bootloader
  558. * env scripts will try loading each from most specific to
  559. * least.
  560. */
  561. if (is_cpu_type(MXC_CPU_MX6Q) ||
  562. is_cpu_type(MXC_CPU_MX6D))
  563. cputype = "imx6q";
  564. else if (is_cpu_type(MXC_CPU_MX6DL) ||
  565. is_cpu_type(MXC_CPU_MX6SOLO))
  566. cputype = "imx6dl";
  567. env_set("soctype", cputype);
  568. if (8 << (ventana_info.nand_flash_size-1) >= 2048)
  569. env_set("flash_layout", "large");
  570. else
  571. env_set("flash_layout", "normal");
  572. memset(str, 0, sizeof(str));
  573. for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
  574. str[i] = tolower(info->model[i]);
  575. env_set("model", str);
  576. if (!env_get("fdt_file")) {
  577. sprintf(fdt, "%s-%s.dtb", cputype, str);
  578. env_set("fdt_file", fdt);
  579. }
  580. p = strchr(str, '-');
  581. if (p) {
  582. *p++ = 0;
  583. env_set("model_base", str);
  584. sprintf(fdt, "%s-%s.dtb", cputype, str);
  585. env_set("fdt_file1", fdt);
  586. if (board_type != GW551x &&
  587. board_type != GW552x &&
  588. board_type != GW553x &&
  589. board_type != GW560x)
  590. str[4] = 'x';
  591. str[5] = 'x';
  592. str[6] = 0;
  593. sprintf(fdt, "%s-%s.dtb", cputype, str);
  594. env_set("fdt_file2", fdt);
  595. }
  596. /* initialize env from EEPROM */
  597. if (test_bit(EECONFIG_ETH0, info->config) &&
  598. !env_get("ethaddr")) {
  599. eth_env_set_enetaddr("ethaddr", info->mac0);
  600. }
  601. if (test_bit(EECONFIG_ETH1, info->config) &&
  602. !env_get("eth1addr")) {
  603. eth_env_set_enetaddr("eth1addr", info->mac1);
  604. }
  605. /* board serial-number */
  606. sprintf(str, "%6d", info->serial);
  607. env_set("serial#", str);
  608. /* memory MB */
  609. sprintf(str, "%d", (int) (gd->ram_size >> 20));
  610. env_set("mem_mb", str);
  611. }
  612. /* Set a non-initialized hwconfig based on board configuration */
  613. if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
  614. buf[0] = 0;
  615. if (gpio_cfg[board_type].rs232_en)
  616. strcat(buf, "rs232;");
  617. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  618. char buf1[32];
  619. sprintf(buf1, "dio%d:mode=gpio;", i);
  620. if (strlen(buf) + strlen(buf1) < sizeof(buf))
  621. strcat(buf, buf1);
  622. }
  623. env_set("hwconfig", buf);
  624. }
  625. /* setup baseboard specific GPIO based on board and env */
  626. setup_board_gpio(board_type, info);
  627. #ifdef CONFIG_CMD_BMODE
  628. add_board_boot_modes(board_boot_modes);
  629. #endif
  630. /* disable boot watchdog */
  631. gsc_boot_wd_disable();
  632. return 0;
  633. }
  634. #ifdef CONFIG_OF_BOARD_SETUP
  635. static int ft_sethdmiinfmt(void *blob, char *mode)
  636. {
  637. int off;
  638. if (!mode)
  639. return -EINVAL;
  640. off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
  641. if (off < 0)
  642. return off;
  643. if (0 == strcasecmp(mode, "yuv422bt656")) {
  644. u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
  645. 0x00, 0x00, 0x00 };
  646. mode = "422_ccir";
  647. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  648. fdt_setprop_u32(blob, off, "vidout_trc", 1);
  649. fdt_setprop_u32(blob, off, "vidout_blc", 1);
  650. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  651. printf(" set HDMI input mode to %s\n", mode);
  652. } else if (0 == strcasecmp(mode, "yuv422smp")) {
  653. u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
  654. 0x82, 0x81, 0x00 };
  655. mode = "422_smp";
  656. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  657. fdt_setprop_u32(blob, off, "vidout_trc", 0);
  658. fdt_setprop_u32(blob, off, "vidout_blc", 0);
  659. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  660. printf(" set HDMI input mode to %s\n", mode);
  661. } else {
  662. return -EINVAL;
  663. }
  664. return 0;
  665. }
  666. #if defined(CONFIG_CMD_PCI)
  667. #define PCI_ID(x) ( \
  668. (PCI_BUS(x->devfn)<<16)| \
  669. (PCI_DEV(x->devfn)<<11)| \
  670. (PCI_FUNC(x->devfn)<<8) \
  671. )
  672. int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
  673. {
  674. uint32_t reg[5];
  675. char node[32];
  676. int np;
  677. sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
  678. PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
  679. np = fdt_subnode_offset(blob, par, node);
  680. if (np >= 0)
  681. return np;
  682. np = fdt_add_subnode(blob, par, node);
  683. if (np < 0) {
  684. printf(" %s failed: no space\n", __func__);
  685. return np;
  686. }
  687. memset(reg, 0, sizeof(reg));
  688. reg[0] = cpu_to_fdt32(PCI_ID(dev));
  689. fdt_setprop(blob, np, "reg", reg, sizeof(reg));
  690. return np;
  691. }
  692. /* build a path of nested PCI devs for all bridges passed through */
  693. int fdt_add_pci_path(void *blob, struct pci_dev *dev)
  694. {
  695. struct pci_dev *bridges[MAX_PCI_DEVS];
  696. int k, np;
  697. /* build list of parents */
  698. np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  699. if (np < 0)
  700. return np;
  701. k = 0;
  702. while (dev) {
  703. bridges[k++] = dev;
  704. dev = dev->ppar;
  705. };
  706. /* now add them the to DT in reverse order */
  707. while (k--) {
  708. np = fdt_add_pci_node(blob, np, bridges[k]);
  709. if (np < 0)
  710. break;
  711. }
  712. return np;
  713. }
  714. /*
  715. * The GW16082 has a hardware errata errata such that it's
  716. * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
  717. * of this normal PCI interrupt swizzling will not work so we will
  718. * provide an irq-map via device-tree.
  719. */
  720. int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
  721. {
  722. int len;
  723. int host;
  724. uint32_t imap_new[8*4*4];
  725. const uint32_t *imap;
  726. uint32_t irq[4];
  727. uint32_t reg[4];
  728. int i;
  729. /* build irq-map based on host controllers map */
  730. host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  731. if (host < 0) {
  732. printf(" %s failed: missing host\n", __func__);
  733. return host;
  734. }
  735. /* use interrupt data from root complex's node */
  736. imap = fdt_getprop(blob, host, "interrupt-map", &len);
  737. if (!imap || len != 128) {
  738. printf(" %s failed: invalid interrupt-map\n",
  739. __func__);
  740. return -FDT_ERR_NOTFOUND;
  741. }
  742. /* obtain irq's of host controller in pin order */
  743. for (i = 0; i < 4; i++)
  744. irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
  745. /*
  746. * determine number of swizzles necessary:
  747. * For each bridge we pass through we need to swizzle
  748. * the number of the slot we are on.
  749. */
  750. struct pci_dev *d;
  751. int b;
  752. b = 0;
  753. d = dev->ppar;
  754. while(d && d->ppar) {
  755. b += PCI_DEV(d->devfn);
  756. d = d->ppar;
  757. }
  758. /* create new irq mappings for slots12-15
  759. * <skt> <idsel> <slot> <skt-inta> <skt-intb>
  760. * J3 AD28 12 INTD INTA
  761. * J4 AD29 13 INTC INTD
  762. * J5 AD30 14 INTB INTC
  763. * J2 AD31 15 INTA INTB
  764. */
  765. for (i = 0; i < 4; i++) {
  766. /* addr matches bus:dev:func */
  767. u32 addr = dev->busno << 16 | (12+i) << 11;
  768. /* default cells from root complex */
  769. memcpy(&imap_new[i*32], imap, 128);
  770. /* first cell is PCI device address (BDF) */
  771. imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
  772. imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
  773. imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
  774. imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
  775. /* third cell is pin */
  776. imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
  777. imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
  778. imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
  779. imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
  780. /* sixth cell is relative interrupt */
  781. imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
  782. imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
  783. imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
  784. imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
  785. }
  786. fdt_setprop(blob, np, "interrupt-map", imap_new,
  787. sizeof(imap_new));
  788. reg[0] = cpu_to_fdt32(0xfff00);
  789. reg[1] = 0;
  790. reg[2] = 0;
  791. reg[3] = cpu_to_fdt32(0x7);
  792. fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
  793. fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
  794. fdt_setprop_string(blob, np, "device_type", "pci");
  795. fdt_setprop_cell(blob, np, "#address-cells", 3);
  796. fdt_setprop_cell(blob, np, "#size-cells", 2);
  797. printf(" Added custom interrupt-map for GW16082\n");
  798. return 0;
  799. }
  800. /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
  801. int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
  802. {
  803. char *tmp, *end;
  804. char mac[16];
  805. unsigned char mac_addr[6];
  806. int j;
  807. sprintf(mac, "eth1addr");
  808. tmp = env_get(mac);
  809. if (tmp) {
  810. for (j = 0; j < 6; j++) {
  811. mac_addr[j] = tmp ?
  812. hextoul(tmp, &end) : 0;
  813. if (tmp)
  814. tmp = (*end) ? end+1 : end;
  815. }
  816. fdt_setprop(blob, np, "local-mac-address", mac_addr,
  817. sizeof(mac_addr));
  818. printf(" Added mac addr for eth1\n");
  819. return 0;
  820. }
  821. return -1;
  822. }
  823. /*
  824. * PCI DT nodes must be nested therefore if we need to apply a DT fixup
  825. * we will walk the PCI bus and add bridge nodes up to the device receiving
  826. * the fixup.
  827. */
  828. void ft_board_pci_fixup(void *blob, struct bd_info *bd)
  829. {
  830. int i, np;
  831. struct pci_dev *dev;
  832. for (i = 0; i < pci_devno; i++) {
  833. dev = &pci_devs[i];
  834. /*
  835. * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
  836. * an EEPROM at i2c1-0x50.
  837. */
  838. if ((dev->vendor == PCI_VENDOR_ID_TI) &&
  839. (dev->device == 0x8240) &&
  840. (i2c_set_bus_num(1) == 0) &&
  841. (i2c_probe(0x50) == 0))
  842. {
  843. np = fdt_add_pci_path(blob, dev);
  844. if (np > 0)
  845. fdt_fixup_gw16082(blob, np, dev);
  846. }
  847. /* ethernet1 mac address */
  848. else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
  849. (dev->device == 0x4380))
  850. {
  851. np = fdt_add_pci_path(blob, dev);
  852. if (np > 0)
  853. fdt_fixup_sky2(blob, np, dev);
  854. }
  855. }
  856. }
  857. #endif /* if defined(CONFIG_CMD_PCI) */
  858. void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
  859. {
  860. int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
  861. if (off) {
  862. fdt_delprop(blob, off, "ext-reset-output");
  863. fdt_delprop(blob, off, "fsl,ext-reset-output");
  864. }
  865. }
  866. /*
  867. * called prior to booting kernel or by 'fdt boardsetup' command
  868. *
  869. * unless 'fdt_noauto' env var is set we will update the following in the DTB:
  870. * - mtd partitions based on mtdparts/mtdids env
  871. * - system-serial (board serial num from EEPROM)
  872. * - board (full model from EEPROM)
  873. * - peripherals removed from DTB if not loaded on board (per EEPROM config)
  874. */
  875. #define WDOG1_ADDR 0x20bc000
  876. #define WDOG2_ADDR 0x20c0000
  877. #define GPIO3_ADDR 0x20a4000
  878. #define USDHC3_ADDR 0x2198000
  879. #define PWM0_ADDR 0x2080000
  880. int ft_board_setup(void *blob, struct bd_info *bd)
  881. {
  882. struct ventana_board_info *info = &ventana_info;
  883. struct ventana_eeprom_config *cfg;
  884. static const struct node_info nodes[] = {
  885. { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
  886. { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  887. };
  888. const char *model = env_get("model");
  889. const char *display = env_get("display");
  890. int i;
  891. char rev = 0;
  892. /* determine board revision */
  893. for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
  894. if (ventana_info.model[i] >= 'A') {
  895. rev = ventana_info.model[i];
  896. break;
  897. }
  898. }
  899. if (env_get("fdt_noauto")) {
  900. puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
  901. return 0;
  902. }
  903. if (test_bit(EECONFIG_NAND, info->config)) {
  904. /* Update partition nodes using info from mtdparts env var */
  905. puts(" Updating MTD partitions...\n");
  906. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  907. }
  908. /* Update display timings from display env var */
  909. if (display) {
  910. if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
  911. display) >= 0)
  912. printf(" Set display timings for %s...\n", display);
  913. }
  914. printf(" Adjusting FDT per EEPROM for %s...\n", model);
  915. /* board serial number */
  916. fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
  917. strlen(env_get("serial#")) + 1);
  918. /* board (model contains model from device-tree) */
  919. fdt_setprop(blob, 0, "board", info->model,
  920. strlen((const char *)info->model) + 1);
  921. /* set desired digital video capture format */
  922. ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
  923. /*
  924. * Board model specific fixups
  925. */
  926. switch (board_type) {
  927. case GW51xx:
  928. /*
  929. * disable wdog node for GW51xx-A/B to work around
  930. * errata causing wdog timer to be unreliable.
  931. */
  932. if (rev >= 'A' && rev < 'C') {
  933. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
  934. WDOG1_ADDR);
  935. if (i)
  936. fdt_status_disabled(blob, i);
  937. }
  938. /* GW51xx-E adds WDOG1_B external reset */
  939. if (rev < 'E')
  940. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  941. break;
  942. case GW52xx:
  943. /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
  944. if (info->model[4] == '2') {
  945. u32 handle = 0;
  946. u32 *range = NULL;
  947. i = fdt_node_offset_by_compatible(blob, -1,
  948. "fsl,imx6q-pcie");
  949. if (i)
  950. range = (u32 *)fdt_getprop(blob, i,
  951. "reset-gpio", NULL);
  952. if (range) {
  953. i = fdt_node_offset_by_compat_reg(blob,
  954. "fsl,imx6q-gpio", GPIO3_ADDR);
  955. if (i)
  956. handle = fdt_get_phandle(blob, i);
  957. if (handle) {
  958. range[0] = cpu_to_fdt32(handle);
  959. range[1] = cpu_to_fdt32(23);
  960. }
  961. }
  962. /* these have broken usd_vsel */
  963. if (strstr((const char *)info->model, "SP318-B") ||
  964. strstr((const char *)info->model, "SP331-B"))
  965. gpio_cfg[board_type].usd_vsel = 0;
  966. /* GW522x-B adds WDOG1_B external reset */
  967. if (rev < 'B')
  968. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  969. }
  970. /* GW520x-E adds WDOG1_B external reset */
  971. else if (info->model[4] == '0' && rev < 'E')
  972. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  973. break;
  974. case GW53xx:
  975. /* GW53xx-E adds WDOG1_B external reset */
  976. if (rev < 'E')
  977. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  978. break;
  979. case GW54xx:
  980. /*
  981. * disable serial2 node for GW54xx for compatibility with older
  982. * 3.10.x kernel that improperly had this node enabled in the DT
  983. */
  984. fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
  985. 0);
  986. /* GW54xx-E adds WDOG2_B external reset */
  987. if (rev < 'E')
  988. ft_board_wdog_fixup(blob, WDOG2_ADDR);
  989. break;
  990. case GW551x:
  991. /*
  992. * isolate CSI0_DATA_EN for GW551x-A to work around errata
  993. * causing non functional digital video in (it is not hooked up)
  994. */
  995. if (rev == 'A') {
  996. u32 *range = NULL;
  997. int len;
  998. const u32 *handle = NULL;
  999. i = fdt_node_offset_by_compatible(blob, -1,
  1000. "fsl,imx-tda1997x-video");
  1001. if (i)
  1002. handle = fdt_getprop(blob, i, "pinctrl-0",
  1003. NULL);
  1004. if (handle)
  1005. i = fdt_node_offset_by_phandle(blob,
  1006. fdt32_to_cpu(*handle));
  1007. if (i)
  1008. range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
  1009. &len);
  1010. if (range) {
  1011. len /= sizeof(u32);
  1012. for (i = 0; i < len; i += 6) {
  1013. u32 mux_reg = fdt32_to_cpu(range[i+0]);
  1014. u32 conf_reg = fdt32_to_cpu(range[i+1]);
  1015. /* mux PAD_CSI0_DATA_EN to GPIO */
  1016. if (is_cpu_type(MXC_CPU_MX6Q) &&
  1017. mux_reg == 0x260 &&
  1018. conf_reg == 0x630)
  1019. range[i+3] = cpu_to_fdt32(0x5);
  1020. else if (!is_cpu_type(MXC_CPU_MX6Q) &&
  1021. mux_reg == 0x08c &&
  1022. conf_reg == 0x3a0)
  1023. range[i+3] = cpu_to_fdt32(0x5);
  1024. }
  1025. fdt_setprop_inplace(blob, i, "fsl,pins", range,
  1026. len);
  1027. }
  1028. /* set BT656 video format */
  1029. ft_sethdmiinfmt(blob, "yuv422bt656");
  1030. }
  1031. /* GW551x-C adds WDOG1_B external reset */
  1032. if (rev < 'C')
  1033. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1034. break;
  1035. case GW5901:
  1036. case GW5902:
  1037. /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
  1038. if (rev < 'B')
  1039. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1040. break;
  1041. }
  1042. /* Configure DIO */
  1043. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  1044. struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
  1045. char arg[10];
  1046. sprintf(arg, "dio%d", i);
  1047. if (!hwconfig(arg))
  1048. continue;
  1049. if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
  1050. {
  1051. phys_addr_t addr;
  1052. int off;
  1053. printf(" Enabling pwm%d for DIO%d\n",
  1054. cfg->pwm_param, i);
  1055. addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
  1056. off = fdt_node_offset_by_compat_reg(blob,
  1057. "fsl,imx6q-pwm",
  1058. addr);
  1059. if (off)
  1060. fdt_status_okay(blob, off);
  1061. }
  1062. }
  1063. /* remove no-1-8-v if UHS-I support is present */
  1064. if (gpio_cfg[board_type].usd_vsel) {
  1065. debug("Enabling UHS-I support\n");
  1066. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
  1067. USDHC3_ADDR);
  1068. if (i)
  1069. fdt_delprop(blob, i, "no-1-8-v");
  1070. }
  1071. #if defined(CONFIG_CMD_PCI)
  1072. if (!env_get("nopcifixup"))
  1073. ft_board_pci_fixup(blob, bd);
  1074. #endif
  1075. /*
  1076. * Peripheral Config:
  1077. * remove nodes by alias path if EEPROM config tells us the
  1078. * peripheral is not loaded on the board.
  1079. */
  1080. if (env_get("fdt_noconfig")) {
  1081. puts(" Skiping periperhal config (fdt_noconfig defined)\n");
  1082. return 0;
  1083. }
  1084. cfg = econfig;
  1085. while (cfg->name) {
  1086. if (!test_bit(cfg->bit, info->config)) {
  1087. fdt_del_node_and_alias(blob, cfg->dtalias ?
  1088. cfg->dtalias : cfg->name);
  1089. }
  1090. cfg++;
  1091. }
  1092. return 0;
  1093. }
  1094. #endif /* CONFIG_OF_BOARD_SETUP */