pixis.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2006,2010 Freescale Semiconductor
  4. * Jeff Brown
  5. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <asm/io.h>
  10. #define pixis_base (u8 *)PIXIS_BASE
  11. /*
  12. * Simple board reset.
  13. */
  14. void pixis_reset(void)
  15. {
  16. out_8(pixis_base + PIXIS_RST, 0);
  17. while (1);
  18. }
  19. /*
  20. * Per table 27, page 58 of MPC8641HPCN spec.
  21. */
  22. static int set_px_sysclk(unsigned long sysclk)
  23. {
  24. u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
  25. switch (sysclk) {
  26. case 33:
  27. sysclk_s = 0x04;
  28. sysclk_r = 0x04;
  29. sysclk_v = 0x07;
  30. sysclk_aux = 0x00;
  31. break;
  32. case 40:
  33. sysclk_s = 0x01;
  34. sysclk_r = 0x1F;
  35. sysclk_v = 0x20;
  36. sysclk_aux = 0x01;
  37. break;
  38. case 50:
  39. sysclk_s = 0x01;
  40. sysclk_r = 0x1F;
  41. sysclk_v = 0x2A;
  42. sysclk_aux = 0x02;
  43. break;
  44. case 66:
  45. sysclk_s = 0x01;
  46. sysclk_r = 0x04;
  47. sysclk_v = 0x04;
  48. sysclk_aux = 0x03;
  49. break;
  50. case 83:
  51. sysclk_s = 0x01;
  52. sysclk_r = 0x1F;
  53. sysclk_v = 0x4B;
  54. sysclk_aux = 0x04;
  55. break;
  56. case 100:
  57. sysclk_s = 0x01;
  58. sysclk_r = 0x1F;
  59. sysclk_v = 0x5C;
  60. sysclk_aux = 0x05;
  61. break;
  62. case 134:
  63. sysclk_s = 0x06;
  64. sysclk_r = 0x1F;
  65. sysclk_v = 0x3B;
  66. sysclk_aux = 0x06;
  67. break;
  68. case 166:
  69. sysclk_s = 0x06;
  70. sysclk_r = 0x1F;
  71. sysclk_v = 0x4B;
  72. sysclk_aux = 0x07;
  73. break;
  74. default:
  75. printf("Unsupported SYSCLK frequency.\n");
  76. return 0;
  77. }
  78. vclkh = (sysclk_s << 5) | sysclk_r;
  79. vclkl = sysclk_v;
  80. out_8(pixis_base + PIXIS_VCLKH, vclkh);
  81. out_8(pixis_base + PIXIS_VCLKL, vclkl);
  82. out_8(pixis_base + PIXIS_AUX, sysclk_aux);
  83. return 1;
  84. }
  85. /* Set the CFG_SYSPLL bits
  86. *
  87. * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
  88. * read_from_px_regs() is called.
  89. */
  90. static int set_px_mpxpll(unsigned long mpxpll)
  91. {
  92. switch (mpxpll) {
  93. case 2:
  94. case 4:
  95. case 6:
  96. case 8:
  97. case 10:
  98. case 12:
  99. case 14:
  100. case 16:
  101. clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
  102. return 1;
  103. }
  104. printf("Unsupported MPXPLL ratio.\n");
  105. return 0;
  106. }
  107. static int set_px_corepll(unsigned long corepll)
  108. {
  109. u8 val;
  110. switch (corepll) {
  111. case 20:
  112. val = 0x08;
  113. break;
  114. case 25:
  115. val = 0x0C;
  116. break;
  117. case 30:
  118. val = 0x10;
  119. break;
  120. case 35:
  121. val = 0x1C;
  122. break;
  123. case 40:
  124. val = 0x14;
  125. break;
  126. case 45:
  127. val = 0x0E;
  128. break;
  129. default:
  130. printf("Unsupported COREPLL ratio.\n");
  131. return 0;
  132. }
  133. clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
  134. return 1;
  135. }
  136. #ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
  137. #define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
  138. #endif
  139. /* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
  140. *
  141. * The PIXIS can be programmed to look at either the on-board dip switches
  142. * or various other PIXIS registers to determine the values for COREPLL,
  143. * MPXPLL, and SYSCLK.
  144. *
  145. * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
  146. * register that tells the pixis to use the various PIXIS register.
  147. */
  148. static void read_from_px_regs(int set)
  149. {
  150. u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
  151. if (set)
  152. tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
  153. else
  154. tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
  155. out_8(pixis_base + PIXIS_VCFGEN0, tmp);
  156. }
  157. /* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
  158. * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
  159. */
  160. #ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
  161. #define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
  162. #endif
  163. /* Configure the source of the boot location
  164. *
  165. * The PIXIS can be programmed to look at either the on-board dip switches
  166. * or the PX_VBOOT[LBMAP] register to determine where we should boot.
  167. *
  168. * If we want to boot from the alternate boot bank, we need to tell the PIXIS
  169. * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
  170. */
  171. static void read_from_px_regs_altbank(int set)
  172. {
  173. u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
  174. if (set)
  175. tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
  176. else
  177. tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
  178. out_8(pixis_base + PIXIS_VCFGEN1, tmp);
  179. }
  180. /* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
  181. * tells the PIXIS what the alternate flash bank is.
  182. *
  183. * Note that it's not really a mask. It contains the actual LBMAP bits that
  184. * must be set to select the alternate bank. This code assumes that the
  185. * primary bank has these bits set to 0, and the alternate bank has these
  186. * bits set to 1.
  187. */
  188. #ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
  189. #define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
  190. #endif
  191. /* Tell the PIXIS to boot from the default flash bank
  192. *
  193. * Program the default flash bank into the VBOOT register. This register is
  194. * used only if PX_VCFGEN1[FLASH]=1.
  195. */
  196. static void clear_altbank(void)
  197. {
  198. clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
  199. }
  200. /* Tell the PIXIS to boot from the alternate flash bank
  201. *
  202. * Program the alternate flash bank into the VBOOT register. This register is
  203. * used only if PX_VCFGEN1[FLASH]=1.
  204. */
  205. static void set_altbank(void)
  206. {
  207. setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
  208. }
  209. /* Reset the board with watchdog disabled.
  210. *
  211. * This respects the altbank setting.
  212. */
  213. static void set_px_go(void)
  214. {
  215. /* Disable the VELA sequencer and watchdog */
  216. clrbits_8(pixis_base + PIXIS_VCTL, 9);
  217. /* Reboot by starting the VELA sequencer */
  218. setbits_8(pixis_base + PIXIS_VCTL, 0x1);
  219. while (1);
  220. }
  221. /* Reset the board with watchdog enabled.
  222. *
  223. * This respects the altbank setting.
  224. */
  225. static void set_px_go_with_watchdog(void)
  226. {
  227. /* Disable the VELA sequencer */
  228. clrbits_8(pixis_base + PIXIS_VCTL, 1);
  229. /* Enable the watchdog and reboot by starting the VELA sequencer */
  230. setbits_8(pixis_base + PIXIS_VCTL, 0x9);
  231. while (1);
  232. }
  233. /* Disable the watchdog
  234. *
  235. */
  236. static int pixis_disable_watchdog_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  237. char *const argv[])
  238. {
  239. /* Disable the VELA sequencer and the watchdog */
  240. clrbits_8(pixis_base + PIXIS_VCTL, 9);
  241. return 0;
  242. }
  243. U_BOOT_CMD(
  244. diswd, 1, 0, pixis_disable_watchdog_cmd,
  245. "Disable watchdog timer",
  246. ""
  247. );
  248. #ifdef CONFIG_PIXIS_SGMII_CMD
  249. /* Enable or disable SGMII mode for a TSEC
  250. */
  251. static int pixis_set_sgmii(struct cmd_tbl *cmdtp, int flag, int argc,
  252. char *const argv[])
  253. {
  254. int which_tsec = -1;
  255. unsigned char mask;
  256. unsigned char switch_mask;
  257. if ((argc > 2) && (strcmp(argv[1], "all") != 0))
  258. which_tsec = simple_strtoul(argv[1], NULL, 0);
  259. switch (which_tsec) {
  260. #ifdef CONFIG_TSEC1
  261. case 1:
  262. mask = PIXIS_VSPEED2_TSEC1SER;
  263. switch_mask = PIXIS_VCFGEN1_TSEC1SER;
  264. break;
  265. #endif
  266. #ifdef CONFIG_TSEC2
  267. case 2:
  268. mask = PIXIS_VSPEED2_TSEC2SER;
  269. switch_mask = PIXIS_VCFGEN1_TSEC2SER;
  270. break;
  271. #endif
  272. #ifdef CONFIG_TSEC3
  273. case 3:
  274. mask = PIXIS_VSPEED2_TSEC3SER;
  275. switch_mask = PIXIS_VCFGEN1_TSEC3SER;
  276. break;
  277. #endif
  278. #ifdef CONFIG_TSEC4
  279. case 4:
  280. mask = PIXIS_VSPEED2_TSEC4SER;
  281. switch_mask = PIXIS_VCFGEN1_TSEC4SER;
  282. break;
  283. #endif
  284. default:
  285. mask = PIXIS_VSPEED2_MASK;
  286. switch_mask = PIXIS_VCFGEN1_MASK;
  287. break;
  288. }
  289. /* Toggle whether the switches or FPGA control the settings */
  290. if (!strcmp(argv[argc - 1], "switch"))
  291. clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
  292. else
  293. setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
  294. /* If it's not the switches, enable or disable SGMII, as specified */
  295. if (!strcmp(argv[argc - 1], "on"))
  296. clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
  297. else if (!strcmp(argv[argc - 1], "off"))
  298. setbits_8(pixis_base + PIXIS_VSPEED2, mask);
  299. return 0;
  300. }
  301. U_BOOT_CMD(
  302. pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
  303. "pixis_set_sgmii"
  304. " - Enable or disable SGMII mode for a given TSEC \n",
  305. "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
  306. " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
  307. " on - enables SGMII\n"
  308. " off - disables SGMII\n"
  309. " switch - use switch settings"
  310. );
  311. #endif
  312. /*
  313. * This function takes the non-integral cpu:mpx pll ratio
  314. * and converts it to an integer that can be used to assign
  315. * FPGA register values.
  316. * input: strptr i.e. argv[2]
  317. */
  318. static unsigned long strfractoint(char *strptr)
  319. {
  320. int i, j;
  321. int mulconst;
  322. int no_dec = 0;
  323. unsigned long intval = 0, decval = 0;
  324. char intarr[3], decarr[3];
  325. /* Assign the integer part to intarr[]
  326. * If there is no decimal point i.e.
  327. * if the ratio is an integral value
  328. * simply create the intarr.
  329. */
  330. i = 0;
  331. while (strptr[i] != '.') {
  332. if (strptr[i] == 0) {
  333. no_dec = 1;
  334. break;
  335. }
  336. intarr[i] = strptr[i];
  337. i++;
  338. }
  339. intarr[i] = '\0';
  340. if (no_dec) {
  341. /* Currently needed only for single digit corepll ratios */
  342. mulconst = 10;
  343. decval = 0;
  344. } else {
  345. j = 0;
  346. i++; /* Skipping the decimal point */
  347. while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
  348. decarr[j] = strptr[i];
  349. i++;
  350. j++;
  351. }
  352. decarr[j] = '\0';
  353. mulconst = 1;
  354. for (i = 0; i < j; i++)
  355. mulconst *= 10;
  356. decval = dectoul(decarr, NULL);
  357. }
  358. intval = dectoul(intarr, NULL);
  359. intval = intval * mulconst;
  360. return intval + decval;
  361. }
  362. static int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  363. char *const argv[])
  364. {
  365. unsigned int i;
  366. char *p_cf = NULL;
  367. char *p_cf_sysclk = NULL;
  368. char *p_cf_corepll = NULL;
  369. char *p_cf_mpxpll = NULL;
  370. char *p_altbank = NULL;
  371. char *p_wd = NULL;
  372. int unknown_param = 0;
  373. /*
  374. * No args is a simple reset request.
  375. */
  376. if (argc <= 1) {
  377. pixis_reset();
  378. /* not reached */
  379. }
  380. for (i = 1; i < argc; i++) {
  381. if (strcmp(argv[i], "cf") == 0) {
  382. p_cf = argv[i];
  383. if (i + 3 >= argc) {
  384. break;
  385. }
  386. p_cf_sysclk = argv[i+1];
  387. p_cf_corepll = argv[i+2];
  388. p_cf_mpxpll = argv[i+3];
  389. i += 3;
  390. continue;
  391. }
  392. if (strcmp(argv[i], "altbank") == 0) {
  393. p_altbank = argv[i];
  394. continue;
  395. }
  396. if (strcmp(argv[i], "wd") == 0) {
  397. p_wd = argv[i];
  398. continue;
  399. }
  400. unknown_param = 1;
  401. }
  402. /*
  403. * Check that cf has all required parms
  404. */
  405. if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
  406. || unknown_param) {
  407. #ifdef CONFIG_SYS_LONGHELP
  408. puts(cmdtp->help);
  409. putc('\n');
  410. #endif
  411. return 1;
  412. }
  413. /*
  414. * PIXIS seems to be sensitive to the ordering of
  415. * the registers that are touched.
  416. */
  417. read_from_px_regs(0);
  418. if (p_altbank)
  419. read_from_px_regs_altbank(0);
  420. clear_altbank();
  421. /*
  422. * Clock configuration specified.
  423. */
  424. if (p_cf) {
  425. unsigned long sysclk;
  426. unsigned long corepll;
  427. unsigned long mpxpll;
  428. sysclk = dectoul(p_cf_sysclk, NULL);
  429. corepll = strfractoint(p_cf_corepll);
  430. mpxpll = dectoul(p_cf_mpxpll, NULL);
  431. if (!(set_px_sysclk(sysclk)
  432. && set_px_corepll(corepll)
  433. && set_px_mpxpll(mpxpll))) {
  434. #ifdef CONFIG_SYS_LONGHELP
  435. puts(cmdtp->help);
  436. putc('\n');
  437. #endif
  438. return 1;
  439. }
  440. read_from_px_regs(1);
  441. }
  442. /*
  443. * Altbank specified
  444. *
  445. * NOTE CHANGE IN BEHAVIOR: previous code would default
  446. * to enabling watchdog if altbank is specified.
  447. * Now the watchdog must be enabled explicitly using 'wd'.
  448. */
  449. if (p_altbank) {
  450. set_altbank();
  451. read_from_px_regs_altbank(1);
  452. }
  453. /*
  454. * Reset with watchdog specified.
  455. */
  456. if (p_wd)
  457. set_px_go_with_watchdog();
  458. else
  459. set_px_go();
  460. /*
  461. * Shouldn't be reached.
  462. */
  463. return 0;
  464. }
  465. U_BOOT_CMD(
  466. pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
  467. "Reset the board using the FPGA sequencer",
  468. " pixis_reset\n"
  469. " pixis_reset [altbank]\n"
  470. " pixis_reset altbank wd\n"
  471. " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
  472. " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
  473. );