da850evm.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on da830evm.c. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  8. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <env.h>
  13. #include <i2c.h>
  14. #include <init.h>
  15. #include <net.h>
  16. #include <spi.h>
  17. #include <spi_flash.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/global_data.h>
  20. #include <asm/ti-common/davinci_nand.h>
  21. #include <asm/arch/emac_defs.h>
  22. #include <asm/arch/pinmux_defs.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/davinci_misc.h>
  25. #include <linux/errno.h>
  26. #include <hwconfig.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/gpio.h>
  29. #ifdef CONFIG_MMC_DAVINCI
  30. #include <mmc.h>
  31. #include <asm/arch/sdmmc_defs.h>
  32. #endif
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #ifdef CONFIG_DRIVER_TI_EMAC
  35. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  36. #define HAS_RMII 1
  37. #else
  38. #define HAS_RMII 0
  39. #endif
  40. #endif /* CONFIG_DRIVER_TI_EMAC */
  41. #define CFG_MAC_ADDR_SPI_BUS 0
  42. #define CFG_MAC_ADDR_SPI_CS 0
  43. #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  44. #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
  45. #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
  46. #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
  47. static int get_mac_addr(u8 *addr)
  48. {
  49. struct spi_flash *flash;
  50. int ret;
  51. flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
  52. CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
  53. if (!flash) {
  54. printf("Error - unable to probe SPI flash.\n");
  55. return -1;
  56. }
  57. ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
  58. if (ret) {
  59. printf("Error - unable to read MAC address from SPI flash.\n");
  60. return -1;
  61. }
  62. return ret;
  63. }
  64. #endif
  65. void dsp_lpsc_on(unsigned domain, unsigned int id)
  66. {
  67. dv_reg_p mdstat, mdctl, ptstat, ptcmd;
  68. struct davinci_psc_regs *psc_regs;
  69. psc_regs = davinci_psc0_regs;
  70. mdstat = &psc_regs->psc0.mdstat[id];
  71. mdctl = &psc_regs->psc0.mdctl[id];
  72. ptstat = &psc_regs->ptstat;
  73. ptcmd = &psc_regs->ptcmd;
  74. while (*ptstat & (0x1 << domain))
  75. ;
  76. if ((*mdstat & 0x1f) == 0x03)
  77. return; /* Already on and enabled */
  78. *mdctl |= 0x03;
  79. *ptcmd = 0x1 << domain;
  80. while (*ptstat & (0x1 << domain))
  81. ;
  82. while ((*mdstat & 0x1f) != 0x03)
  83. ; /* Probably an overkill... */
  84. }
  85. static void dspwake(void)
  86. {
  87. unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
  88. u32 val;
  89. /* if the device is ARM only, return */
  90. if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
  91. return;
  92. if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
  93. return;
  94. *resetvect++ = 0x1E000; /* DSP Idle */
  95. /* clear out the next 10 words as NOP */
  96. memset(resetvect, 0, sizeof(unsigned) *10);
  97. /* setup the DSP reset vector */
  98. writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
  99. dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
  100. val = readl(PSC0_MDCTL + (15 * 4));
  101. val |= 0x100;
  102. writel(val, (PSC0_MDCTL + (15 * 4)));
  103. }
  104. int misc_init_r(void)
  105. {
  106. dspwake();
  107. #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
  108. uchar env_enetaddr[6];
  109. int enetaddr_found;
  110. enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
  111. #endif
  112. #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
  113. int spi_mac_read;
  114. uchar buff[6];
  115. spi_mac_read = get_mac_addr(buff);
  116. buff[0] = 0;
  117. /*
  118. * MAC address not present in the environment
  119. * try and read the MAC address from SPI flash
  120. * and set it.
  121. */
  122. if (!enetaddr_found) {
  123. if (!spi_mac_read) {
  124. if (is_valid_ethaddr(buff)) {
  125. if (eth_env_set_enetaddr("ethaddr", buff)) {
  126. printf("Warning: Failed to "
  127. "set MAC address from SPI flash\n");
  128. }
  129. } else {
  130. printf("Warning: Invalid "
  131. "MAC address read from SPI flash\n");
  132. }
  133. }
  134. } else {
  135. /*
  136. * MAC address present in environment compare it with
  137. * the MAC address in SPI flash and warn on mismatch
  138. */
  139. if (!spi_mac_read && is_valid_ethaddr(buff) &&
  140. memcmp(env_enetaddr, buff, 6))
  141. printf("Warning: MAC address in SPI flash don't match "
  142. "with the MAC address in the environment\n");
  143. printf("Default using MAC address from environment\n");
  144. }
  145. #elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
  146. uint8_t enetaddr[8];
  147. int eeprom_mac_read;
  148. /* Read Ethernet MAC address from EEPROM */
  149. eeprom_mac_read = dvevm_read_mac_address(enetaddr);
  150. /*
  151. * MAC address not present in the environment
  152. * try and read the MAC address from EEPROM flash
  153. * and set it.
  154. */
  155. if (!enetaddr_found) {
  156. if (eeprom_mac_read)
  157. /* Set Ethernet MAC address from EEPROM */
  158. davinci_sync_env_enetaddr(enetaddr);
  159. } else {
  160. /*
  161. * MAC address present in environment compare it with
  162. * the MAC address in EEPROM and warn on mismatch
  163. */
  164. if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
  165. printf("Warning: MAC address in EEPROM don't match "
  166. "with the MAC address in the environment\n");
  167. printf("Default using MAC address from environment\n");
  168. }
  169. #endif
  170. return 0;
  171. }
  172. static const struct pinmux_config gpio_pins[] = {
  173. #ifdef CONFIG_MTD_NOR_FLASH
  174. /* GP0[11] is required for NOR to work on Rev 3 EVMs */
  175. { pinmux(0), 8, 4 }, /* GP0[11] */
  176. #endif
  177. #ifdef CONFIG_MMC_DAVINCI
  178. /* GP0[11] is required for SD to work on Rev 3 EVMs */
  179. { pinmux(0), 8, 4 }, /* GP0[11] */
  180. #endif
  181. };
  182. const struct pinmux_resource pinmuxes[] = {
  183. #ifdef CONFIG_DRIVER_TI_EMAC
  184. PINMUX_ITEM(emac_pins_mdio),
  185. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  186. PINMUX_ITEM(emac_pins_rmii),
  187. #else
  188. PINMUX_ITEM(emac_pins_mii),
  189. #endif
  190. #endif
  191. #ifdef CONFIG_SPI_FLASH
  192. PINMUX_ITEM(spi1_pins_base),
  193. PINMUX_ITEM(spi1_pins_scs0),
  194. #endif
  195. PINMUX_ITEM(uart2_pins_txrx),
  196. PINMUX_ITEM(uart2_pins_rtscts),
  197. PINMUX_ITEM(i2c0_pins),
  198. #ifdef CONFIG_NAND_DAVINCI
  199. PINMUX_ITEM(emifa_pins_cs3),
  200. PINMUX_ITEM(emifa_pins_cs4),
  201. PINMUX_ITEM(emifa_pins_nand),
  202. #elif defined(CONFIG_MTD_NOR_FLASH)
  203. PINMUX_ITEM(emifa_pins_cs2),
  204. PINMUX_ITEM(emifa_pins_nor),
  205. #endif
  206. PINMUX_ITEM(gpio_pins),
  207. #ifdef CONFIG_MMC_DAVINCI
  208. PINMUX_ITEM(mmc0_pins),
  209. #endif
  210. };
  211. const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
  212. const struct lpsc_resource lpsc[] = {
  213. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  214. { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
  215. { DAVINCI_LPSC_EMAC }, /* image download */
  216. { DAVINCI_LPSC_UART2 }, /* console */
  217. { DAVINCI_LPSC_GPIO },
  218. #ifdef CONFIG_MMC_DAVINCI
  219. { DAVINCI_LPSC_MMC_SD },
  220. #endif
  221. };
  222. const int lpsc_size = ARRAY_SIZE(lpsc);
  223. #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
  224. #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
  225. #endif
  226. #define REV_AM18X_EVM 0x100
  227. /*
  228. * get_board_rev() - setup to pass kernel board revision information
  229. * Returns:
  230. * bit[0-3] Maximum cpu clock rate supported by onboard SoC
  231. * 0000b - 300 MHz
  232. * 0001b - 372 MHz
  233. * 0010b - 408 MHz
  234. * 0011b - 456 MHz
  235. */
  236. u32 get_board_rev(void)
  237. {
  238. char *s;
  239. u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
  240. u32 rev = 0;
  241. s = env_get("maxcpuclk");
  242. if (s)
  243. maxcpuclk = dectoul(s, NULL);
  244. if (maxcpuclk >= 456000000)
  245. rev = 3;
  246. else if (maxcpuclk >= 408000000)
  247. rev = 2;
  248. else if (maxcpuclk >= 372000000)
  249. rev = 1;
  250. return rev;
  251. }
  252. int board_early_init_f(void)
  253. {
  254. /*
  255. * Power on required peripherals
  256. * ARM does not have access by default to PSC0 and PSC1
  257. * assuming here that the DSP bootloader has set the IOPU
  258. * such that PSC access is available to ARM
  259. */
  260. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  261. return 1;
  262. return 0;
  263. }
  264. int board_init(void)
  265. {
  266. irq_init();
  267. #ifdef CONFIG_NAND_DAVINCI
  268. /*
  269. * NAND CS setup - cycle counts based on da850evm NAND timings in the
  270. * Linux kernel @ 25MHz EMIFA
  271. */
  272. writel((DAVINCI_ABCR_WSETUP(2) |
  273. DAVINCI_ABCR_WSTROBE(2) |
  274. DAVINCI_ABCR_WHOLD(1) |
  275. DAVINCI_ABCR_RSETUP(1) |
  276. DAVINCI_ABCR_RSTROBE(4) |
  277. DAVINCI_ABCR_RHOLD(0) |
  278. DAVINCI_ABCR_TA(1) |
  279. DAVINCI_ABCR_ASIZE_8BIT),
  280. &davinci_emif_regs->ab2cr); /* CS3 */
  281. #endif
  282. /* arch number of the board */
  283. gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
  284. /* address of boot parameters */
  285. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  286. /* setup the SUSPSRC for ARM to control emulation suspend */
  287. writel(readl(&davinci_syscfg_regs->suspsrc) &
  288. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  289. DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  290. DAVINCI_SYSCFG_SUSPSRC_UART2),
  291. &davinci_syscfg_regs->suspsrc);
  292. #ifdef CONFIG_MTD_NOR_FLASH
  293. /* Set the GPIO direction as output */
  294. clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
  295. /* Set the output as low */
  296. writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
  297. #endif
  298. #ifdef CONFIG_MMC_DAVINCI
  299. /* Set the GPIO direction as output */
  300. clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
  301. /* Set the output as high */
  302. writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
  303. #endif
  304. #ifdef CONFIG_DRIVER_TI_EMAC
  305. davinci_emac_mii_mode_sel(HAS_RMII);
  306. #endif /* CONFIG_DRIVER_TI_EMAC */
  307. return 0;
  308. }
  309. #ifdef CONFIG_DRIVER_TI_EMAC
  310. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  311. /**
  312. * rmii_hw_init
  313. *
  314. * DA850/OMAP-L138 EVM can interface to a daughter card for
  315. * additional features. This card has an I2C GPIO Expander TCA6416
  316. * to select the required functions like camera, RMII Ethernet,
  317. * character LCD, video.
  318. *
  319. * Initialization of the expander involves configuring the
  320. * polarity and direction of the ports. P07-P05 are used here.
  321. * These ports are connected to a Mux chip which enables only one
  322. * functionality at a time.
  323. *
  324. * For RMII phy to respond, the MII MDIO clock has to be disabled
  325. * since both the PHY devices have address as zero. The MII MDIO
  326. * clock is controlled via GPIO2[6].
  327. *
  328. * This code is valid for Beta version of the hardware
  329. */
  330. int rmii_hw_init(void)
  331. {
  332. const struct pinmux_config gpio_pins[] = {
  333. { pinmux(6), 8, 1 }
  334. };
  335. u_int8_t buf[2];
  336. unsigned int temp;
  337. int ret;
  338. /* PinMux for GPIO */
  339. if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
  340. return 1;
  341. /* I2C Exapnder configuration */
  342. /* Set polarity to non-inverted */
  343. buf[0] = 0x0;
  344. buf[1] = 0x0;
  345. ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
  346. if (ret) {
  347. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  348. CONFIG_SYS_I2C_EXPANDER_ADDR);
  349. return ret;
  350. }
  351. /* Configure P07-P05 as outputs */
  352. buf[0] = 0x1f;
  353. buf[1] = 0xff;
  354. ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
  355. if (ret) {
  356. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  357. CONFIG_SYS_I2C_EXPANDER_ADDR);
  358. }
  359. /* For Ethernet RMII selection
  360. * P07(SelA)=0
  361. * P06(SelB)=1
  362. * P05(SelC)=1
  363. */
  364. if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
  365. printf("\nExpander @ 0x%02x read FAILED!!!\n",
  366. CONFIG_SYS_I2C_EXPANDER_ADDR);
  367. }
  368. buf[0] &= 0x1f;
  369. buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
  370. if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
  371. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  372. CONFIG_SYS_I2C_EXPANDER_ADDR);
  373. }
  374. /* Set the output as high */
  375. temp = REG(GPIO_BANK2_REG_SET_ADDR);
  376. temp |= (0x01 << 6);
  377. REG(GPIO_BANK2_REG_SET_ADDR) = temp;
  378. /* Set the GPIO direction as output */
  379. temp = REG(GPIO_BANK2_REG_DIR_ADDR);
  380. temp &= ~(0x01 << 6);
  381. REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
  382. return 0;
  383. }
  384. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  385. /*
  386. * Initializes on-board ethernet controllers.
  387. */
  388. int board_eth_init(struct bd_info *bis)
  389. {
  390. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  391. /* Select RMII fucntion through the expander */
  392. if (rmii_hw_init())
  393. printf("RMII hardware init failed!!!\n");
  394. #endif
  395. return 0;
  396. }
  397. #endif /* CONFIG_DRIVER_TI_EMAC */