ecc.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on the contribution of Marian Balakowicz <m8@semihalf.com>
  7. */
  8. #include <common.h>
  9. #include <irq_func.h>
  10. #include <mpc83xx.h>
  11. #include <command.h>
  12. #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
  13. void ecc_print_status(void)
  14. {
  15. immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  16. #ifdef CONFIG_SYS_FSL_DDR2
  17. struct ccsr_ddr __iomem *ddr = &immap->ddr;
  18. #else
  19. ddr83xx_t *ddr = &immap->ddr;
  20. #endif
  21. printf("\nECC mode: %s\n\n",
  22. (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
  23. /* Interrupts */
  24. printf("Memory Error Interrupt Enable:\n");
  25. printf(" Multiple-Bit Error Interrupt Enable: %d\n",
  26. (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
  27. printf(" Single-Bit Error Interrupt Enable: %d\n",
  28. (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
  29. printf(" Memory Select Error Interrupt Enable: %d\n\n",
  30. (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
  31. /* Error disable */
  32. printf("Memory Error Disable:\n");
  33. printf(" Multiple-Bit Error Disable: %d\n",
  34. (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
  35. printf(" Single-Bit Error Disable: %d\n",
  36. (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
  37. printf(" Memory Select Error Disable: %d\n\n",
  38. (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
  39. /* Error injection */
  40. printf("Memory Data Path Error Injection Mask High/Low: %08x %08x\n",
  41. ddr->data_err_inject_hi, ddr->data_err_inject_lo);
  42. printf("Memory Data Path Error Injection Mask ECC:\n");
  43. printf(" ECC Mirror Byte: %d\n",
  44. (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
  45. printf(" ECC Injection Enable: %d\n",
  46. (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
  47. printf(" ECC Error Injection Mask: 0x%02x\n\n",
  48. ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
  49. /* SBE counter/threshold */
  50. printf("Memory Single-Bit Error Management (0..255):\n");
  51. printf(" Single-Bit Error Threshold: %d\n",
  52. (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
  53. printf(" Single-Bit Error Counter: %d\n\n",
  54. (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
  55. /* Error detect */
  56. printf("Memory Error Detect:\n");
  57. printf(" Multiple Memory Errors: %d\n",
  58. (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
  59. printf(" Multiple-Bit Error: %d\n",
  60. (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
  61. printf(" Single-Bit Error: %d\n",
  62. (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
  63. printf(" Memory Select Error: %d\n\n",
  64. (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
  65. /* Capture data */
  66. printf("Memory Error Address Capture: 0x%08x\n", ddr->capture_address);
  67. printf("Memory Data Path Read Capture High/Low: %08x %08x\n",
  68. ddr->capture_data_hi, ddr->capture_data_lo);
  69. printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
  70. ddr->capture_ecc & CAPTURE_ECC_ECE);
  71. printf("Memory Error Attributes Capture:\n");
  72. printf(" Data Beat Number: %d\n",
  73. (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
  74. ECC_CAPT_ATTR_BNUM_SHIFT);
  75. printf(" Transaction Size: %d\n",
  76. (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
  77. ECC_CAPT_ATTR_TSIZ_SHIFT);
  78. printf(" Transaction Source: %d\n",
  79. (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
  80. ECC_CAPT_ATTR_TSRC_SHIFT);
  81. printf(" Transaction Type: %d\n",
  82. (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
  83. ECC_CAPT_ATTR_TTYP_SHIFT);
  84. printf(" Error Information Valid: %d\n\n",
  85. ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
  86. }
  87. int do_ecc(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  88. {
  89. immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  90. #ifdef CONFIG_SYS_FSL_DDR2
  91. struct ccsr_ddr __iomem *ddr = &immap->ddr;
  92. #else
  93. ddr83xx_t *ddr = &immap->ddr;
  94. #endif
  95. volatile u32 val;
  96. u64 *addr;
  97. u32 count;
  98. register u64 *i;
  99. u32 ret[2];
  100. u32 pattern[2];
  101. u32 writeback[2];
  102. /* The pattern is written into memory to generate error */
  103. pattern[0] = 0xfedcba98UL;
  104. pattern[1] = 0x76543210UL;
  105. /* After injecting error, re-initialize the memory with the value */
  106. writeback[0] = 0x01234567UL;
  107. writeback[1] = 0x89abcdefUL;
  108. if (argc > 4)
  109. return cmd_usage(cmdtp);
  110. if (argc == 2) {
  111. if (strcmp(argv[1], "status") == 0) {
  112. ecc_print_status();
  113. return 0;
  114. } else if (strcmp(argv[1], "captureclear") == 0) {
  115. ddr->capture_address = 0;
  116. ddr->capture_data_hi = 0;
  117. ddr->capture_data_lo = 0;
  118. ddr->capture_ecc = 0;
  119. ddr->capture_attributes = 0;
  120. return 0;
  121. }
  122. }
  123. if (argc == 3) {
  124. if (strcmp(argv[1], "sbecnt") == 0) {
  125. val = dectoul(argv[2], NULL);
  126. if (val > 255) {
  127. printf("Incorrect Counter value, "
  128. "should be 0..255\n");
  129. return 1;
  130. }
  131. val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
  132. val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
  133. ddr->err_sbe = val;
  134. return 0;
  135. } else if (strcmp(argv[1], "sbethr") == 0) {
  136. val = dectoul(argv[2], NULL);
  137. if (val > 255) {
  138. printf("Incorrect Counter value, "
  139. "should be 0..255\n");
  140. return 1;
  141. }
  142. val = (val << ECC_ERROR_MAN_SBET_SHIFT);
  143. val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
  144. ddr->err_sbe = val;
  145. return 0;
  146. } else if (strcmp(argv[1], "errdisable") == 0) {
  147. val = ddr->err_disable;
  148. if (strcmp(argv[2], "+sbe") == 0) {
  149. val |= ECC_ERROR_DISABLE_SBED;
  150. } else if (strcmp(argv[2], "+mbe") == 0) {
  151. val |= ECC_ERROR_DISABLE_MBED;
  152. } else if (strcmp(argv[2], "+mse") == 0) {
  153. val |= ECC_ERROR_DISABLE_MSED;
  154. } else if (strcmp(argv[2], "+all") == 0) {
  155. val |= (ECC_ERROR_DISABLE_SBED |
  156. ECC_ERROR_DISABLE_MBED |
  157. ECC_ERROR_DISABLE_MSED);
  158. } else if (strcmp(argv[2], "-sbe") == 0) {
  159. val &= ~ECC_ERROR_DISABLE_SBED;
  160. } else if (strcmp(argv[2], "-mbe") == 0) {
  161. val &= ~ECC_ERROR_DISABLE_MBED;
  162. } else if (strcmp(argv[2], "-mse") == 0) {
  163. val &= ~ECC_ERROR_DISABLE_MSED;
  164. } else if (strcmp(argv[2], "-all") == 0) {
  165. val &= ~(ECC_ERROR_DISABLE_SBED |
  166. ECC_ERROR_DISABLE_MBED |
  167. ECC_ERROR_DISABLE_MSED);
  168. } else {
  169. printf("Incorrect err_disable field\n");
  170. return 1;
  171. }
  172. ddr->err_disable = val;
  173. sync();
  174. isync();
  175. return 0;
  176. } else if (strcmp(argv[1], "errdetectclr") == 0) {
  177. val = ddr->err_detect;
  178. if (strcmp(argv[2], "mme") == 0) {
  179. val |= ECC_ERROR_DETECT_MME;
  180. } else if (strcmp(argv[2], "sbe") == 0) {
  181. val |= ECC_ERROR_DETECT_SBE;
  182. } else if (strcmp(argv[2], "mbe") == 0) {
  183. val |= ECC_ERROR_DETECT_MBE;
  184. } else if (strcmp(argv[2], "mse") == 0) {
  185. val |= ECC_ERROR_DETECT_MSE;
  186. } else if (strcmp(argv[2], "all") == 0) {
  187. val |= (ECC_ERROR_DETECT_MME |
  188. ECC_ERROR_DETECT_MBE |
  189. ECC_ERROR_DETECT_SBE |
  190. ECC_ERROR_DETECT_MSE);
  191. } else {
  192. printf("Incorrect err_detect field\n");
  193. return 1;
  194. }
  195. ddr->err_detect = val;
  196. return 0;
  197. } else if (strcmp(argv[1], "injectdatahi") == 0) {
  198. val = hextoul(argv[2], NULL);
  199. ddr->data_err_inject_hi = val;
  200. return 0;
  201. } else if (strcmp(argv[1], "injectdatalo") == 0) {
  202. val = hextoul(argv[2], NULL);
  203. ddr->data_err_inject_lo = val;
  204. return 0;
  205. } else if (strcmp(argv[1], "injectecc") == 0) {
  206. val = hextoul(argv[2], NULL);
  207. if (val > 0xff) {
  208. printf("Incorrect ECC inject mask, "
  209. "should be 0x00..0xff\n");
  210. return 1;
  211. }
  212. val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
  213. ddr->ecc_err_inject = val;
  214. return 0;
  215. } else if (strcmp(argv[1], "inject") == 0) {
  216. val = ddr->ecc_err_inject;
  217. if (strcmp(argv[2], "en") == 0)
  218. val |= ECC_ERR_INJECT_EIEN;
  219. else if (strcmp(argv[2], "dis") == 0)
  220. val &= ~ECC_ERR_INJECT_EIEN;
  221. else
  222. printf("Incorrect command\n");
  223. ddr->ecc_err_inject = val;
  224. sync();
  225. isync();
  226. return 0;
  227. } else if (strcmp(argv[1], "mirror") == 0) {
  228. val = ddr->ecc_err_inject;
  229. if (strcmp(argv[2], "en") == 0)
  230. val |= ECC_ERR_INJECT_EMB;
  231. else if (strcmp(argv[2], "dis") == 0)
  232. val &= ~ECC_ERR_INJECT_EMB;
  233. else
  234. printf("Incorrect command\n");
  235. ddr->ecc_err_inject = val;
  236. return 0;
  237. }
  238. }
  239. if (argc == 4) {
  240. if (strcmp(argv[1], "testdw") == 0) {
  241. addr = (u64 *)hextoul(argv[2], NULL);
  242. count = hextoul(argv[3], NULL);
  243. if ((u32) addr % 8) {
  244. printf("Address not aligned on "
  245. "double word boundary\n");
  246. return 1;
  247. }
  248. disable_interrupts();
  249. for (i = addr; i < addr + count; i++) {
  250. /* enable injects */
  251. ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
  252. sync();
  253. isync();
  254. /* write memory location injecting errors */
  255. ppcDWstore((u32 *) i, pattern);
  256. sync();
  257. /* disable injects */
  258. ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
  259. sync();
  260. isync();
  261. /* read data, this generates ECC error */
  262. ppcDWload((u32 *) i, ret);
  263. sync();
  264. /* re-initialize memory, double word write the location again,
  265. * generates new ECC code this time */
  266. ppcDWstore((u32 *) i, writeback);
  267. sync();
  268. }
  269. enable_interrupts();
  270. return 0;
  271. }
  272. if (strcmp(argv[1], "testword") == 0) {
  273. addr = (u64 *)hextoul(argv[2], NULL);
  274. count = hextoul(argv[3], NULL);
  275. if ((u32) addr % 8) {
  276. printf("Address not aligned on "
  277. "double word boundary\n");
  278. return 1;
  279. }
  280. disable_interrupts();
  281. for (i = addr; i < addr + count; i++) {
  282. /* enable injects */
  283. ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
  284. sync();
  285. isync();
  286. /* write memory location injecting errors */
  287. *(u32 *) i = 0xfedcba98UL;
  288. sync();
  289. /* sub double word write,
  290. * bus will read-modify-write,
  291. * generates ECC error */
  292. *((u32 *) i + 1) = 0x76543210UL;
  293. sync();
  294. /* disable injects */
  295. ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
  296. sync();
  297. isync();
  298. /* re-initialize memory,
  299. * double word write the location again,
  300. * generates new ECC code this time */
  301. ppcDWstore((u32 *) i, writeback);
  302. sync();
  303. }
  304. enable_interrupts();
  305. return 0;
  306. }
  307. }
  308. return cmd_usage(cmdtp);
  309. }
  310. U_BOOT_CMD(ecc, 4, 0, do_ecc,
  311. "support for DDR ECC features",
  312. "status - print out status info\n"
  313. "ecc captureclear - clear capture regs data\n"
  314. "ecc sbecnt <val> - set Single-Bit Error counter\n"
  315. "ecc sbethr <val> - set Single-Bit Threshold\n"
  316. "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
  317. " [-|+]sbe - Single-Bit Error\n"
  318. " [-|+]mbe - Multiple-Bit Error\n"
  319. " [-|+]mse - Memory Select Error\n"
  320. " [-|+]all - all errors\n"
  321. "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
  322. " mme - Multiple Memory Errors\n"
  323. " sbe - Single-Bit Error\n"
  324. " mbe - Multiple-Bit Error\n"
  325. " mse - Memory Select Error\n"
  326. " all - all errors\n"
  327. "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
  328. "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
  329. "ecc injectecc <ecc> - set ECC Error Injection Mask\n"
  330. "ecc inject <en|dis> - enable/disable error injection\n"
  331. "ecc mirror <en|dis> - enable/disable mirror byte\n"
  332. "ecc testdw <addr> <cnt> - test mem region with double word access:\n"
  333. " - enables injects\n"
  334. " - writes pattern injecting errors with double word access\n"
  335. " - disables injects\n"
  336. " - reads pattern back with double word access, generates error\n"
  337. " - re-inits memory\n"
  338. "ecc testword <addr> <cnt> - test mem region with word access:\n"
  339. " - enables injects\n"
  340. " - writes pattern injecting errors with word access\n"
  341. " - writes pattern with word access, generates error\n"
  342. " - disables injects\n" " - re-inits memory");
  343. #endif