cpu_init.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm-offsets.h>
  7. #include <mpc83xx.h>
  8. #include <ioports.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <asm/processor.h>
  12. #include <fsl_qe.h>
  13. #ifdef CONFIG_USB_EHCI_FSL
  14. #include <usb/ehci-ci.h>
  15. #endif
  16. #include <linux/delay.h>
  17. #ifdef CONFIG_QE
  18. #include <fsl_qe.h>
  19. #endif
  20. #include "lblaw/lblaw.h"
  21. #include "elbc/elbc.h"
  22. #include "sysio/sysio.h"
  23. #include "arbiter/arbiter.h"
  24. #include "initreg/initreg.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #ifdef CONFIG_QE
  27. extern qe_iop_conf_t qe_iop_conf_tab[];
  28. extern void qe_config_iopin(u8 port, u8 pin, int dir,
  29. int open_drain, int assign);
  30. #if !defined(CONFIG_PINCTRL)
  31. static void config_qe_ioports(void)
  32. {
  33. u8 port, pin;
  34. int dir, open_drain, assign;
  35. int i;
  36. for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  37. port = qe_iop_conf_tab[i].port;
  38. pin = qe_iop_conf_tab[i].pin;
  39. dir = qe_iop_conf_tab[i].dir;
  40. open_drain = qe_iop_conf_tab[i].open_drain;
  41. assign = qe_iop_conf_tab[i].assign;
  42. qe_config_iopin(port, pin, dir, open_drain, assign);
  43. }
  44. }
  45. #endif
  46. #endif
  47. /*
  48. * Breathe some life into the CPU...
  49. *
  50. * Set up the memory map,
  51. * initialize a bunch of registers,
  52. * initialize the UPM's
  53. */
  54. void cpu_init_f (volatile immap_t * im)
  55. {
  56. __be32 sccr_mask =
  57. #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  58. SCCR_ENCCM |
  59. #endif
  60. #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  61. SCCR_PCICM |
  62. #endif
  63. #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
  64. SCCR_PCIEXP1CM |
  65. #endif
  66. #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
  67. SCCR_PCIEXP2CM |
  68. #endif
  69. #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  70. SCCR_TSECCM |
  71. #endif
  72. #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  73. SCCR_TSEC1CM |
  74. #endif
  75. #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  76. SCCR_TSEC2CM |
  77. #endif
  78. #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  79. SCCR_TSEC1ON |
  80. #endif
  81. #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  82. SCCR_TSEC2ON |
  83. #endif
  84. #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  85. SCCR_USBMPHCM |
  86. #endif
  87. #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  88. SCCR_USBDRCM |
  89. #endif
  90. #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  91. SCCR_SATACM |
  92. #endif
  93. 0;
  94. __be32 sccr_val =
  95. #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  96. (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
  97. #endif
  98. #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  99. (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
  100. #endif
  101. #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
  102. (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
  103. #endif
  104. #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
  105. (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
  106. #endif
  107. #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  108. (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
  109. #endif
  110. #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  111. (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
  112. #endif
  113. #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  114. (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
  115. #endif
  116. #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  117. (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
  118. #endif
  119. #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  120. (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
  121. #endif
  122. #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  123. (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
  124. #endif
  125. #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  126. (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
  127. #endif
  128. #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  129. (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
  130. #endif
  131. 0;
  132. /* Pointer is writable since we allocated a register for it */
  133. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  134. /* global data region was cleared in start.S */
  135. /* system performance tweaking */
  136. clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
  137. clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
  138. clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
  139. /* RSR - Reset Status Register - clear all status (4.6.1.3) */
  140. gd->arch.reset_status = __raw_readl(&im->reset.rsr);
  141. __raw_writel(~(RSR_RES), &im->reset.rsr);
  142. /* AER - Arbiter Event Register - store status */
  143. gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
  144. gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
  145. /*
  146. * RMR - Reset Mode Register
  147. * contains checkstop reset enable (4.6.1.4)
  148. */
  149. __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
  150. /* LCRR - Clock Ratio Register (10.3.1.16)
  151. * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
  152. */
  153. clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
  154. __raw_readl(&im->im_lbc.lcrr);
  155. isync();
  156. /* Enable Time Base & Decrementer ( so we will have udelay() )*/
  157. setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
  158. /* System General Purpose Register */
  159. #ifdef CONFIG_SYS_SICRH
  160. #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
  161. /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
  162. __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
  163. &im->sysconf.sicrh);
  164. #else
  165. __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
  166. #endif
  167. #endif
  168. #ifdef CONFIG_SYS_SICRL
  169. __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
  170. #endif
  171. #ifdef CONFIG_SYS_GPR1
  172. __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
  173. #endif
  174. #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
  175. __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
  176. #endif
  177. #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
  178. __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
  179. #endif
  180. #if !defined(CONFIG_PINCTRL)
  181. #ifdef CONFIG_QE
  182. /* Config QE ioports */
  183. config_qe_ioports();
  184. #endif
  185. #endif
  186. /* Set up preliminary BR/OR regs */
  187. init_early_memctl_regs();
  188. /* Local Access window setup */
  189. #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
  190. im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
  191. im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
  192. #else
  193. #error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
  194. #endif
  195. #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
  196. im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
  197. im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
  198. #endif
  199. #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
  200. im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
  201. im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
  202. #endif
  203. #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
  204. im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
  205. im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
  206. #endif
  207. #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
  208. im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
  209. im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
  210. #endif
  211. #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
  212. im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
  213. im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
  214. #endif
  215. #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
  216. im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
  217. im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
  218. #endif
  219. #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
  220. im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
  221. im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
  222. #endif
  223. #ifdef CONFIG_SYS_GPIO1_PRELIM
  224. im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
  225. im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
  226. #endif
  227. #ifdef CONFIG_SYS_GPIO2_PRELIM
  228. im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
  229. im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
  230. #endif
  231. #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
  232. uint32_t temp;
  233. struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
  234. /* Configure interface. */
  235. setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
  236. /* Wait for clock to stabilize */
  237. do {
  238. temp = __raw_readl(&ehci->control);
  239. udelay(1000);
  240. } while (!(temp & PHY_CLK_VALID));
  241. #endif
  242. }
  243. int cpu_init_r (void)
  244. {
  245. #ifdef CONFIG_QE
  246. uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
  247. qe_init(qe_base);
  248. qe_reset();
  249. #endif
  250. return 0;
  251. }
  252. /*
  253. * Print out the bus arbiter event
  254. */
  255. #if defined(CONFIG_DISPLAY_AER_FULL)
  256. static int print_83xx_arb_event(int force)
  257. {
  258. static char* event[] = {
  259. "Address Time Out",
  260. "Data Time Out",
  261. "Address Only Transfer Type",
  262. "External Control Word Transfer Type",
  263. "Reserved Transfer Type",
  264. "Transfer Error",
  265. "reserved",
  266. "reserved"
  267. };
  268. static char* master[] = {
  269. "e300 Core Data Transaction",
  270. "reserved",
  271. "e300 Core Instruction Fetch",
  272. "reserved",
  273. "TSEC1",
  274. "TSEC2",
  275. "USB MPH",
  276. "USB DR",
  277. "Encryption Core",
  278. "I2C Boot Sequencer",
  279. "JTAG",
  280. "reserved",
  281. "eSDHC",
  282. "PCI1",
  283. "PCI2",
  284. "DMA",
  285. "QUICC Engine 00",
  286. "QUICC Engine 01",
  287. "QUICC Engine 10",
  288. "QUICC Engine 11",
  289. "reserved",
  290. "reserved",
  291. "reserved",
  292. "reserved",
  293. "SATA1",
  294. "SATA2",
  295. "SATA3",
  296. "SATA4",
  297. "reserved",
  298. "PCI Express 1",
  299. "PCI Express 2",
  300. "TDM-DMAC"
  301. };
  302. static char *transfer[] = {
  303. "Address-only, Clean Block",
  304. "Address-only, lwarx reservation set",
  305. "Single-beat or Burst write",
  306. "reserved",
  307. "Address-only, Flush Block",
  308. "reserved",
  309. "Burst write",
  310. "reserved",
  311. "Address-only, sync",
  312. "Address-only, tlbsync",
  313. "Single-beat or Burst read",
  314. "Single-beat or Burst read",
  315. "Address-only, Kill Block",
  316. "Address-only, icbi",
  317. "Burst read",
  318. "reserved",
  319. "Address-only, eieio",
  320. "reserved",
  321. "Single-beat write",
  322. "reserved",
  323. "ecowx - Illegal single-beat write",
  324. "reserved",
  325. "reserved",
  326. "reserved",
  327. "Address-only, TLB Invalidate",
  328. "reserved",
  329. "Single-beat or Burst read",
  330. "reserved",
  331. "eciwx - Illegal single-beat read",
  332. "reserved",
  333. "Burst read",
  334. "reserved"
  335. };
  336. int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
  337. >> AEATR_EVENT_SHIFT;
  338. int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
  339. >> AEATR_MSTR_ID_SHIFT;
  340. int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
  341. >> AEATR_TBST_SHIFT;
  342. int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
  343. >> AEATR_TSIZE_SHIFT;
  344. int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
  345. >> AEATR_TTYPE_SHIFT;
  346. if (!force && !gd->arch.arbiter_event_address)
  347. return 0;
  348. puts("Arbiter Event Status:\n");
  349. printf(" Event Address: 0x%08lX\n",
  350. gd->arch.arbiter_event_address);
  351. printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
  352. printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
  353. printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
  354. tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
  355. printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
  356. return gd->arch.arbiter_event_address;
  357. }
  358. #elif defined(CONFIG_DISPLAY_AER_BRIEF)
  359. static int print_83xx_arb_event(int force)
  360. {
  361. if (!force && !gd->arch.arbiter_event_address)
  362. return 0;
  363. printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
  364. gd->arch.arbiter_event_attributes,
  365. gd->arch.arbiter_event_address);
  366. return gd->arch.arbiter_event_address;
  367. }
  368. #endif /* CONFIG_DISPLAY_AER_xxxx */
  369. #ifndef CONFIG_CPU_MPC83XX
  370. /*
  371. * Figure out the cause of the reset
  372. */
  373. int prt_83xx_rsr(void)
  374. {
  375. static struct {
  376. ulong mask;
  377. char *desc;
  378. } bits[] = {
  379. {
  380. RSR_SWSR, "Software Soft"}, {
  381. RSR_SWHR, "Software Hard"}, {
  382. RSR_JSRS, "JTAG Soft"}, {
  383. RSR_CSHR, "Check Stop"}, {
  384. RSR_SWRS, "Software Watchdog"}, {
  385. RSR_BMRS, "Bus Monitor"}, {
  386. RSR_SRS, "External/Internal Soft"}, {
  387. RSR_HRS, "External/Internal Hard"}
  388. };
  389. static int n = ARRAY_SIZE(bits);
  390. ulong rsr = gd->arch.reset_status;
  391. int i;
  392. char *sep;
  393. puts("Reset Status:");
  394. sep = " ";
  395. for (i = 0; i < n; i++)
  396. if (rsr & bits[i].mask) {
  397. printf("%s%s", sep, bits[i].desc);
  398. sep = ", ";
  399. }
  400. puts("\n");
  401. #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
  402. print_83xx_arb_event(rsr & RSR_BMRS);
  403. #endif
  404. puts("\n");
  405. return 0;
  406. }
  407. #endif