clock.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Nexell
  4. * Hyunseok, Jung <hsjung@nexell.co.kr>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <linux/err.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/nexell.h>
  11. #include <asm/arch/clk.h>
  12. /*
  13. * clock generator macros
  14. */
  15. #define I_PLL0_BIT (0)
  16. #define I_PLL1_BIT (1)
  17. #define I_PLL2_BIT (2)
  18. #define I_PLL3_BIT (3)
  19. #define I_EXT1_BIT (4)
  20. #define I_EXT2_BIT (5)
  21. #define I_CLKn_BIT (7)
  22. #define I_EXT1_BIT_FORCE (8)
  23. #define I_EXT2_BIT_FORCE (9)
  24. #define I_CLOCK_NUM 6 /* PLL0, PLL1, PLL2, PLL3, EXT1, EXT2 */
  25. #define I_EXECEPT_CLK (0)
  26. #define I_CLOCK_MASK (((1 << I_CLOCK_NUM) - 1) & ~I_EXECEPT_CLK)
  27. #define I_PLL0 (1 << I_PLL0_BIT)
  28. #define I_PLL1 (1 << I_PLL1_BIT)
  29. #define I_PLL2 (1 << I_PLL2_BIT)
  30. #define I_PLL3 (1 << I_PLL3_BIT)
  31. #define I_EXTCLK1 (1 << I_EXT1_BIT)
  32. #define I_EXTCLK2 (1 << I_EXT2_BIT)
  33. #define I_EXTCLK1_FORCE (1 << I_EXT1_BIT_FORCE)
  34. #define I_EXTCLK2_FORCE (1 << I_EXT2_BIT_FORCE)
  35. #define I_PLL_0_1 (I_PLL0 | I_PLL1)
  36. #define I_PLL_0_2 (I_PLL_0_1 | I_PLL2)
  37. #define I_PLL_0_3 (I_PLL_0_2 | I_PLL3)
  38. #define I_CLKnOUT (0)
  39. #define I_PCLK (1 << 16)
  40. #define I_BCLK (1 << 17)
  41. #define I_GATE_PCLK (1 << 20)
  42. #define I_GATE_BCLK (1 << 21)
  43. #define I_PCLK_MASK (I_GATE_PCLK | I_PCLK)
  44. #define I_BCLK_MASK (I_GATE_BCLK | I_BCLK)
  45. struct clk_dev_peri {
  46. const char *dev_name;
  47. void __iomem *base;
  48. int dev_id;
  49. int periph_id;
  50. int clk_step;
  51. u32 in_mask;
  52. u32 in_mask1;
  53. int div_src_0;
  54. int div_val_0;
  55. int invert_0;
  56. int div_src_1;
  57. int div_val_1;
  58. int invert_1;
  59. int in_extclk_1;
  60. int in_extclk_2;
  61. };
  62. struct clk_dev {
  63. struct clk clk;
  64. struct clk *link;
  65. const char *name;
  66. struct clk_dev_peri *peri;
  67. };
  68. struct clk_dev_map {
  69. unsigned int con_enb;
  70. unsigned int con_gen[4];
  71. };
  72. #define CLK_PERI_1S(name, devid, id, addr, mk)[id] = \
  73. { .dev_name = name, .dev_id = devid, .periph_id = id, .clk_step = 1, \
  74. .base = (void *)addr, .in_mask = mk, }
  75. #define CLK_PERI_2S(name, devid, id, addr, mk, mk2)[id] = \
  76. { .dev_name = name, .dev_id = devid, .periph_id = id, .clk_step = 2, \
  77. .base = (void *)addr, .in_mask = mk, .in_mask1 = mk2, }
  78. static const char * const clk_core[] = {
  79. CORECLK_NAME_PLL0, CORECLK_NAME_PLL1, CORECLK_NAME_PLL2,
  80. CORECLK_NAME_PLL3, CORECLK_NAME_FCLK, CORECLK_NAME_MCLK,
  81. CORECLK_NAME_BCLK, CORECLK_NAME_PCLK, CORECLK_NAME_HCLK,
  82. };
  83. /*
  84. * Section ".data" must be used because BSS is not available before relocation,
  85. * in board_init_f(), respectively! I.e. global variables can not be used!
  86. */
  87. static struct clk_dev_peri clk_periphs[]
  88. __section(".data") = {
  89. CLK_PERI_1S(DEV_NAME_TIMER, 0, CLK_ID_TIMER_0,
  90. PHY_BASEADDR_CLKGEN14, (I_PLL_0_2)),
  91. CLK_PERI_1S(DEV_NAME_TIMER, 1, CLK_ID_TIMER_1,
  92. PHY_BASEADDR_CLKGEN0, (I_PLL_0_2)),
  93. CLK_PERI_1S(DEV_NAME_TIMER, 2, CLK_ID_TIMER_2,
  94. PHY_BASEADDR_CLKGEN1, (I_PLL_0_2)),
  95. CLK_PERI_1S(DEV_NAME_TIMER, 3, CLK_ID_TIMER_3,
  96. PHY_BASEADDR_CLKGEN2, (I_PLL_0_2)),
  97. CLK_PERI_1S(DEV_NAME_UART, 0, CLK_ID_UART_0,
  98. PHY_BASEADDR_CLKGEN22, (I_PLL_0_2)),
  99. CLK_PERI_1S(DEV_NAME_UART, 1, CLK_ID_UART_1,
  100. PHY_BASEADDR_CLKGEN24, (I_PLL_0_2)),
  101. CLK_PERI_1S(DEV_NAME_UART, 2, CLK_ID_UART_2,
  102. PHY_BASEADDR_CLKGEN23, (I_PLL_0_2)),
  103. CLK_PERI_1S(DEV_NAME_UART, 3, CLK_ID_UART_3,
  104. PHY_BASEADDR_CLKGEN25, (I_PLL_0_2)),
  105. CLK_PERI_1S(DEV_NAME_UART, 4, CLK_ID_UART_4,
  106. PHY_BASEADDR_CLKGEN26, (I_PLL_0_2)),
  107. CLK_PERI_1S(DEV_NAME_UART, 5, CLK_ID_UART_5,
  108. PHY_BASEADDR_CLKGEN27, (I_PLL_0_2)),
  109. CLK_PERI_1S(DEV_NAME_PWM, 0, CLK_ID_PWM_0,
  110. PHY_BASEADDR_CLKGEN13, (I_PLL_0_2)),
  111. CLK_PERI_1S(DEV_NAME_PWM, 1, CLK_ID_PWM_1,
  112. PHY_BASEADDR_CLKGEN3, (I_PLL_0_2)),
  113. CLK_PERI_1S(DEV_NAME_PWM, 2, CLK_ID_PWM_2,
  114. PHY_BASEADDR_CLKGEN4, (I_PLL_0_2)),
  115. CLK_PERI_1S(DEV_NAME_PWM, 3, CLK_ID_PWM_3,
  116. PHY_BASEADDR_CLKGEN5, (I_PLL_0_2)),
  117. CLK_PERI_1S(DEV_NAME_I2C, 0, CLK_ID_I2C_0,
  118. PHY_BASEADDR_CLKGEN6, (I_GATE_PCLK)),
  119. CLK_PERI_1S(DEV_NAME_I2C, 1, CLK_ID_I2C_1,
  120. PHY_BASEADDR_CLKGEN7, (I_GATE_PCLK)),
  121. CLK_PERI_1S(DEV_NAME_I2C, 2, CLK_ID_I2C_2,
  122. PHY_BASEADDR_CLKGEN8, (I_GATE_PCLK)),
  123. CLK_PERI_2S(DEV_NAME_GMAC, 0, CLK_ID_GMAC,
  124. PHY_BASEADDR_CLKGEN10,
  125. (I_PLL_0_3 | I_EXTCLK1 | I_EXTCLK1_FORCE),
  126. (I_CLKnOUT)),
  127. CLK_PERI_2S(DEV_NAME_I2S, 0, CLK_ID_I2S_0,
  128. PHY_BASEADDR_CLKGEN15, (I_PLL_0_3 | I_EXTCLK1),
  129. (I_CLKnOUT)),
  130. CLK_PERI_2S(DEV_NAME_I2S, 1, CLK_ID_I2S_1,
  131. PHY_BASEADDR_CLKGEN16, (I_PLL_0_3 | I_EXTCLK1),
  132. (I_CLKnOUT)),
  133. CLK_PERI_2S(DEV_NAME_I2S, 2, CLK_ID_I2S_2,
  134. PHY_BASEADDR_CLKGEN17, (I_PLL_0_3 | I_EXTCLK1),
  135. (I_CLKnOUT)),
  136. CLK_PERI_1S(DEV_NAME_SDHC, 0, CLK_ID_SDHC_0,
  137. PHY_BASEADDR_CLKGEN18, (I_PLL_0_2 | I_GATE_PCLK)),
  138. CLK_PERI_1S(DEV_NAME_SDHC, 1, CLK_ID_SDHC_1,
  139. PHY_BASEADDR_CLKGEN19, (I_PLL_0_2 | I_GATE_PCLK)),
  140. CLK_PERI_1S(DEV_NAME_SDHC, 2, CLK_ID_SDHC_2,
  141. PHY_BASEADDR_CLKGEN20, (I_PLL_0_2 | I_GATE_PCLK)),
  142. CLK_PERI_1S(DEV_NAME_SPI, 0, CLK_ID_SPI_0,
  143. PHY_BASEADDR_CLKGEN37, (I_PLL_0_2)),
  144. CLK_PERI_1S(DEV_NAME_SPI, 1, CLK_ID_SPI_1,
  145. PHY_BASEADDR_CLKGEN38, (I_PLL_0_2)),
  146. CLK_PERI_1S(DEV_NAME_SPI, 2, CLK_ID_SPI_2,
  147. PHY_BASEADDR_CLKGEN39, (I_PLL_0_2)),
  148. };
  149. #define CLK_PERI_NUM ((int)ARRAY_SIZE(clk_periphs))
  150. #define CLK_CORE_NUM ((int)ARRAY_SIZE(clk_core))
  151. #define CLK_DEVS_NUM (CLK_CORE_NUM + CLK_PERI_NUM)
  152. #define MAX_DIVIDER ((1 << 8) - 1) /* 256, align 2 */
  153. static struct clk_dev st_clk_devs[CLK_DEVS_NUM]
  154. __section(".data");
  155. #define clk_dev_get(n) ((struct clk_dev *)&st_clk_devs[n])
  156. #define clk_container(p) (container_of(p, struct clk_dev, clk))
  157. /*
  158. * Core frequencys
  159. */
  160. struct _core_hz_ {
  161. unsigned long pll[4]; /* PLL */
  162. unsigned long cpu_fclk, cpu_bclk; /* cpu */
  163. unsigned long mem_fclk, mem_dclk, mem_bclk, mem_pclk; /* ddr */
  164. unsigned long bus_bclk, bus_pclk; /* bus */
  165. #if defined(CONFIG_ARCH_S5P6818)
  166. unsigned long cci4_bclk, cci4_pclk; /* cci */
  167. #endif
  168. /* ip */
  169. unsigned long g3d_bclk;
  170. unsigned long coda_bclk, coda_pclk;
  171. #if defined(CONFIG_ARCH_S5P6818)
  172. unsigned long disp_bclk, disp_pclk;
  173. unsigned long hdmi_pclk;
  174. #endif
  175. };
  176. /*
  177. * Section ".data" must be used because BSS is not available before relocation,
  178. * in board_init_f(), respectively! I.e. global variables can not be used!
  179. */
  180. /* core clock */
  181. static struct _core_hz_ core_hz __section(".data");
  182. #define CORE_HZ_SIZE (sizeof(core_hz) / 4)
  183. /*
  184. * CLKGEN HW
  185. */
  186. static inline void clk_dev_bclk(void *base, int on)
  187. {
  188. struct clk_dev_map *reg = base;
  189. unsigned int val = readl(&reg->con_enb) & ~(0x3);
  190. val |= (on ? 3 : 0) & 0x3; /* always BCLK */
  191. writel(val, &reg->con_enb);
  192. }
  193. static inline void clk_dev_pclk(void *base, int on)
  194. {
  195. struct clk_dev_map *reg = base;
  196. unsigned int val = 0;
  197. if (!on)
  198. return;
  199. val = readl(&reg->con_enb) & ~(1 << 3);
  200. val |= (1 << 3);
  201. writel(val, &reg->con_enb);
  202. }
  203. static inline void clk_dev_rate(void *base, int step, int src, int div)
  204. {
  205. struct clk_dev_map *reg = base;
  206. unsigned int val = 0;
  207. val = readl(&reg->con_gen[step << 1]);
  208. val &= ~(0x07 << 2);
  209. val |= (src << 2); /* source */
  210. val &= ~(0xFF << 5);
  211. val |= (div - 1) << 5; /* divider */
  212. writel(val, &reg->con_gen[step << 1]);
  213. }
  214. static inline void clk_dev_inv(void *base, int step, int inv)
  215. {
  216. struct clk_dev_map *reg = base;
  217. unsigned int val = readl(&reg->con_gen[step << 1]) & ~(1 << 1);
  218. val |= (inv << 1);
  219. writel(val, &reg->con_gen[step << 1]);
  220. }
  221. static inline void clk_dev_enb(void *base, int on)
  222. {
  223. struct clk_dev_map *reg = base;
  224. unsigned int val = readl(&reg->con_enb) & ~(1 << 2);
  225. val |= ((on ? 1 : 0) << 2);
  226. writel(val, &reg->con_enb);
  227. }
  228. /*
  229. * CORE FREQUENCY
  230. *
  231. * PLL0 [P,M,S] ------- | | ----- [DIV0] --- CPU-G0
  232. * |M| ----- [DIV1] --- BCLK/PCLK
  233. * PLL1 [P,M,S] ------- | | ----- [DIV2] --- DDR
  234. * |U| ----- [DIV3] --- 3D
  235. * PLL2 [P,M,S,K]-------| | ----- [DIV4] --- CODA
  236. * |X| ----- [DIV5] --- DISPLAY
  237. * PLL3 [P,M,S,K]-------| | ----- [DIV6] --- HDMI
  238. * | | ----- [DIV7] --- CPU-G1
  239. * | | ----- [DIV8] --- CCI-400(FASTBUS)
  240. *
  241. */
  242. struct nx_clkpwr_registerset {
  243. u32 clkmodereg0; /* 0x000 : Clock Mode Register0 */
  244. u32 __reserved0; /* 0x004 */
  245. u32 pllsetreg[4]; /* 0x008 ~ 0x014 : PLL Setting Register */
  246. u32 __reserved1[2]; /* 0x018 ~ 0x01C */
  247. u32 dvoreg[9]; /* 0x020 ~ 0x040 : Divider Setting Register */
  248. u32 __Reserved2; /* 0x044 */
  249. u32 pllsetreg_sscg[6]; /* 0x048 ~ 0x05C */
  250. u32 __reserved3[8]; /* 0x060 ~ 0x07C */
  251. u8 __reserved4[0x200 - 0x80]; /* padding (0x80 ~ 0x1FF) */
  252. u32 gpiowakeupriseenb; /* 0x200 : GPIO Rising Edge Detect En. Reg. */
  253. u32 gpiowakeupfallenb; /* 0x204 : GPIO Falling Edge Detect En. Reg. */
  254. u32 gpiorstenb; /* 0x208 : GPIO Reset Enable Register */
  255. u32 gpiowakeupenb; /* 0x20C : GPIO Wakeup Source Enable */
  256. u32 gpiointenb; /* 0x210 : Interrupt Enable Register */
  257. u32 gpiointpend; /* 0x214 : Interrupt Pend Register */
  258. u32 resetstatus; /* 0x218 : Reset Status Register */
  259. u32 intenable; /* 0x21C : Interrupt Enable Register */
  260. u32 intpend; /* 0x220 : Interrupt Pend Register */
  261. u32 pwrcont; /* 0x224 : Power Control Register */
  262. u32 pwrmode; /* 0x228 : Power Mode Register */
  263. u32 __reserved5; /* 0x22C : Reserved Region */
  264. u32 scratch[3]; /* 0x230 ~ 0x238 : Scratch Register */
  265. u32 sysrstconfig; /* 0x23C : System Reset Configuration Reg. */
  266. u8 __reserved6[0x2A0 - 0x240]; /* padding (0x240 ~ 0x29F) */
  267. u32 cpupowerdownreq; /* 0x2A0 : CPU Power Down Request Register */
  268. u32 cpupoweronreq; /* 0x2A4 : CPU Power On Request Register */
  269. u32 cpuresetmode; /* 0x2A8 : CPU Reset Mode Register */
  270. u32 cpuwarmresetreq; /* 0x2AC : CPU Warm Reset Request Register */
  271. u32 __reserved7; /* 0x2B0 */
  272. u32 cpustatus; /* 0x2B4 : CPU Status Register */
  273. u8 __reserved8[0x400 - 0x2B8]; /* padding (0x2B8 ~ 0x33F) */
  274. };
  275. static struct nx_clkpwr_registerset * const clkpwr =
  276. (struct nx_clkpwr_registerset *)PHY_BASEADDR_CLKPWR;
  277. #define getquotient(v, d) ((v) / (d))
  278. #define DIV_CPUG0 0
  279. #define DIV_BUS 1
  280. #define DIV_MEM 2
  281. #define DIV_G3D 3
  282. #define DIV_CODA 4
  283. #if defined(CONFIG_ARCH_S5P6818)
  284. #define DIV_DISP 5
  285. #define DIV_HDMI 6
  286. #define DIV_CPUG1 7
  287. #define DIV_CCI4 8
  288. #endif
  289. #define DVO0 3
  290. #define DVO1 9
  291. #define DVO2 15
  292. #define DVO3 21
  293. static unsigned int pll_rate(unsigned int plln, unsigned int xtal)
  294. {
  295. unsigned int val, val1, nP, nM, nS, nK;
  296. unsigned int temp = 0;
  297. val = clkpwr->pllsetreg[plln];
  298. val1 = clkpwr->pllsetreg_sscg[plln];
  299. xtal /= 1000; /* Unit Khz */
  300. nP = (val >> 18) & 0x03F;
  301. nM = (val >> 8) & 0x3FF;
  302. nS = (val >> 0) & 0x0FF;
  303. nK = (val1 >> 16) & 0xFFFF;
  304. if (plln > 1 && nK) {
  305. temp = (unsigned int)(getquotient((getquotient((nK * 1000),
  306. 65536) * xtal), nP) >> nS);
  307. }
  308. temp = (unsigned int)((getquotient((nM * xtal), nP) >> nS) * 1000)
  309. + temp;
  310. return temp;
  311. }
  312. static unsigned int pll_dvo(int dvo)
  313. {
  314. unsigned int val;
  315. val = (clkpwr->dvoreg[dvo] & 0x7);
  316. return val;
  317. }
  318. static unsigned int pll_div(int dvo)
  319. {
  320. unsigned int val = clkpwr->dvoreg[dvo];
  321. return ((((val >> DVO3) & 0x3F) + 1) << 24) |
  322. ((((val >> DVO2) & 0x3F) + 1) << 16) |
  323. ((((val >> DVO1) & 0x3F) + 1) << 8) |
  324. ((((val >> DVO0) & 0x3F) + 1) << 0);
  325. }
  326. #define PLLN_RATE(n) (pll_rate(n, CONFIG_SYS_PLLFIN)) /* 0~ 3 */
  327. #define CPU_FCLK_RATE(n) (pll_rate(pll_dvo(n), CONFIG_SYS_PLLFIN) / \
  328. ((pll_div(n) >> 0) & 0x3F))
  329. #define CPU_BCLK_RATE(n) (pll_rate(pll_dvo(n), CONFIG_SYS_PLLFIN) / \
  330. ((pll_div(n) >> 0) & 0x3F) / \
  331. ((pll_div(n) >> 8) & 0x3F))
  332. #define MEM_FCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
  333. ((pll_div(DIV_MEM) >> 0) & 0x3F) / \
  334. ((pll_div(DIV_MEM) >> 8) & 0x3F))
  335. #define MEM_DCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
  336. ((pll_div(DIV_MEM) >> 0) & 0x3F))
  337. #define MEM_BCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
  338. ((pll_div(DIV_MEM) >> 0) & 0x3F) / \
  339. ((pll_div(DIV_MEM) >> 8) & 0x3F) / \
  340. ((pll_div(DIV_MEM) >> 16) & 0x3F))
  341. #define MEM_PCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
  342. ((pll_div(DIV_MEM) >> 0) & 0x3F) / \
  343. ((pll_div(DIV_MEM) >> 8) & 0x3F) / \
  344. ((pll_div(DIV_MEM) >> 16) & 0x3F) / \
  345. ((pll_div(DIV_MEM) >> 24) & 0x3F))
  346. #define BUS_BCLK_RATE() (pll_rate(pll_dvo(DIV_BUS), CONFIG_SYS_PLLFIN) / \
  347. ((pll_div(DIV_BUS) >> 0) & 0x3F))
  348. #define BUS_PCLK_RATE() (pll_rate(pll_dvo(DIV_BUS), CONFIG_SYS_PLLFIN) / \
  349. ((pll_div(DIV_BUS) >> 0) & 0x3F) / \
  350. ((pll_div(DIV_BUS) >> 8) & 0x3F))
  351. #define G3D_BCLK_RATE() (pll_rate(pll_dvo(DIV_G3D), CONFIG_SYS_PLLFIN) / \
  352. ((pll_div(DIV_G3D) >> 0) & 0x3F))
  353. #define MPG_BCLK_RATE() (pll_rate(pll_dvo(DIV_CODA), CONFIG_SYS_PLLFIN) / \
  354. ((pll_div(DIV_CODA) >> 0) & 0x3F))
  355. #define MPG_PCLK_RATE() (pll_rate(pll_dvo(DIV_CODA), CONFIG_SYS_PLLFIN) / \
  356. ((pll_div(DIV_CODA) >> 0) & 0x3F) / \
  357. ((pll_div(DIV_CODA) >> 8) & 0x3F))
  358. #if defined(CONFIG_ARCH_S5P6818)
  359. #define DISP_BCLK_RATE() (pll_rate(pll_dvo(DIV_DISP), CONFIG_SYS_PLLFIN) / \
  360. ((pll_div(DIV_DISP) >> 0) & 0x3F))
  361. #define DISP_PCLK_RATE() (pll_rate(pll_dvo(DIV_DISP), CONFIG_SYS_PLLFIN) / \
  362. ((pll_div(DIV_DISP) >> 0) & 0x3F) / \
  363. ((pll_div(DIV_DISP) >> 8) & 0x3F))
  364. #define HDMI_PCLK_RATE() (pll_rate(pll_dvo(DIV_HDMI), CONFIG_SYS_PLLFIN) / \
  365. ((pll_div(DIV_HDMI) >> 0) & 0x3F))
  366. #define CCI4_BCLK_RATE() (pll_rate(pll_dvo(DIV_CCI4), CONFIG_SYS_PLLFIN) / \
  367. ((pll_div(DIV_CCI4) >> 0) & 0x3F))
  368. #define CCI4_PCLK_RATE() (pll_rate(pll_dvo(DIV_CCI4), CONFIG_SYS_PLLFIN) / \
  369. ((pll_div(DIV_CCI4) >> 0) & 0x3F) / \
  370. ((pll_div(DIV_CCI4) >> 8) & 0x3F))
  371. #endif
  372. static void core_update_rate(int type)
  373. {
  374. switch (type) {
  375. case 0:
  376. core_hz.pll[0] = PLLN_RATE(0); break;
  377. case 1:
  378. core_hz.pll[1] = PLLN_RATE(1); break;
  379. case 2:
  380. core_hz.pll[2] = PLLN_RATE(2); break;
  381. case 3:
  382. core_hz.pll[3] = PLLN_RATE(3); break;
  383. case 4:
  384. core_hz.cpu_fclk = CPU_FCLK_RATE(DIV_CPUG0); break;
  385. case 5:
  386. core_hz.mem_fclk = MEM_FCLK_RATE(); break;
  387. case 6:
  388. core_hz.bus_bclk = BUS_BCLK_RATE(); break;
  389. case 7:
  390. core_hz.bus_pclk = BUS_PCLK_RATE(); break;
  391. case 8:
  392. core_hz.cpu_bclk = CPU_BCLK_RATE(DIV_CPUG0); break;
  393. case 9:
  394. core_hz.mem_dclk = MEM_DCLK_RATE(); break;
  395. case 10:
  396. core_hz.mem_bclk = MEM_BCLK_RATE(); break;
  397. case 11:
  398. core_hz.mem_pclk = MEM_PCLK_RATE(); break;
  399. case 12:
  400. core_hz.g3d_bclk = G3D_BCLK_RATE(); break;
  401. case 13:
  402. core_hz.coda_bclk = MPG_BCLK_RATE(); break;
  403. case 14:
  404. core_hz.coda_pclk = MPG_PCLK_RATE(); break;
  405. #if defined(CONFIG_ARCH_S5P6818)
  406. case 15:
  407. core_hz.disp_bclk = DISP_BCLK_RATE(); break;
  408. case 16:
  409. core_hz.disp_pclk = DISP_PCLK_RATE(); break;
  410. case 17:
  411. core_hz.hdmi_pclk = HDMI_PCLK_RATE(); break;
  412. case 18:
  413. core_hz.cci4_bclk = CCI4_BCLK_RATE(); break;
  414. case 19:
  415. core_hz.cci4_pclk = CCI4_PCLK_RATE(); break;
  416. #endif
  417. };
  418. }
  419. static unsigned long core_get_rate(int type)
  420. {
  421. unsigned long rate = 0;
  422. switch (type) {
  423. case 0:
  424. rate = core_hz.pll[0]; break;
  425. case 1:
  426. rate = core_hz.pll[1]; break;
  427. case 2:
  428. rate = core_hz.pll[2]; break;
  429. case 3:
  430. rate = core_hz.pll[3]; break;
  431. case 4:
  432. rate = core_hz.cpu_fclk; break;
  433. case 5:
  434. rate = core_hz.mem_fclk; break;
  435. case 6:
  436. rate = core_hz.bus_bclk; break;
  437. case 7:
  438. rate = core_hz.bus_pclk; break;
  439. case 8:
  440. rate = core_hz.cpu_bclk; break;
  441. case 9:
  442. rate = core_hz.mem_dclk; break;
  443. case 10:
  444. rate = core_hz.mem_bclk; break;
  445. case 11:
  446. rate = core_hz.mem_pclk; break;
  447. case 12:
  448. rate = core_hz.g3d_bclk; break;
  449. case 13:
  450. rate = core_hz.coda_bclk; break;
  451. case 14:
  452. rate = core_hz.coda_pclk; break;
  453. #if defined(CONFIG_ARCH_S5P6818)
  454. case 15:
  455. rate = core_hz.disp_bclk; break;
  456. case 16:
  457. rate = core_hz.disp_pclk; break;
  458. case 17:
  459. rate = core_hz.hdmi_pclk; break;
  460. case 18:
  461. rate = core_hz.cci4_bclk; break;
  462. case 19:
  463. rate = core_hz.cci4_pclk; break;
  464. #endif
  465. default:
  466. printf("unknown core clock type %d ...\n", type);
  467. break;
  468. };
  469. return rate;
  470. }
  471. static long core_set_rate(struct clk *clk, long rate)
  472. {
  473. return clk->rate;
  474. }
  475. static void core_rate_init(void)
  476. {
  477. int i;
  478. for (i = 0; i < CORE_HZ_SIZE; i++)
  479. core_update_rate(i);
  480. }
  481. /*
  482. * Clock Interfaces
  483. */
  484. static inline long clk_divide(long rate, long request,
  485. int align, int *divide)
  486. {
  487. int div = (rate / request);
  488. int max = MAX_DIVIDER & ~(align - 1);
  489. int adv = (div & ~(align - 1)) + align;
  490. long ret;
  491. if (!div) {
  492. if (divide)
  493. *divide = 1;
  494. return rate;
  495. }
  496. if (div != 1)
  497. div &= ~(align - 1);
  498. if (div != adv && abs(request - rate / div) > abs(request - rate / adv))
  499. div = adv;
  500. div = (div > max ? max : div);
  501. if (divide)
  502. *divide = div;
  503. ret = rate / div;
  504. return ret;
  505. }
  506. void clk_put(struct clk *clk)
  507. {
  508. }
  509. struct clk *clk_get(const char *id)
  510. {
  511. struct clk_dev *cdev = clk_dev_get(0);
  512. struct clk *clk = NULL;
  513. const char *str = NULL, *c = NULL;
  514. int i, devid;
  515. if (id)
  516. str = id;
  517. for (i = 0; i < CLK_DEVS_NUM; i++, cdev++) {
  518. if (!cdev->name)
  519. continue;
  520. if (!strncmp(cdev->name, str, strlen(cdev->name))) {
  521. c = strrchr((const char *)str, (int)'.');
  522. if (!c || !cdev->peri)
  523. break;
  524. devid = dectoul(++c, NULL);
  525. if (cdev->peri->dev_id == devid)
  526. break;
  527. }
  528. }
  529. if (i < CLK_DEVS_NUM)
  530. clk = &cdev->clk;
  531. else
  532. clk = &(clk_dev_get(7))->clk; /* pclk */
  533. return clk ? clk : ERR_PTR(-ENOENT);
  534. }
  535. long clk_round_rate(struct clk *clk, unsigned long rate)
  536. {
  537. struct clk_dev *pll = NULL, *cdev = clk_container(clk);
  538. struct clk_dev_peri *peri = cdev->peri;
  539. unsigned long request = rate, rate_hz = 0;
  540. unsigned int mask;
  541. int step, div[2] = { 0, };
  542. int i, n, clk2 = 0;
  543. int start_src = 0, max_src = I_CLOCK_NUM;
  544. short s1 = 0, s2 = 0, d1 = 0, d2 = 0;
  545. if (!peri)
  546. return core_set_rate(clk, rate);
  547. step = peri->clk_step;
  548. mask = peri->in_mask;
  549. debug("clk: %s.%d request = %ld [input=0x%x]\n", peri->dev_name,
  550. peri->dev_id, rate, mask);
  551. if (!(I_CLOCK_MASK & mask)) {
  552. if (I_PCLK_MASK & mask)
  553. return core_get_rate(CORECLK_ID_PCLK);
  554. else if (I_BCLK_MASK & mask)
  555. return core_get_rate(CORECLK_ID_BCLK);
  556. else
  557. return clk->rate;
  558. }
  559. next:
  560. if (peri->in_mask & I_EXTCLK1_FORCE) {
  561. start_src = 4; max_src = 5;
  562. }
  563. for (n = start_src ; max_src > n; n++) {
  564. if (!(((mask & I_CLOCK_MASK) >> n) & 0x1))
  565. continue;
  566. if (n == I_EXT1_BIT) {
  567. rate = peri->in_extclk_1;
  568. } else if (n == I_EXT2_BIT) {
  569. rate = peri->in_extclk_2;
  570. } else {
  571. pll = clk_dev_get(n);
  572. rate = pll->clk.rate;
  573. }
  574. if (!rate)
  575. continue;
  576. for (i = 0; step > i ; i++)
  577. rate = clk_divide(rate, request, 2, &div[i]);
  578. if (rate_hz && (abs(rate - request) > abs(rate_hz - request)))
  579. continue;
  580. debug("clk: %s.%d, pll.%d[%lu] request[%ld] calc[%ld]\n",
  581. peri->dev_name, peri->dev_id, n, pll->clk.rate,
  582. request, rate);
  583. if (clk2) {
  584. s1 = -1, d1 = -1; /* not use */
  585. s2 = n, d2 = div[0];
  586. } else {
  587. s1 = n, d1 = div[0];
  588. s2 = I_CLKn_BIT, d2 = div[1];
  589. }
  590. rate_hz = rate;
  591. }
  592. /* search 2th clock from input */
  593. if (!clk2 && abs(rate_hz - request) &&
  594. peri->in_mask1 & ((1 << I_CLOCK_NUM) - 1)) {
  595. clk2 = 1;
  596. mask = peri->in_mask1;
  597. step = 1;
  598. goto next;
  599. }
  600. if (peri->in_mask & I_EXTCLK1_FORCE) {
  601. if (s1 == 0) {
  602. s1 = 4; s2 = 7;
  603. d1 = 1; d2 = 1;
  604. }
  605. }
  606. peri->div_src_0 = s1, peri->div_val_0 = d1;
  607. peri->div_src_1 = s2, peri->div_val_1 = d2;
  608. clk->rate = rate_hz;
  609. debug("clk: %s.%d, step[%d] src[%d,%d] %ld", peri->dev_name,
  610. peri->dev_id, peri->clk_step, peri->div_src_0, peri->div_src_1,
  611. rate);
  612. debug("/(div0: %d * div1: %d) = %ld, %ld diff (%ld)\n",
  613. peri->div_val_0, peri->div_val_1, rate_hz, request,
  614. abs(rate_hz - request));
  615. return clk->rate;
  616. }
  617. unsigned long clk_get_rate(struct clk *clk)
  618. {
  619. struct clk_dev *cdev = clk_container(clk);
  620. if (cdev->link)
  621. clk = cdev->link;
  622. return clk->rate;
  623. }
  624. int clk_set_rate(struct clk *clk, unsigned long rate)
  625. {
  626. struct clk_dev *cdev = clk_container(clk);
  627. struct clk_dev_peri *peri = cdev->peri;
  628. int i;
  629. if (!peri)
  630. return core_set_rate(clk, rate);
  631. clk_round_rate(clk, rate);
  632. for (i = 0; peri->clk_step > i ; i++) {
  633. int s = (i == 0 ? peri->div_src_0 : peri->div_src_1);
  634. int d = (i == 0 ? peri->div_val_0 : peri->div_val_1);
  635. if (-1 == s)
  636. continue;
  637. clk_dev_rate(peri->base, i, s, d);
  638. debug("clk: %s.%d (%p) set_rate [%d] src[%d] div[%d]\n",
  639. peri->dev_name, peri->dev_id, peri->base, i, s, d);
  640. }
  641. return clk->rate;
  642. }
  643. int clk_enable(struct clk *clk)
  644. {
  645. struct clk_dev *cdev = clk_container(clk);
  646. struct clk_dev_peri *peri = cdev->peri;
  647. int i = 0, inv = 0;
  648. if (!peri)
  649. return 0;
  650. debug("clk: %s.%d enable (BCLK=%s, PCLK=%s)\n", peri->dev_name,
  651. peri->dev_id, I_GATE_BCLK & peri->in_mask ? "ON" : "PASS",
  652. I_GATE_PCLK & peri->in_mask ? "ON" : "PASS");
  653. if (!(I_CLOCK_MASK & peri->in_mask)) {
  654. /* Gated BCLK/PCLK enable */
  655. if (I_GATE_BCLK & peri->in_mask)
  656. clk_dev_bclk(peri->base, 1);
  657. if (I_GATE_PCLK & peri->in_mask)
  658. clk_dev_pclk(peri->base, 1);
  659. return 0;
  660. }
  661. /* invert */
  662. inv = peri->invert_0;
  663. for (; peri->clk_step > i; i++, inv = peri->invert_1)
  664. clk_dev_inv(peri->base, i, inv);
  665. /* Gated BCLK/PCLK enable */
  666. if (I_GATE_BCLK & peri->in_mask)
  667. clk_dev_bclk(peri->base, 1);
  668. if (I_GATE_PCLK & peri->in_mask)
  669. clk_dev_pclk(peri->base, 1);
  670. /* restore clock rate */
  671. for (i = 0; peri->clk_step > i ; i++) {
  672. int s = (i == 0 ? peri->div_src_0 : peri->div_src_1);
  673. int d = (i == 0 ? peri->div_val_0 : peri->div_val_1);
  674. if (s == -1)
  675. continue;
  676. clk_dev_rate(peri->base, i, s, d);
  677. }
  678. clk_dev_enb(peri->base, 1);
  679. return 0;
  680. }
  681. void clk_disable(struct clk *clk)
  682. {
  683. struct clk_dev *cdev = clk_container(clk);
  684. struct clk_dev_peri *peri = cdev->peri;
  685. if (!peri)
  686. return;
  687. debug("clk: %s.%d disable\n", peri->dev_name, peri->dev_id);
  688. if (!(I_CLOCK_MASK & peri->in_mask)) {
  689. /* Gated BCLK/PCLK disable */
  690. if (I_GATE_BCLK & peri->in_mask)
  691. clk_dev_bclk(peri->base, 0);
  692. if (I_GATE_PCLK & peri->in_mask)
  693. clk_dev_pclk(peri->base, 0);
  694. return;
  695. }
  696. clk_dev_rate(peri->base, 0, 7, 256); /* for power save */
  697. clk_dev_enb(peri->base, 0);
  698. /* Gated BCLK/PCLK disable */
  699. if (I_GATE_BCLK & peri->in_mask)
  700. clk_dev_bclk(peri->base, 0);
  701. if (I_GATE_PCLK & peri->in_mask)
  702. clk_dev_pclk(peri->base, 0);
  703. }
  704. /*
  705. * Core clocks APIs
  706. */
  707. void __init clk_init(void)
  708. {
  709. struct clk_dev *cdev = st_clk_devs;
  710. struct clk_dev_peri *peri = clk_periphs;
  711. struct clk *clk = NULL;
  712. int i = 0;
  713. memset(cdev, 0, sizeof(st_clk_devs));
  714. core_rate_init();
  715. for (i = 0; (CLK_CORE_NUM + CLK_PERI_NUM) > i; i++, cdev++) {
  716. if (i < CLK_CORE_NUM) {
  717. cdev->name = clk_core[i];
  718. clk = &cdev->clk;
  719. clk->rate = core_get_rate(i);
  720. continue;
  721. }
  722. peri = &clk_periphs[i - CLK_CORE_NUM];
  723. peri->base = (void *)peri->base;
  724. cdev->peri = peri;
  725. cdev->name = peri->dev_name;
  726. if (!(I_CLOCK_MASK & peri->in_mask)) {
  727. if (I_BCLK_MASK & peri->in_mask)
  728. cdev->clk.rate = core_get_rate(CORECLK_ID_BCLK);
  729. if (I_PCLK_MASK & peri->in_mask)
  730. cdev->clk.rate = core_get_rate(CORECLK_ID_PCLK);
  731. }
  732. /* prevent uart clock disable for low step debug message */
  733. #ifndef CONFIG_DEBUG_NX_UART
  734. if (peri->dev_name) {
  735. #ifdef CONFIG_BACKLIGHT_PWM
  736. if (!strcmp(peri->dev_name, DEV_NAME_PWM))
  737. continue;
  738. #endif
  739. }
  740. #endif
  741. }
  742. debug("CPU : Clock Generator= %d EA, ", CLK_DEVS_NUM);
  743. }