snvs_security_sc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019-2020 NXP.
  4. */
  5. /*
  6. * Configuration of the Tamper pins in different mode:
  7. * - default (no tamper pins): _default_
  8. * - passive mode expecting VCC on the line: "_passive_vcc_"
  9. * - passive mode expecting VCC on the line: "_passive_gnd_"
  10. * - active mode: "_active_"
  11. */
  12. #include <command.h>
  13. #include <log.h>
  14. #include <stddef.h>
  15. #include <common.h>
  16. #include <asm/arch/sci/sci.h>
  17. #include <asm/arch-imx8/imx8-pins.h>
  18. #include <asm/arch-imx8/snvs_security_sc.h>
  19. #include <asm/global_data.h>
  20. /* Access to gd */
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define SC_WRITE_CONF 1
  23. #define PGD_HEX_VALUE 0x41736166
  24. #define SRTC_EN 0x1
  25. #define DP_EN BIT(5)
  26. struct snvs_security_sc_conf {
  27. struct snvs_hp_conf {
  28. u32 lock; /* HPLR - HP Lock */
  29. u32 __cmd; /* HPCOMR - HP Command */
  30. u32 __ctl; /* HPCR - HP Control */
  31. u32 secvio_intcfg; /* HPSICR - Security Violation Int
  32. * Config
  33. */
  34. u32 secvio_ctl; /* HPSVCR - Security Violation Control*/
  35. u32 status; /* HPSR - HP Status */
  36. u32 secvio_status; /* HPSVSR - Security Violation Status */
  37. u32 __ha_counteriv; /* High Assurance Counter IV */
  38. u32 __ha_counter; /* High Assurance Counter */
  39. u32 __rtc_msb; /* Real Time Clock/Counter MSB */
  40. u32 __rtc_lsb; /* Real Time Counter LSB */
  41. u32 __time_alarm_msb; /* Time Alarm MSB */
  42. u32 __time_alarm_lsb; /* Time Alarm LSB */
  43. } hp;
  44. struct snvs_lp_conf {
  45. u32 lock;
  46. u32 __ctl;
  47. u32 __mstr_key_ctl; /* Master Key Control */
  48. u32 secvio_ctl; /* Security Violation Control */
  49. u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration*/
  50. u32 tamper_det_cfg; /* Tamper Detectors Configuration */
  51. u32 status;
  52. u32 __srtc_msb; /* Secure Real Time Clock/Counter MSB */
  53. u32 __srtc_lsb; /* Secure Real Time Clock/Counter LSB */
  54. u32 __time_alarm; /* Time Alarm */
  55. u32 __smc_msb; /* Secure Monotonic Counter MSB */
  56. u32 __smc_lsb; /* Secure Monotonic Counter LSB */
  57. u32 __pwr_glitch_det; /* Power Glitch Detector */
  58. u32 __gen_purpose;
  59. u8 __zmk[32]; /* Zeroizable Master Key */
  60. u32 __rsvd0;
  61. u32 __gen_purposes[4]; /* gp0_30 to gp0_33 */
  62. u32 tamper_det_cfg2; /* Tamper Detectors Configuration2 */
  63. u32 tamper_det_status; /* Tamper Detectors status */
  64. u32 tamper_filt1_cfg; /* Tamper Glitch Filter1 Configuration*/
  65. u32 tamper_filt2_cfg; /* Tamper Glitch Filter2 Configuration*/
  66. u32 __rsvd1[4];
  67. u32 act_tamper1_cfg; /* Active Tamper1 Configuration */
  68. u32 act_tamper2_cfg; /* Active Tamper2 Configuration */
  69. u32 act_tamper3_cfg; /* Active Tamper3 Configuration */
  70. u32 act_tamper4_cfg; /* Active Tamper4 Configuration */
  71. u32 act_tamper5_cfg; /* Active Tamper5 Configuration */
  72. u32 __rsvd2[3];
  73. u32 act_tamper_ctl; /* Active Tamper Control */
  74. u32 act_tamper_clk_ctl; /* Active Tamper Clock Control */
  75. u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */
  76. u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */
  77. } lp;
  78. };
  79. static struct snvs_security_sc_conf snvs_default_config = {
  80. .hp = {
  81. .lock = 0x1f0703ff,
  82. .secvio_ctl = 0x3000007f,
  83. },
  84. .lp = {
  85. .lock = 0x1f0003ff,
  86. .secvio_ctl = 0x36,
  87. .tamper_filt_cfg = 0,
  88. .tamper_det_cfg = 0x76, /* analogic tampers
  89. * + rollover tampers
  90. */
  91. .tamper_det_cfg2 = 0,
  92. .tamper_filt1_cfg = 0,
  93. .tamper_filt2_cfg = 0,
  94. .act_tamper1_cfg = 0,
  95. .act_tamper2_cfg = 0,
  96. .act_tamper3_cfg = 0,
  97. .act_tamper4_cfg = 0,
  98. .act_tamper5_cfg = 0,
  99. .act_tamper_ctl = 0,
  100. .act_tamper_clk_ctl = 0,
  101. .act_tamper_routing_ctl1 = 0,
  102. .act_tamper_routing_ctl2 = 0,
  103. }
  104. };
  105. static struct snvs_security_sc_conf snvs_passive_vcc_config = {
  106. .hp = {
  107. .lock = 0x1f0703ff,
  108. .secvio_ctl = 0x3000007f,
  109. },
  110. .lp = {
  111. .lock = 0x1f0003ff,
  112. .secvio_ctl = 0x36,
  113. .tamper_filt_cfg = 0,
  114. .tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
  115. * + analogic tampers
  116. * + rollover tampers
  117. */
  118. .tamper_det_cfg2 = 0,
  119. .tamper_filt1_cfg = 0,
  120. .tamper_filt2_cfg = 0,
  121. .act_tamper1_cfg = 0,
  122. .act_tamper2_cfg = 0,
  123. .act_tamper3_cfg = 0,
  124. .act_tamper4_cfg = 0,
  125. .act_tamper5_cfg = 0,
  126. .act_tamper_ctl = 0,
  127. .act_tamper_clk_ctl = 0,
  128. .act_tamper_routing_ctl1 = 0,
  129. .act_tamper_routing_ctl2 = 0,
  130. }
  131. };
  132. static struct snvs_security_sc_conf snvs_passive_gnd_config = {
  133. .hp = {
  134. .lock = 0x1f0703ff,
  135. .secvio_ctl = 0x3000007f,
  136. },
  137. .lp = {
  138. .lock = 0x1f0003ff,
  139. .secvio_ctl = 0x36,
  140. .tamper_filt_cfg = 0,
  141. .tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
  142. * + analogic tampers
  143. * + rollover tampers
  144. */
  145. .tamper_det_cfg2 = 0,
  146. .tamper_filt1_cfg = 0,
  147. .tamper_filt2_cfg = 0,
  148. .act_tamper1_cfg = 0,
  149. .act_tamper2_cfg = 0,
  150. .act_tamper3_cfg = 0,
  151. .act_tamper4_cfg = 0,
  152. .act_tamper5_cfg = 0,
  153. .act_tamper_ctl = 0,
  154. .act_tamper_clk_ctl = 0,
  155. .act_tamper_routing_ctl1 = 0,
  156. .act_tamper_routing_ctl2 = 0,
  157. }
  158. };
  159. static struct snvs_security_sc_conf snvs_active_config = {
  160. .hp = {
  161. .lock = 0x1f0703ff,
  162. .secvio_ctl = 0x3000007f,
  163. },
  164. .lp = {
  165. .lock = 0x1f0003ff,
  166. .secvio_ctl = 0x36,
  167. .tamper_filt_cfg = 0x00800000, /* Enable filtering */
  168. .tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
  169. * + rollover tampers
  170. */
  171. .tamper_det_cfg2 = 0,
  172. .tamper_filt1_cfg = 0,
  173. .tamper_filt2_cfg = 0,
  174. .act_tamper1_cfg = 0x84001111,
  175. .act_tamper2_cfg = 0,
  176. .act_tamper3_cfg = 0,
  177. .act_tamper4_cfg = 0,
  178. .act_tamper5_cfg = 0,
  179. .act_tamper_ctl = 0x00010001,
  180. .act_tamper_clk_ctl = 0,
  181. .act_tamper_routing_ctl1 = 0x1,
  182. .act_tamper_routing_ctl2 = 0,
  183. }
  184. };
  185. static struct snvs_security_sc_conf *get_snvs_config(void)
  186. {
  187. return &snvs_default_config;
  188. }
  189. struct snvs_dgo_conf {
  190. u32 tamper_offset_ctl;
  191. u32 tamper_pull_ctl;
  192. u32 tamper_ana_test_ctl;
  193. u32 tamper_sensor_trim_ctl;
  194. u32 tamper_misc_ctl;
  195. u32 tamper_core_volt_mon_ctl;
  196. };
  197. static struct snvs_dgo_conf snvs_dgo_default_config = {
  198. .tamper_misc_ctl = 0x80000000, /* Lock the DGO */
  199. };
  200. static struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
  201. .tamper_misc_ctl = 0x80000000, /* Lock the DGO */
  202. .tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
  203. .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
  204. };
  205. static struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
  206. .tamper_misc_ctl = 0x80000000, /* Lock the DGO */
  207. .tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
  208. .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
  209. };
  210. static struct snvs_dgo_conf snvs_dgo_active_config = {
  211. .tamper_misc_ctl = 0x80000000, /* Lock the DGO */
  212. .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
  213. };
  214. static struct snvs_dgo_conf *get_snvs_dgo_config(void)
  215. {
  216. return &snvs_dgo_default_config;
  217. }
  218. struct tamper_pin_cfg {
  219. u32 pad;
  220. u32 mux_conf;
  221. };
  222. static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
  223. {SC_P_CSI_D00, 0}, /* Tamp_Out0 */
  224. {SC_P_CSI_D01, 0}, /* Tamp_Out1 */
  225. {SC_P_CSI_D02, 0}, /* Tamp_Out2 */
  226. {SC_P_CSI_D03, 0}, /* Tamp_Out3 */
  227. {SC_P_CSI_D04, 0}, /* Tamp_Out4 */
  228. {SC_P_CSI_D05, 0}, /* Tamp_In0 */
  229. {SC_P_CSI_D06, 0}, /* Tamp_In1 */
  230. {SC_P_CSI_D07, 0}, /* Tamp_In2 */
  231. {SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */
  232. {SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */
  233. };
  234. static struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
  235. {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
  236. };
  237. static struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
  238. {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
  239. };
  240. static struct tamper_pin_cfg tamper_pin_list_active_config[] = {
  241. {SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */
  242. {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
  243. };
  244. #define TAMPER_PIN_LIST_CHOSEN tamper_pin_list_default_config
  245. static struct tamper_pin_cfg *get_tamper_pin_cfg_list(u32 *size)
  246. {
  247. *size = sizeof(TAMPER_PIN_LIST_CHOSEN) /
  248. sizeof(TAMPER_PIN_LIST_CHOSEN[0]);
  249. return TAMPER_PIN_LIST_CHOSEN;
  250. }
  251. #define SC_CONF_OFFSET_OF(_field) \
  252. (offsetof(struct snvs_security_sc_conf, _field))
  253. static u32 ptr_value(u32 *_p)
  254. {
  255. return (_p) ? *_p : 0xdeadbeef;
  256. }
  257. static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
  258. u32 *_p3, u32 *_p4, u32 *_p5,
  259. u32 _cnt)
  260. {
  261. int scierr = 0;
  262. u32 d1 = ptr_value(_p1);
  263. u32 d2 = ptr_value(_p2);
  264. u32 d3 = ptr_value(_p3);
  265. u32 d4 = ptr_value(_p4);
  266. u32 d5 = ptr_value(_p5);
  267. scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3,
  268. &d4, &d4, _cnt);
  269. if (scierr != SC_ERR_NONE) {
  270. printf("Failed to set secvio configuration\n");
  271. debug("Failed to set conf id 0x%x with values ", id);
  272. debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n",
  273. d1, d2, d3, d4, d5, _cnt);
  274. goto exit;
  275. }
  276. if (_p1)
  277. *(u32 *)_p1 = d1;
  278. if (_p2)
  279. *(u32 *)_p2 = d2;
  280. if (_p3)
  281. *(u32 *)_p3 = d3;
  282. if (_p4)
  283. *(u32 *)_p4 = d4;
  284. if (_p5)
  285. *(u32 *)_p5 = d5;
  286. exit:
  287. return scierr;
  288. }
  289. #define SC_CHECK_WRITE1(id, _p1) \
  290. check_write_secvio_config(id, _p1, NULL, NULL, NULL, NULL, 1)
  291. static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
  292. {
  293. int scierr = 0;
  294. debug("%s\n", __func__);
  295. debug("Applying config:\n"
  296. "\thp.lock = 0x%.8x\n"
  297. "\thp.secvio_ctl = 0x%.8x\n"
  298. "\tlp.lock = 0x%.8x\n"
  299. "\tlp.secvio_ctl = 0x%.8x\n"
  300. "\tlp.tamper_filt_cfg = 0x%.8x\n"
  301. "\tlp.tamper_det_cfg = 0x%.8x\n"
  302. "\tlp.tamper_det_cfg2 = 0x%.8x\n"
  303. "\tlp.tamper_filt1_cfg = 0x%.8x\n"
  304. "\tlp.tamper_filt2_cfg = 0x%.8x\n"
  305. "\tlp.act_tamper1_cfg = 0x%.8x\n"
  306. "\tlp.act_tamper2_cfg = 0x%.8x\n"
  307. "\tlp.act_tamper3_cfg = 0x%.8x\n"
  308. "\tlp.act_tamper4_cfg = 0x%.8x\n"
  309. "\tlp.act_tamper5_cfg = 0x%.8x\n"
  310. "\tlp.act_tamper_ctl = 0x%.8x\n"
  311. "\tlp.act_tamper_clk_ctl = 0x%.8x\n"
  312. "\tlp.act_tamper_routing_ctl1 = 0x%.8x\n"
  313. "\tlp.act_tamper_routing_ctl2 = 0x%.8x\n",
  314. cnf->hp.lock,
  315. cnf->hp.secvio_ctl,
  316. cnf->lp.lock,
  317. cnf->lp.secvio_ctl,
  318. cnf->lp.tamper_filt_cfg,
  319. cnf->lp.tamper_det_cfg,
  320. cnf->lp.tamper_det_cfg2,
  321. cnf->lp.tamper_filt1_cfg,
  322. cnf->lp.tamper_filt2_cfg,
  323. cnf->lp.act_tamper1_cfg,
  324. cnf->lp.act_tamper2_cfg,
  325. cnf->lp.act_tamper3_cfg,
  326. cnf->lp.act_tamper4_cfg,
  327. cnf->lp.act_tamper5_cfg,
  328. cnf->lp.act_tamper_ctl,
  329. cnf->lp.act_tamper_clk_ctl,
  330. cnf->lp.act_tamper_routing_ctl1,
  331. cnf->lp.act_tamper_routing_ctl2);
  332. scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
  333. &cnf->lp.tamper_filt_cfg,
  334. &cnf->lp.tamper_filt1_cfg,
  335. &cnf->lp.tamper_filt2_cfg, NULL,
  336. NULL, 3);
  337. if (scierr != SC_ERR_NONE)
  338. goto exit;
  339. /* Configure AT */
  340. scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
  341. &cnf->lp.act_tamper1_cfg,
  342. &cnf->lp.act_tamper2_cfg,
  343. &cnf->lp.act_tamper2_cfg,
  344. &cnf->lp.act_tamper2_cfg,
  345. &cnf->lp.act_tamper2_cfg, 5);
  346. if (scierr != SC_ERR_NONE)
  347. goto exit;
  348. /* Configure AT routing */
  349. scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
  350. &cnf->lp.act_tamper_routing_ctl1,
  351. &cnf->lp.act_tamper_routing_ctl2,
  352. NULL, NULL, NULL, 2);
  353. if (scierr != SC_ERR_NONE)
  354. goto exit;
  355. /* Configure AT frequency */
  356. scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
  357. &cnf->lp.act_tamper_clk_ctl);
  358. if (scierr != SC_ERR_NONE)
  359. goto exit;
  360. /* Activate the ATs */
  361. scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl),
  362. &cnf->lp.act_tamper_ctl);
  363. if (scierr != SC_ERR_NONE)
  364. goto exit;
  365. /* Activate the detectors */
  366. scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
  367. &cnf->lp.tamper_det_cfg,
  368. &cnf->lp.tamper_det_cfg2, NULL, NULL,
  369. NULL, 2);
  370. if (scierr != SC_ERR_NONE)
  371. goto exit;
  372. /* Configure LP secvio */
  373. scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl),
  374. &cnf->lp.secvio_ctl);
  375. if (scierr != SC_ERR_NONE)
  376. goto exit;
  377. /* Configure HP secvio */
  378. scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl),
  379. &cnf->hp.secvio_ctl);
  380. if (scierr != SC_ERR_NONE)
  381. goto exit;
  382. /* Lock access */
  383. scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
  384. if (scierr != SC_ERR_NONE)
  385. goto exit;
  386. scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
  387. if (scierr != SC_ERR_NONE)
  388. goto exit;
  389. exit:
  390. return (scierr == SC_ERR_NONE) ? 0 : -EIO;
  391. }
  392. static int dgo_write(u32 _id, u8 _access, u32 *_pdata)
  393. {
  394. int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
  395. if (scierr != SC_ERR_NONE) {
  396. printf("Failed to set dgo configuration\n");
  397. debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata);
  398. }
  399. return scierr;
  400. }
  401. static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
  402. {
  403. int scierr = 0;
  404. debug("%s\n", __func__);
  405. debug("Applying config:\n"
  406. "\ttamper_offset_ctl = 0x%.8x\n"
  407. "\ttamper_pull_ctl = 0x%.8x\n"
  408. "\ttamper_ana_test_ctl = 0x%.8x\n"
  409. "\ttamper_sensor_trim_ctl = 0x%.8x\n"
  410. "\ttamper_misc_ctl = 0x%.8x\n"
  411. "\ttamper_core_volt_mon_ctl = 0x%.8x\n",
  412. cnf->tamper_offset_ctl,
  413. cnf->tamper_pull_ctl,
  414. cnf->tamper_ana_test_ctl,
  415. cnf->tamper_sensor_trim_ctl,
  416. cnf->tamper_misc_ctl,
  417. cnf->tamper_core_volt_mon_ctl);
  418. dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
  419. if (scierr != SC_ERR_NONE)
  420. goto exit;
  421. dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
  422. if (scierr != SC_ERR_NONE)
  423. goto exit;
  424. dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
  425. if (scierr != SC_ERR_NONE)
  426. goto exit;
  427. dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
  428. if (scierr != SC_ERR_NONE)
  429. goto exit;
  430. dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
  431. if (scierr != SC_ERR_NONE)
  432. goto exit;
  433. /* Last as it could lock the writes */
  434. dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
  435. if (scierr != SC_ERR_NONE)
  436. goto exit;
  437. exit:
  438. return (scierr == SC_ERR_NONE) ? 0 : -EIO;
  439. }
  440. static int pad_write(u32 _pad, u32 _value)
  441. {
  442. int scierr = sc_pad_set(-1, _pad, _value);
  443. if (scierr != SC_ERR_NONE) {
  444. printf("Failed to set pad configuration\n");
  445. debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value);
  446. }
  447. return scierr;
  448. }
  449. static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size)
  450. {
  451. int scierr = 0;
  452. u32 idx;
  453. debug("%s\n", __func__);
  454. for (idx = 0; idx < size; idx++) {
  455. debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad,
  456. confs[idx].mux_conf);
  457. pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
  458. if (scierr != SC_ERR_NONE)
  459. goto exit;
  460. }
  461. exit:
  462. return (scierr == SC_ERR_NONE) ? 0 : -EIO;
  463. }
  464. int examples(void)
  465. {
  466. u32 size;
  467. struct snvs_security_sc_conf *snvs_conf;
  468. struct snvs_dgo_conf *snvs_dgo_conf;
  469. struct tamper_pin_cfg *tamper_pin_conf;
  470. /* Caller */
  471. snvs_conf = get_snvs_config();
  472. snvs_dgo_conf = get_snvs_dgo_config();
  473. tamper_pin_conf = get_tamper_pin_cfg_list(&size);
  474. /* Default */
  475. snvs_conf = &snvs_default_config;
  476. snvs_dgo_conf = &snvs_dgo_default_config;
  477. tamper_pin_conf = tamper_pin_list_default_config;
  478. /* Passive tamper expecting VCC on the line */
  479. snvs_conf = &snvs_passive_vcc_config;
  480. snvs_dgo_conf = &snvs_dgo_passive_vcc_config;
  481. tamper_pin_conf = tamper_pin_list_passive_vcc_config;
  482. /* Passive tamper expecting GND on the line */
  483. snvs_conf = &snvs_passive_gnd_config;
  484. snvs_dgo_conf = &snvs_dgo_passive_gnd_config;
  485. tamper_pin_conf = tamper_pin_list_passive_gnd_config;
  486. /* Active tamper */
  487. snvs_conf = &snvs_active_config;
  488. snvs_dgo_conf = &snvs_dgo_active_config;
  489. tamper_pin_conf = tamper_pin_list_active_config;
  490. return !snvs_conf + !snvs_dgo_conf + !tamper_pin_conf;
  491. }
  492. #ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
  493. int snvs_security_sc_init(void)
  494. {
  495. int err = 0;
  496. struct snvs_security_sc_conf *snvs_conf;
  497. struct snvs_dgo_conf *snvs_dgo_conf;
  498. struct tamper_pin_cfg *tamper_pin_conf;
  499. u32 size;
  500. debug("%s\n", __func__);
  501. snvs_conf = get_snvs_config();
  502. snvs_dgo_conf = get_snvs_dgo_config();
  503. tamper_pin_conf = get_tamper_pin_cfg_list(&size);
  504. err = apply_tamper_pin_list_config(tamper_pin_conf, size);
  505. if (err) {
  506. debug("Failed to set pins\n");
  507. goto exit;
  508. }
  509. err = apply_snvs_dgo_config(snvs_dgo_conf);
  510. if (err) {
  511. debug("Failed to set dgo\n");
  512. goto exit;
  513. }
  514. err = apply_snvs_config(snvs_conf);
  515. if (err) {
  516. debug("Failed to set snvs\n");
  517. goto exit;
  518. }
  519. exit:
  520. return err;
  521. }
  522. #endif /* CONFIG_IMX_SNVS_SEC_SC_AUTO */
  523. static char snvs_cfg_help_text[] =
  524. "snvs_cfg\n"
  525. "\thp.lock\n"
  526. "\thp.secvio_ctl\n"
  527. "\tlp.lock\n"
  528. "\tlp.secvio_ctl\n"
  529. "\tlp.tamper_filt_cfg\n"
  530. "\tlp.tamper_det_cfg\n"
  531. "\tlp.tamper_det_cfg2\n"
  532. "\tlp.tamper_filt1_cfg\n"
  533. "\tlp.tamper_filt2_cfg\n"
  534. "\tlp.act_tamper1_cfg\n"
  535. "\tlp.act_tamper2_cfg\n"
  536. "\tlp.act_tamper3_cfg\n"
  537. "\tlp.act_tamper4_cfg\n"
  538. "\tlp.act_tamper5_cfg\n"
  539. "\tlp.act_tamper_ctl\n"
  540. "\tlp.act_tamper_clk_ctl\n"
  541. "\tlp.act_tamper_routing_ctl1\n"
  542. "\tlp.act_tamper_routing_ctl2\n"
  543. "\n"
  544. "ALL values should be in hexadecimal format";
  545. #define NB_REGISTERS 18
  546. static int do_snvs_cfg(struct cmd_tbl *cmdtp, int flag, int argc,
  547. char *const argv[])
  548. {
  549. int err = 0;
  550. u32 idx = 0;
  551. struct snvs_security_sc_conf conf = {0};
  552. if (argc != (NB_REGISTERS + 1))
  553. return CMD_RET_USAGE;
  554. conf.hp.lock = hextoul(argv[++idx], NULL);
  555. conf.hp.secvio_ctl = hextoul(argv[++idx], NULL);
  556. conf.lp.lock = hextoul(argv[++idx], NULL);
  557. conf.lp.secvio_ctl = hextoul(argv[++idx], NULL);
  558. conf.lp.tamper_filt_cfg = hextoul(argv[++idx], NULL);
  559. conf.lp.tamper_det_cfg = hextoul(argv[++idx], NULL);
  560. conf.lp.tamper_det_cfg2 = hextoul(argv[++idx], NULL);
  561. conf.lp.tamper_filt1_cfg = hextoul(argv[++idx], NULL);
  562. conf.lp.tamper_filt2_cfg = hextoul(argv[++idx], NULL);
  563. conf.lp.act_tamper1_cfg = hextoul(argv[++idx], NULL);
  564. conf.lp.act_tamper2_cfg = hextoul(argv[++idx], NULL);
  565. conf.lp.act_tamper3_cfg = hextoul(argv[++idx], NULL);
  566. conf.lp.act_tamper4_cfg = hextoul(argv[++idx], NULL);
  567. conf.lp.act_tamper5_cfg = hextoul(argv[++idx], NULL);
  568. conf.lp.act_tamper_ctl = hextoul(argv[++idx], NULL);
  569. conf.lp.act_tamper_clk_ctl = hextoul(argv[++idx], NULL);
  570. conf.lp.act_tamper_routing_ctl1 = hextoul(argv[++idx], NULL);
  571. conf.lp.act_tamper_routing_ctl2 = hextoul(argv[++idx], NULL);
  572. err = apply_snvs_config(&conf);
  573. return err;
  574. }
  575. U_BOOT_CMD(snvs_cfg,
  576. NB_REGISTERS + 1, 1, do_snvs_cfg,
  577. "Security violation configuration",
  578. snvs_cfg_help_text
  579. );
  580. static char snvs_dgo_cfg_help_text[] =
  581. "snvs_dgo_cfg\n"
  582. "\ttamper_offset_ctl\n"
  583. "\ttamper_pull_ctl\n"
  584. "\ttamper_ana_test_ctl\n"
  585. "\ttamper_sensor_trim_ctl\n"
  586. "\ttamper_misc_ctl\n"
  587. "\ttamper_core_volt_mon_ctl\n"
  588. "\n"
  589. "ALL values should be in hexadecimal format";
  590. static int do_snvs_dgo_cfg(struct cmd_tbl *cmdtp, int flag, int argc,
  591. char *const argv[])
  592. {
  593. int err = 0;
  594. u32 idx = 0;
  595. struct snvs_dgo_conf conf = {0};
  596. if (argc != (6 + 1))
  597. return CMD_RET_USAGE;
  598. conf.tamper_offset_ctl = hextoul(argv[++idx], NULL);
  599. conf.tamper_pull_ctl = hextoul(argv[++idx], NULL);
  600. conf.tamper_ana_test_ctl = hextoul(argv[++idx], NULL);
  601. conf.tamper_sensor_trim_ctl = hextoul(argv[++idx], NULL);
  602. conf.tamper_misc_ctl = hextoul(argv[++idx], NULL);
  603. conf.tamper_core_volt_mon_ctl = hextoul(argv[++idx], NULL);
  604. err = apply_snvs_dgo_config(&conf);
  605. return err;
  606. }
  607. U_BOOT_CMD(snvs_dgo_cfg,
  608. 7, 1, do_snvs_dgo_cfg,
  609. "SNVS DGO configuration",
  610. snvs_dgo_cfg_help_text
  611. );
  612. static char tamper_pin_cfg_help_text[] =
  613. "snvs_dgo_cfg\n"
  614. "\tpad\n"
  615. "\tvalue\n"
  616. "\n"
  617. "ALL values should be in hexadecimal format";
  618. static int do_tamper_pin_cfg(struct cmd_tbl *cmdtp, int flag, int argc,
  619. char *const argv[])
  620. {
  621. int err = 0;
  622. u32 idx = 0;
  623. struct tamper_pin_cfg conf = {0};
  624. if (argc != (2 + 1))
  625. return CMD_RET_USAGE;
  626. conf.pad = dectoul(argv[++idx], NULL);
  627. conf.mux_conf = hextoul(argv[++idx], NULL);
  628. err = apply_tamper_pin_list_config(&conf, 1);
  629. return err;
  630. }
  631. U_BOOT_CMD(tamper_pin_cfg,
  632. 3, 1, do_tamper_pin_cfg,
  633. "tamper pin configuration",
  634. tamper_pin_cfg_help_text
  635. );
  636. static char snvs_clear_status_help_text[] =
  637. "snvs_clear_status\n"
  638. "\tHPSR\n"
  639. "\tHPSVSR\n"
  640. "\tLPSR\n"
  641. "\tLPTDSR\n"
  642. "\n"
  643. "Write the status registers with the value provided,"
  644. " clearing the status";
  645. static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc,
  646. char *const argv[])
  647. {
  648. int scierr = 0;
  649. u32 idx = 0;
  650. struct snvs_security_sc_conf conf = {0};
  651. if (argc != (2 + 1))
  652. return CMD_RET_USAGE;
  653. conf.lp.status = hextoul(argv[++idx], NULL);
  654. conf.lp.tamper_det_status = hextoul(argv[++idx], NULL);
  655. scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
  656. &conf.lp.status, NULL, NULL, NULL,
  657. NULL, 1);
  658. if (scierr != SC_ERR_NONE)
  659. goto exit;
  660. scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
  661. &conf.lp.tamper_det_status, NULL,
  662. NULL, NULL, NULL, 1);
  663. if (scierr != SC_ERR_NONE)
  664. goto exit;
  665. exit:
  666. return (scierr == SC_ERR_NONE) ? 0 : 1;
  667. }
  668. U_BOOT_CMD(snvs_clear_status,
  669. 3, 1, do_snvs_clear_status,
  670. "snvs clear status",
  671. snvs_clear_status_help_text
  672. );
  673. static char snvs_sec_status_help_text[] =
  674. "snvs_sec_status\n"
  675. "Display information about the security related to tamper and secvio";
  676. static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
  677. char *const argv[])
  678. {
  679. int scierr;
  680. u32 idx;
  681. u32 data[5];
  682. u32 pads[] = {
  683. SC_P_CSI_D00,
  684. SC_P_CSI_D01,
  685. SC_P_CSI_D02,
  686. SC_P_CSI_D03,
  687. SC_P_CSI_D04,
  688. SC_P_CSI_D05,
  689. SC_P_CSI_D06,
  690. SC_P_CSI_D07,
  691. SC_P_CSI_HSYNC,
  692. SC_P_CSI_VSYNC,
  693. };
  694. u32 fuses[] = {
  695. 14,
  696. 30,
  697. 31,
  698. 260,
  699. 261,
  700. 262,
  701. 263,
  702. 768,
  703. };
  704. struct snvs_reg {
  705. u32 id;
  706. u32 nb;
  707. } snvs[] = {
  708. /* Locks */
  709. {0x0, 1},
  710. {0x34, 1},
  711. /* Security violation */
  712. {0xc, 1},
  713. {0x10, 1},
  714. {0x18, 1},
  715. {0x40, 1},
  716. /* Temper detectors */
  717. {0x48, 2},
  718. {0x4c, 1},
  719. {0xa4, 1},
  720. /* */
  721. {0x44, 3},
  722. {0xe0, 1},
  723. {0xe4, 1},
  724. {0xe8, 2},
  725. /* Misc */
  726. {0x3c, 1},
  727. {0x5c, 2},
  728. {0x64, 1},
  729. {0xf8, 2},
  730. };
  731. u32 dgo[] = {
  732. 0x0,
  733. 0x10,
  734. 0x20,
  735. 0x30,
  736. 0x40,
  737. 0x50,
  738. };
  739. /* Pins */
  740. printf("Pins:\n");
  741. for (idx = 0; idx < ARRAY_SIZE(pads); idx++) {
  742. u8 pad_id = pads[idx];
  743. scierr = sc_pad_get(-1, pad_id, &data[0]);
  744. if (scierr == 0)
  745. printf("\t- Pin %d: %.8x\n", pad_id, data[0]);
  746. else
  747. printf("Failed to read Pin %d\n", pad_id);
  748. }
  749. /* Fuses */
  750. printf("Fuses:\n");
  751. for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) {
  752. u32 fuse_id = fuses[idx];
  753. scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
  754. if (scierr == 0)
  755. printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]);
  756. else
  757. printf("Failed to read Fuse %d\n", fuse_id);
  758. }
  759. /* SNVS */
  760. printf("SNVS:\n");
  761. for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) {
  762. struct snvs_reg *reg = &snvs[idx];
  763. scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
  764. &data[1], &data[2], &data[3],
  765. &data[4], reg->nb);
  766. if (scierr == 0) {
  767. int subidx;
  768. printf("\t- SNVS %.2x(%d):", reg->id, reg->nb);
  769. for (subidx = 0; subidx < reg->nb; subidx++)
  770. printf(" %.8x", data[subidx]);
  771. printf("\n");
  772. } else {
  773. printf("Failed to read SNVS %d\n", reg->id);
  774. }
  775. }
  776. /* DGO */
  777. printf("DGO:\n");
  778. for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) {
  779. u8 dgo_id = dgo[idx];
  780. scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
  781. if (scierr == 0)
  782. printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]);
  783. else
  784. printf("Failed to read DGO %d\n", dgo_id);
  785. }
  786. return 0;
  787. }
  788. U_BOOT_CMD(snvs_sec_status,
  789. 1, 1, do_snvs_sec_status,
  790. "tamper pin configuration",
  791. snvs_sec_status_help_text
  792. );