soc.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor
  4. * Copyright 2019-2021 NXP
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <fsl_immap.h>
  11. #include <fsl_ifc.h>
  12. #include <init.h>
  13. #include <linux/sizes.h>
  14. #include <log.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/cache.h>
  18. #include <asm/io.h>
  19. #include <asm/global_data.h>
  20. #include <asm/arch-fsl-layerscape/config.h>
  21. #include <asm/arch-fsl-layerscape/ns_access.h>
  22. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  23. #include <asm/gic-v3.h>
  24. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  25. #include <fsl_csu.h>
  26. #endif
  27. #ifdef CONFIG_SYS_FSL_DDR
  28. #include <fsl_ddr_sdram.h>
  29. #include <fsl_ddr.h>
  30. #endif
  31. #ifdef CONFIG_CHAIN_OF_TRUST
  32. #include <fsl_validate.h>
  33. #endif
  34. #include <fsl_immap.h>
  35. #include <dm.h>
  36. #include <dm/device_compat.h>
  37. #include <linux/err.h>
  38. #ifdef CONFIG_GIC_V3_ITS
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #endif
  41. #ifdef CONFIG_GIC_V3_ITS
  42. int ls_gic_rd_tables_init(void *blob)
  43. {
  44. struct fdt_memory lpi_base;
  45. fdt_addr_t addr;
  46. fdt_size_t size;
  47. int offset, ret;
  48. offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000");
  49. addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg",
  50. 0, &size, false);
  51. lpi_base.start = addr;
  52. lpi_base.end = addr + size - 1;
  53. ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false);
  54. if (ret) {
  55. debug("%s: failed to add reserved memory\n", __func__);
  56. return ret;
  57. }
  58. ret = gic_lpi_tables_init();
  59. if (ret)
  60. debug("%s: failed to init gic-lpi-tables\n", __func__);
  61. return ret;
  62. }
  63. #endif
  64. bool soc_has_dp_ddr(void)
  65. {
  66. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  67. u32 svr = gur_in32(&gur->svr);
  68. /* LS2085A, LS2088A, LS2048A has DP_DDR */
  69. if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
  70. (SVR_SOC_VER(svr) == SVR_LS2088A) ||
  71. (SVR_SOC_VER(svr) == SVR_LS2048A))
  72. return true;
  73. return false;
  74. }
  75. bool soc_has_aiop(void)
  76. {
  77. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  78. u32 svr = gur_in32(&gur->svr);
  79. /* LS2085A has AIOP */
  80. if (SVR_SOC_VER(svr) == SVR_LS2085A)
  81. return true;
  82. return false;
  83. }
  84. static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
  85. {
  86. scfg_clrsetbits32(scfg + offset / 4,
  87. 0xF << 6,
  88. SCFG_USB_TXVREFTUNE << 6);
  89. }
  90. static void erratum_a009008(void)
  91. {
  92. #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  93. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  94. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  95. defined(CONFIG_ARCH_LS1012A)
  96. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
  97. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  98. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
  99. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
  100. #endif
  101. #elif defined(CONFIG_ARCH_LS2080A)
  102. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
  103. #endif
  104. #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  105. }
  106. static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
  107. {
  108. scfg_clrbits32(scfg + offset / 4,
  109. SCFG_USB_SQRXTUNE_MASK << 23);
  110. }
  111. static void erratum_a009798(void)
  112. {
  113. #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  114. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  115. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  116. defined(CONFIG_ARCH_LS1012A)
  117. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
  118. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  119. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
  120. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
  121. #endif
  122. #elif defined(CONFIG_ARCH_LS2080A)
  123. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
  124. #endif
  125. #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  126. }
  127. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  128. defined(CONFIG_ARCH_LS1012A)
  129. static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
  130. {
  131. scfg_clrsetbits32(scfg + offset / 4,
  132. 0x7F << 9,
  133. SCFG_USB_PCSTXSWINGFULL << 9);
  134. }
  135. #endif
  136. static void erratum_a008997(void)
  137. {
  138. #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  139. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  140. defined(CONFIG_ARCH_LS1012A)
  141. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  142. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
  143. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  144. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
  145. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
  146. #endif
  147. #elif defined(CONFIG_ARCH_LS1028A)
  148. clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
  149. 0x7F << 11,
  150. DCSR_USB_PCSTXSWINGFULL << 11);
  151. #endif
  152. #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  153. }
  154. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  155. defined(CONFIG_ARCH_LS1012A)
  156. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  157. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  158. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  159. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  160. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  161. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  162. defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
  163. defined(CONFIG_ARCH_LX2162A)
  164. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  165. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  166. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  167. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  168. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  169. #endif
  170. static void erratum_a009007(void)
  171. {
  172. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  173. defined(CONFIG_ARCH_LS1012A)
  174. void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
  175. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  176. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  177. usb_phy = (void __iomem *)SCFG_USB_PHY2;
  178. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  179. usb_phy = (void __iomem *)SCFG_USB_PHY3;
  180. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  181. #endif
  182. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  183. defined(CONFIG_ARCH_LS1028A)
  184. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  185. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  186. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  187. #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
  188. }
  189. #if defined(CONFIG_FSL_LSCH3)
  190. static void erratum_a050204(void)
  191. {
  192. #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
  193. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  194. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  195. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  196. #endif
  197. }
  198. /*
  199. * This erratum requires setting a value to eddrtqcr1 to
  200. * optimal the DDR performance.
  201. */
  202. static void erratum_a008336(void)
  203. {
  204. #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  205. u32 *eddrtqcr1;
  206. #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
  207. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  208. if (fsl_ddr_get_version(0) == 0x50200)
  209. out_le32(eddrtqcr1, 0x63b30002);
  210. #endif
  211. #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
  212. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  213. if (fsl_ddr_get_version(0) == 0x50200)
  214. out_le32(eddrtqcr1, 0x63b30002);
  215. #endif
  216. #endif
  217. }
  218. /*
  219. * This erratum requires a register write before being Memory
  220. * controller 3 being enabled.
  221. */
  222. static void erratum_a008514(void)
  223. {
  224. #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  225. u32 *eddrtqcr1;
  226. #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
  227. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  228. out_le32(eddrtqcr1, 0x63b20002);
  229. #endif
  230. #endif
  231. }
  232. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  233. #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
  234. static unsigned long get_internval_val_mhz(void)
  235. {
  236. char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
  237. /*
  238. * interval is the number of platform cycles(MHz) between
  239. * wake up events generated by EPU.
  240. */
  241. ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
  242. if (interval)
  243. interval_mhz = dectoul(interval, NULL);
  244. return interval_mhz;
  245. }
  246. void erratum_a009635(void)
  247. {
  248. u32 val;
  249. unsigned long interval_mhz = get_internval_val_mhz();
  250. if (!interval_mhz)
  251. return;
  252. val = in_le32(DCSR_CGACRE5);
  253. writel(val | 0x00000200, DCSR_CGACRE5);
  254. val = in_le32(EPU_EPCMPR5);
  255. writel(interval_mhz, EPU_EPCMPR5);
  256. val = in_le32(EPU_EPCCR5);
  257. writel(val | 0x82820000, EPU_EPCCR5);
  258. val = in_le32(EPU_EPSMCR5);
  259. writel(val | 0x002f0000, EPU_EPSMCR5);
  260. val = in_le32(EPU_EPECR5);
  261. writel(val | 0x20000000, EPU_EPECR5);
  262. val = in_le32(EPU_EPGCR);
  263. writel(val | 0x80000000, EPU_EPGCR);
  264. }
  265. #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
  266. static void erratum_rcw_src(void)
  267. {
  268. #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
  269. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  270. u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  271. u32 val;
  272. val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  273. val &= ~DCFG_PORSR1_RCW_SRC;
  274. val |= DCFG_PORSR1_RCW_SRC_NOR;
  275. out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  276. #endif
  277. }
  278. #define I2C_DEBUG_REG 0x6
  279. #define I2C_GLITCH_EN 0x8
  280. /*
  281. * This erratum requires setting glitch_en bit to enable
  282. * digital glitch filter to improve clock stability.
  283. */
  284. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  285. static void erratum_a009203(void)
  286. {
  287. #ifdef CONFIG_SYS_I2C_LEGACY
  288. u8 __iomem *ptr;
  289. #ifdef I2C1_BASE_ADDR
  290. ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
  291. writeb(I2C_GLITCH_EN, ptr);
  292. #endif
  293. #ifdef I2C2_BASE_ADDR
  294. ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
  295. writeb(I2C_GLITCH_EN, ptr);
  296. #endif
  297. #ifdef I2C3_BASE_ADDR
  298. ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
  299. writeb(I2C_GLITCH_EN, ptr);
  300. #endif
  301. #ifdef I2C4_BASE_ADDR
  302. ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
  303. writeb(I2C_GLITCH_EN, ptr);
  304. #endif
  305. #endif
  306. }
  307. #endif
  308. void bypass_smmu(void)
  309. {
  310. u32 val;
  311. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  312. out_le32(SMMU_SCR0, val);
  313. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  314. out_le32(SMMU_NSCR0, val);
  315. }
  316. void fsl_lsch3_early_init_f(void)
  317. {
  318. erratum_rcw_src();
  319. #ifdef CONFIG_FSL_IFC
  320. init_early_memctl_regs(); /* tighten IFC timing */
  321. #endif
  322. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  323. erratum_a009203();
  324. #endif
  325. erratum_a008514();
  326. erratum_a008336();
  327. erratum_a009008();
  328. erratum_a009798();
  329. erratum_a008997();
  330. erratum_a009007();
  331. erratum_a050204();
  332. #ifdef CONFIG_CHAIN_OF_TRUST
  333. /* In case of Secure Boot, the IBR configures the SMMU
  334. * to allow only Secure transactions.
  335. * SMMU must be reset in bypass mode.
  336. * Set the ClientPD bit and Clear the USFCFG Bit
  337. */
  338. if (fsl_check_boot_mode_secure() == 1)
  339. bypass_smmu();
  340. #endif
  341. #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
  342. defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
  343. defined(CONFIG_ARCH_LX2162A)
  344. set_icids();
  345. #endif
  346. }
  347. /* Get VDD in the unit mV from voltage ID */
  348. int get_core_volt_from_fuse(void)
  349. {
  350. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  351. int vdd;
  352. u32 fusesr;
  353. u8 vid;
  354. /* get the voltage ID from fuse status register */
  355. fusesr = in_le32(&gur->dcfg_fusesr);
  356. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  357. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
  358. FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
  359. if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
  360. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
  361. FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
  362. }
  363. debug("%s: VID = 0x%x\n", __func__, vid);
  364. switch (vid) {
  365. case 0x00: /* VID isn't supported */
  366. vdd = -EINVAL;
  367. debug("%s: The VID feature is not supported\n", __func__);
  368. break;
  369. case 0x08: /* 0.9V silicon */
  370. vdd = 900;
  371. break;
  372. case 0x10: /* 1.0V silicon */
  373. vdd = 1000;
  374. break;
  375. default: /* Other core voltage */
  376. vdd = -EINVAL;
  377. debug("%s: The VID(%x) isn't supported\n", __func__, vid);
  378. break;
  379. }
  380. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  381. return vdd;
  382. }
  383. #elif defined(CONFIG_FSL_LSCH2)
  384. /*
  385. * This erratum requires setting a value to eddrtqcr1 to optimal
  386. * the DDR performance. The eddrtqcr1 register is in SCFG space
  387. * of LS1043A and the offset is 0x157_020c.
  388. */
  389. #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
  390. && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  391. #error A009660 and A008514 can not be both enabled.
  392. #endif
  393. static void erratum_a009660(void)
  394. {
  395. #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
  396. u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
  397. out_be32(eddrtqcr1, 0x63b20042);
  398. #endif
  399. }
  400. static void erratum_a008850_early(void)
  401. {
  402. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  403. /* part 1 of 2 */
  404. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  405. CONFIG_SYS_CCI400_OFFSET);
  406. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  407. /* Skip if running at lower exception level */
  408. if (current_el() < 3)
  409. return;
  410. /* disables propagation of barrier transactions to DDRC from CCI400 */
  411. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
  412. /* disable the re-ordering in DDRC */
  413. ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  414. #endif
  415. }
  416. void erratum_a008850_post(void)
  417. {
  418. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  419. /* part 2 of 2 */
  420. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  421. CONFIG_SYS_CCI400_OFFSET);
  422. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  423. u32 tmp;
  424. /* Skip if running at lower exception level */
  425. if (current_el() < 3)
  426. return;
  427. /* enable propagation of barrier transactions to DDRC from CCI400 */
  428. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  429. /* enable the re-ordering in DDRC */
  430. tmp = ddr_in32(&ddr->eor);
  431. tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  432. ddr_out32(&ddr->eor, tmp);
  433. #endif
  434. }
  435. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  436. void erratum_a010315(void)
  437. {
  438. int i;
  439. for (i = PCIE1; i <= PCIE4; i++)
  440. if (!is_serdes_configured(i)) {
  441. debug("PCIe%d: disabled all R/W permission!\n", i);
  442. set_pcie_ns_access(i, 0);
  443. }
  444. }
  445. #endif
  446. static void erratum_a010539(void)
  447. {
  448. #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
  449. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  450. u32 porsr1;
  451. porsr1 = in_be32(&gur->porsr1);
  452. porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
  453. out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  454. porsr1);
  455. out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
  456. #endif
  457. }
  458. /* Get VDD in the unit mV from voltage ID */
  459. int get_core_volt_from_fuse(void)
  460. {
  461. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  462. int vdd;
  463. u32 fusesr;
  464. u8 vid;
  465. fusesr = in_be32(&gur->dcfg_fusesr);
  466. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  467. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
  468. FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
  469. if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
  470. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
  471. FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
  472. }
  473. debug("%s: VID = 0x%x\n", __func__, vid);
  474. switch (vid) {
  475. case 0x00: /* VID isn't supported */
  476. vdd = -EINVAL;
  477. debug("%s: The VID feature is not supported\n", __func__);
  478. break;
  479. case 0x08: /* 0.9V silicon */
  480. vdd = 900;
  481. break;
  482. case 0x10: /* 1.0V silicon */
  483. vdd = 1000;
  484. break;
  485. default: /* Other core voltage */
  486. vdd = -EINVAL;
  487. printf("%s: The VID(%x) isn't supported\n", __func__, vid);
  488. break;
  489. }
  490. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  491. return vdd;
  492. }
  493. __weak int board_switch_core_volt(u32 vdd)
  494. {
  495. return 0;
  496. }
  497. static int setup_core_volt(u32 vdd)
  498. {
  499. return board_setup_core_volt(vdd);
  500. }
  501. #ifdef CONFIG_SYS_FSL_DDR
  502. static void ddr_enable_0v9_volt(bool en)
  503. {
  504. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  505. u32 tmp;
  506. tmp = ddr_in32(&ddr->ddr_cdr1);
  507. if (en)
  508. tmp |= DDR_CDR1_V0PT9_EN;
  509. else
  510. tmp &= ~DDR_CDR1_V0PT9_EN;
  511. ddr_out32(&ddr->ddr_cdr1, tmp);
  512. }
  513. #endif
  514. int setup_chip_volt(void)
  515. {
  516. int vdd;
  517. vdd = get_core_volt_from_fuse();
  518. /* Nothing to do for silicons doesn't support VID */
  519. if (vdd < 0)
  520. return vdd;
  521. if (setup_core_volt(vdd))
  522. printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
  523. #ifdef CONFIG_SYS_HAS_SERDES
  524. if (setup_serdes_volt(vdd))
  525. printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
  526. #endif
  527. #ifdef CONFIG_SYS_FSL_DDR
  528. if (vdd == 900)
  529. ddr_enable_0v9_volt(true);
  530. #endif
  531. return 0;
  532. }
  533. #ifdef CONFIG_FSL_PFE
  534. void init_pfe_scfg_dcfg_regs(void)
  535. {
  536. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  537. u32 ecccr2;
  538. out_be32(&scfg->pfeasbcr,
  539. in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
  540. out_be32(&scfg->pfebsbcr,
  541. in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
  542. /* CCI-400 QoS settings for PFE */
  543. out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
  544. | SCFG_WR_QOS1_PFE2_QOS));
  545. out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
  546. | SCFG_RD_QOS1_PFE2_QOS));
  547. ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
  548. out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
  549. ecccr2 | (unsigned int)DISABLE_PFE_ECC);
  550. }
  551. #endif
  552. void fsl_lsch2_early_init_f(void)
  553. {
  554. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  555. CONFIG_SYS_CCI400_OFFSET);
  556. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  557. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  558. enum boot_src src;
  559. #endif
  560. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  561. enable_layerscape_ns_access();
  562. #endif
  563. #ifdef CONFIG_FSL_IFC
  564. init_early_memctl_regs(); /* tighten IFC timing */
  565. #endif
  566. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  567. src = get_boot_src();
  568. if (src != BOOT_SOURCE_QSPI_NOR)
  569. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  570. #else
  571. #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
  572. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  573. #endif
  574. #endif
  575. /* Make SEC reads and writes snoopable */
  576. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  577. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  578. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  579. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
  580. SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
  581. SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  582. SCFG_SNPCNFGCR_SATAWRSNP);
  583. #elif defined(CONFIG_ARCH_LS1012A)
  584. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  585. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  586. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  587. SCFG_SNPCNFGCR_SATAWRSNP);
  588. #else
  589. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  590. SCFG_SNPCNFGCR_SECWRSNP |
  591. SCFG_SNPCNFGCR_SATARDSNP |
  592. SCFG_SNPCNFGCR_SATAWRSNP);
  593. #endif
  594. /*
  595. * Enable snoop requests and DVM message requests for
  596. * Slave insterface S4 (A53 core cluster)
  597. */
  598. if (current_el() == 3) {
  599. out_le32(&cci->slave[4].snoop_ctrl,
  600. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  601. }
  602. /*
  603. * Program Central Security Unit (CSU) to grant access
  604. * permission for USB 2.0 controller
  605. */
  606. #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
  607. if (current_el() == 3)
  608. set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
  609. #endif
  610. /* Erratum */
  611. erratum_a008850_early(); /* part 1 of 2 */
  612. erratum_a009660();
  613. erratum_a010539();
  614. erratum_a009008();
  615. erratum_a009798();
  616. erratum_a008997();
  617. erratum_a009007();
  618. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  619. set_icids();
  620. #endif
  621. }
  622. #endif
  623. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  624. int fspi_ahb_init(void)
  625. {
  626. /* Enable 4bytes address support and fast read */
  627. u32 *fspi_lut, lut_key, *fspi_key;
  628. fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
  629. fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
  630. lut_key = in_be32(fspi_key);
  631. if (lut_key == SYS_NXP_FSPI_LUTKEY) {
  632. /* That means the register is BE */
  633. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  634. /* Unlock the lut table */
  635. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  636. /* Create READ LUT */
  637. out_be32(fspi_lut, 0x0820040c);
  638. out_be32(fspi_lut + 1, 0x24003008);
  639. out_be32(fspi_lut + 2, 0x00000000);
  640. /* Lock the lut table */
  641. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  642. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  643. } else {
  644. /* That means the register is LE */
  645. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  646. /* Unlock the lut table */
  647. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  648. /* Create READ LUT */
  649. out_le32(fspi_lut, 0x0820040c);
  650. out_le32(fspi_lut + 1, 0x24003008);
  651. out_le32(fspi_lut + 2, 0x00000000);
  652. /* Lock the lut table */
  653. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  654. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  655. }
  656. return 0;
  657. }
  658. #endif
  659. #ifdef CONFIG_QSPI_AHB_INIT
  660. /* Enable 4bytes address support and fast read */
  661. int qspi_ahb_init(void)
  662. {
  663. u32 *qspi_lut, lut_key, *qspi_key;
  664. qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
  665. qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
  666. lut_key = in_be32(qspi_key);
  667. if (lut_key == 0x5af05af0) {
  668. /* That means the register is BE */
  669. out_be32(qspi_key, 0x5af05af0);
  670. /* Unlock the lut table */
  671. out_be32(qspi_key + 1, 0x00000002);
  672. out_be32(qspi_lut, 0x0820040c);
  673. out_be32(qspi_lut + 1, 0x1c080c08);
  674. out_be32(qspi_lut + 2, 0x00002400);
  675. /* Lock the lut table */
  676. out_be32(qspi_key, 0x5af05af0);
  677. out_be32(qspi_key + 1, 0x00000001);
  678. } else {
  679. /* That means the register is LE */
  680. out_le32(qspi_key, 0x5af05af0);
  681. /* Unlock the lut table */
  682. out_le32(qspi_key + 1, 0x00000002);
  683. out_le32(qspi_lut, 0x0820040c);
  684. out_le32(qspi_lut + 1, 0x1c080c08);
  685. out_le32(qspi_lut + 2, 0x00002400);
  686. /* Lock the lut table */
  687. out_le32(qspi_key, 0x5af05af0);
  688. out_le32(qspi_key + 1, 0x00000001);
  689. }
  690. return 0;
  691. }
  692. #endif
  693. #ifdef CONFIG_TFABOOT
  694. #define MAX_BOOTCMD_SIZE 512
  695. int fsl_setenv_bootcmd(void)
  696. {
  697. int ret;
  698. enum boot_src src = get_boot_src();
  699. char bootcmd_str[MAX_BOOTCMD_SIZE];
  700. switch (src) {
  701. #ifdef IFC_NOR_BOOTCOMMAND
  702. case BOOT_SOURCE_IFC_NOR:
  703. sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
  704. break;
  705. #endif
  706. #ifdef QSPI_NOR_BOOTCOMMAND
  707. case BOOT_SOURCE_QSPI_NOR:
  708. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  709. break;
  710. #endif
  711. #ifdef XSPI_NOR_BOOTCOMMAND
  712. case BOOT_SOURCE_XSPI_NOR:
  713. sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
  714. break;
  715. #endif
  716. #ifdef IFC_NAND_BOOTCOMMAND
  717. case BOOT_SOURCE_IFC_NAND:
  718. sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
  719. break;
  720. #endif
  721. #ifdef QSPI_NAND_BOOTCOMMAND
  722. case BOOT_SOURCE_QSPI_NAND:
  723. sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
  724. break;
  725. #endif
  726. #ifdef XSPI_NAND_BOOTCOMMAND
  727. case BOOT_SOURCE_XSPI_NAND:
  728. sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
  729. break;
  730. #endif
  731. #ifdef SD_BOOTCOMMAND
  732. case BOOT_SOURCE_SD_MMC:
  733. sprintf(bootcmd_str, SD_BOOTCOMMAND);
  734. break;
  735. #endif
  736. #ifdef SD2_BOOTCOMMAND
  737. case BOOT_SOURCE_SD_MMC2:
  738. sprintf(bootcmd_str, SD2_BOOTCOMMAND);
  739. break;
  740. #endif
  741. default:
  742. #ifdef QSPI_NOR_BOOTCOMMAND
  743. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  744. #endif
  745. break;
  746. }
  747. ret = env_set("bootcmd", bootcmd_str);
  748. if (ret) {
  749. printf("Failed to set bootcmd: ret = %d\n", ret);
  750. return ret;
  751. }
  752. return 0;
  753. }
  754. int fsl_setenv_mcinitcmd(void)
  755. {
  756. int ret = 0;
  757. enum boot_src src = get_boot_src();
  758. switch (src) {
  759. #ifdef IFC_MC_INIT_CMD
  760. case BOOT_SOURCE_IFC_NAND:
  761. case BOOT_SOURCE_IFC_NOR:
  762. ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
  763. break;
  764. #endif
  765. #ifdef QSPI_MC_INIT_CMD
  766. case BOOT_SOURCE_QSPI_NAND:
  767. case BOOT_SOURCE_QSPI_NOR:
  768. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  769. break;
  770. #endif
  771. #ifdef XSPI_MC_INIT_CMD
  772. case BOOT_SOURCE_XSPI_NAND:
  773. case BOOT_SOURCE_XSPI_NOR:
  774. ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
  775. break;
  776. #endif
  777. #ifdef SD_MC_INIT_CMD
  778. case BOOT_SOURCE_SD_MMC:
  779. ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
  780. break;
  781. #endif
  782. #ifdef SD2_MC_INIT_CMD
  783. case BOOT_SOURCE_SD_MMC2:
  784. ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
  785. break;
  786. #endif
  787. default:
  788. #ifdef QSPI_MC_INIT_CMD
  789. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  790. #endif
  791. break;
  792. }
  793. if (ret) {
  794. printf("Failed to set mcinitcmd: ret = %d\n", ret);
  795. return ret;
  796. }
  797. return 0;
  798. }
  799. #endif
  800. #ifdef CONFIG_BOARD_LATE_INIT
  801. __weak int fsl_board_late_init(void)
  802. {
  803. return 0;
  804. }
  805. #define DWC3_GSBUSCFG0 0xc100
  806. #define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16
  807. #define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
  808. << DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
  809. void enable_dwc3_snooping(void)
  810. {
  811. int ret;
  812. u32 val;
  813. struct udevice *bus;
  814. struct uclass *uc;
  815. fdt_addr_t dwc3_base;
  816. ret = uclass_get(UCLASS_USB, &uc);
  817. if (ret)
  818. return;
  819. uclass_foreach_dev(bus, uc) {
  820. if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
  821. dwc3_base = devfdt_get_addr(bus);
  822. if (dwc3_base == FDT_ADDR_T_NONE) {
  823. dev_err(bus, "dwc3 regs missing\n");
  824. continue;
  825. }
  826. val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
  827. val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
  828. val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
  829. writel(val, dwc3_base + DWC3_GSBUSCFG0);
  830. }
  831. }
  832. }
  833. int board_late_init(void)
  834. {
  835. #ifdef CONFIG_CHAIN_OF_TRUST
  836. fsl_setenv_chain_of_trust();
  837. #endif
  838. #ifdef CONFIG_TFABOOT
  839. /*
  840. * Set bootcmd and mcinitcmd if they don't exist in the environment.
  841. */
  842. if (!env_get("bootcmd"))
  843. fsl_setenv_bootcmd();
  844. if (!env_get("mcinitcmd"))
  845. fsl_setenv_mcinitcmd();
  846. #endif
  847. #ifdef CONFIG_QSPI_AHB_INIT
  848. qspi_ahb_init();
  849. #endif
  850. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  851. fspi_ahb_init();
  852. #endif
  853. if (IS_ENABLED(CONFIG_DM))
  854. enable_dwc3_snooping();
  855. return fsl_board_late_init();
  856. }
  857. #endif