hikey.c 9.0 KB

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  1. /*
  2. * (C) Copyright 2015 Linaro
  3. * Peter Griffin <peter.griffin@linaro.org>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <dm/platform_data/serial_pl01x.h>
  10. #include <errno.h>
  11. #include <malloc.h>
  12. #include <netdev.h>
  13. #include <asm/io.h>
  14. #include <usb.h>
  15. #include <power/hi6553_pmic.h>
  16. #include <asm-generic/gpio.h>
  17. #include <asm/arch/dwmmc.h>
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch/periph.h>
  20. #include <asm/arch/pinmux.h>
  21. #include <asm/arch/hi6220.h>
  22. #include <asm/armv8/mmu.h>
  23. /*TODO drop this table in favour of device tree */
  24. static const struct hikey_gpio_platdata hi6220_gpio[] = {
  25. { 0, HI6220_GPIO_BASE(0)},
  26. { 1, HI6220_GPIO_BASE(1)},
  27. { 2, HI6220_GPIO_BASE(2)},
  28. { 3, HI6220_GPIO_BASE(3)},
  29. { 4, HI6220_GPIO_BASE(4)},
  30. { 5, HI6220_GPIO_BASE(5)},
  31. { 6, HI6220_GPIO_BASE(6)},
  32. { 7, HI6220_GPIO_BASE(7)},
  33. { 8, HI6220_GPIO_BASE(8)},
  34. { 9, HI6220_GPIO_BASE(9)},
  35. { 10, HI6220_GPIO_BASE(10)},
  36. { 11, HI6220_GPIO_BASE(11)},
  37. { 12, HI6220_GPIO_BASE(12)},
  38. { 13, HI6220_GPIO_BASE(13)},
  39. { 14, HI6220_GPIO_BASE(14)},
  40. { 15, HI6220_GPIO_BASE(15)},
  41. { 16, HI6220_GPIO_BASE(16)},
  42. { 17, HI6220_GPIO_BASE(17)},
  43. { 18, HI6220_GPIO_BASE(18)},
  44. { 19, HI6220_GPIO_BASE(19)},
  45. };
  46. U_BOOT_DEVICES(hi6220_gpios) = {
  47. { "gpio_hi6220", &hi6220_gpio[0] },
  48. { "gpio_hi6220", &hi6220_gpio[1] },
  49. { "gpio_hi6220", &hi6220_gpio[2] },
  50. { "gpio_hi6220", &hi6220_gpio[3] },
  51. { "gpio_hi6220", &hi6220_gpio[4] },
  52. { "gpio_hi6220", &hi6220_gpio[5] },
  53. { "gpio_hi6220", &hi6220_gpio[6] },
  54. { "gpio_hi6220", &hi6220_gpio[7] },
  55. { "gpio_hi6220", &hi6220_gpio[8] },
  56. { "gpio_hi6220", &hi6220_gpio[9] },
  57. { "gpio_hi6220", &hi6220_gpio[10] },
  58. { "gpio_hi6220", &hi6220_gpio[11] },
  59. { "gpio_hi6220", &hi6220_gpio[12] },
  60. { "gpio_hi6220", &hi6220_gpio[13] },
  61. { "gpio_hi6220", &hi6220_gpio[14] },
  62. { "gpio_hi6220", &hi6220_gpio[15] },
  63. { "gpio_hi6220", &hi6220_gpio[16] },
  64. { "gpio_hi6220", &hi6220_gpio[17] },
  65. { "gpio_hi6220", &hi6220_gpio[18] },
  66. { "gpio_hi6220", &hi6220_gpio[19] },
  67. };
  68. DECLARE_GLOBAL_DATA_PTR;
  69. static const struct pl01x_serial_platdata serial_platdata = {
  70. #if CONFIG_CONS_INDEX == 1
  71. .base = HI6220_UART0_BASE,
  72. #elif CONFIG_CONS_INDEX == 4
  73. .base = HI6220_UART3_BASE,
  74. #else
  75. #error "Unsupported console index value."
  76. #endif
  77. .type = TYPE_PL011,
  78. .clock = 19200000
  79. };
  80. U_BOOT_DEVICE(hikey_seriala) = {
  81. .name = "serial_pl01x",
  82. .platdata = &serial_platdata,
  83. };
  84. static struct mm_region hikey_mem_map[] = {
  85. {
  86. .base = 0x0UL,
  87. .size = 0x80000000UL,
  88. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  89. PTE_BLOCK_INNER_SHARE
  90. }, {
  91. .base = 0x80000000UL,
  92. .size = 0x80000000UL,
  93. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  94. PTE_BLOCK_NON_SHARE |
  95. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  96. }, {
  97. /* List terminator */
  98. 0,
  99. }
  100. };
  101. struct mm_region *mem_map = hikey_mem_map;
  102. #ifdef CONFIG_BOARD_EARLY_INIT_F
  103. int board_uart_init(void)
  104. {
  105. switch (CONFIG_CONS_INDEX) {
  106. case 1:
  107. hi6220_pinmux_config(PERIPH_ID_UART0);
  108. break;
  109. case 4:
  110. hi6220_pinmux_config(PERIPH_ID_UART3);
  111. break;
  112. default:
  113. debug("%s: Unsupported UART selected\n", __func__);
  114. return -1;
  115. }
  116. return 0;
  117. }
  118. int board_early_init_f(void)
  119. {
  120. board_uart_init();
  121. return 0;
  122. }
  123. #endif
  124. struct peri_sc_periph_regs *peri_sc =
  125. (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
  126. struct alwayson_sc_regs *ao_sc =
  127. (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
  128. /* status offset from enable reg */
  129. #define STAT_EN_OFF 0x2
  130. void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
  131. {
  132. uint32_t data;
  133. data = readl(clk_base);
  134. data |= bitfield;
  135. writel(bitfield, clk_base);
  136. do {
  137. data = readl(clk_base + STAT_EN_OFF);
  138. } while ((data & bitfield) == 0);
  139. }
  140. /* status offset from disable reg */
  141. #define STAT_DIS_OFF 0x1
  142. void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
  143. {
  144. uint32_t data;
  145. data = readl(clk_base);
  146. data |= bitfield;
  147. writel(data, clk_base);
  148. do {
  149. data = readl(clk_base + STAT_DIS_OFF);
  150. } while (data & bitfield);
  151. }
  152. #define EYE_PATTERN 0x70533483
  153. int board_usb_init(int index, enum usb_init_type init)
  154. {
  155. unsigned int data;
  156. /* enable USB clock */
  157. hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
  158. /* take usb IPs out of reset */
  159. writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
  160. PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
  161. &peri_sc->rst0_dis);
  162. do {
  163. data = readl(&peri_sc->rst0_stat);
  164. data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
  165. PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
  166. } while (data);
  167. /*CTRL 5*/
  168. data = readl(&peri_sc->ctrl5);
  169. data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
  170. data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
  171. data |= 0x300;
  172. writel(data, &peri_sc->ctrl5);
  173. /*CTRL 4*/
  174. /* configure USB PHY */
  175. data = readl(&peri_sc->ctrl4);
  176. /* make PHY out of low power mode */
  177. data &= ~PERI_CTRL4_PICO_SIDDQ;
  178. data &= ~PERI_CTRL4_PICO_OGDISABLE;
  179. data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
  180. writel(data, &peri_sc->ctrl4);
  181. writel(EYE_PATTERN, &peri_sc->ctrl8);
  182. mdelay(5);
  183. return 0;
  184. }
  185. static int config_sd_carddetect(void)
  186. {
  187. int ret;
  188. /* configure GPIO8 as nopull */
  189. writel(0, 0xf8001830);
  190. gpio_request(8, "SD CD");
  191. gpio_direction_input(8);
  192. ret = gpio_get_value(8);
  193. if (!ret) {
  194. printf("%s: SD card present\n", __func__);
  195. return 1;
  196. }
  197. printf("%s: SD card not present\n", __func__);
  198. return 0;
  199. }
  200. static void mmc1_init_pll(void)
  201. {
  202. uint32_t data;
  203. /* select SYSPLL as the source of MMC1 */
  204. /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
  205. writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
  206. do {
  207. data = readl(&peri_sc->clk0_sel);
  208. } while (!(data & (1 << 11)));
  209. /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
  210. writel(1 << 30, &peri_sc->clk0_sel);
  211. do {
  212. data = readl(&peri_sc->clk0_sel);
  213. } while (data & (1 << 14));
  214. hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
  215. hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
  216. do {
  217. /* 1.2GHz / 50 = 24MHz */
  218. writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
  219. data = readl(&peri_sc->clkcfg8bit2);
  220. } while ((data & 0x31) != 0x31);
  221. }
  222. static void mmc1_reset_clk(void)
  223. {
  224. unsigned int data;
  225. /* disable mmc1 bus clock */
  226. hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
  227. /* enable mmc1 bus clock */
  228. hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
  229. /* reset mmc1 clock domain */
  230. writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
  231. /* bypass mmc1 clock phase */
  232. data = readl(&peri_sc->ctrl2);
  233. data |= 3 << 2;
  234. writel(data, &peri_sc->ctrl2);
  235. /* disable low power */
  236. data = readl(&peri_sc->ctrl13);
  237. data |= 1 << 4;
  238. writel(data, &peri_sc->ctrl13);
  239. do {
  240. data = readl(&peri_sc->rst0_stat);
  241. } while (!(data & PERI_RST0_MMC1));
  242. /* unreset mmc0 clock domain */
  243. writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
  244. do {
  245. data = readl(&peri_sc->rst0_stat);
  246. } while (data & PERI_RST0_MMC1);
  247. }
  248. /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
  249. static void hi6220_pmussi_init(void)
  250. {
  251. uint32_t data;
  252. /* Take PMUSSI out of reset */
  253. writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
  254. &ao_sc->rst4_dis);
  255. do {
  256. data = readl(&ao_sc->rst4_stat);
  257. } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
  258. /* set PMU SSI clock latency for read operation */
  259. data = readl(&ao_sc->mcu_subsys_ctrl3);
  260. data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
  261. data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
  262. writel(data, &ao_sc->mcu_subsys_ctrl3);
  263. /* enable PMUSSI clock */
  264. data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
  265. ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
  266. hi6220_clk_enable(data, &ao_sc->clk5_en);
  267. /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
  268. gpio_request(0, "PWR_HOLD_GPIO0_0");
  269. gpio_direction_output(0, 1);
  270. }
  271. int misc_init_r(void)
  272. {
  273. return 0;
  274. }
  275. int board_init(void)
  276. {
  277. return 0;
  278. }
  279. #ifdef CONFIG_GENERIC_MMC
  280. static int init_dwmmc(void)
  281. {
  282. int ret;
  283. #ifdef CONFIG_DWMMC
  284. /* mmc0 clocks are already configured by ATF */
  285. ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
  286. if (ret)
  287. printf("%s: Error configuring pinmux for eMMC (%d)\n"
  288. , __func__, ret);
  289. ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
  290. if (ret)
  291. printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
  292. /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
  293. mmc1_init_pll();
  294. mmc1_reset_clk();
  295. ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
  296. if (ret)
  297. printf("%s: Error configuring pinmux for eMMC (%d)\n"
  298. , __func__, ret);
  299. config_sd_carddetect();
  300. ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
  301. if (ret)
  302. printf("%s: Error adding SD port (%d)\n", __func__, ret);
  303. #endif
  304. return ret;
  305. }
  306. /* setup board specific PMIC */
  307. int power_init_board(void)
  308. {
  309. /* init the hi6220 pmussi ip */
  310. hi6220_pmussi_init();
  311. power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
  312. return 0;
  313. }
  314. int board_mmc_init(bd_t *bis)
  315. {
  316. int ret;
  317. /* add the eMMC and sd ports */
  318. ret = init_dwmmc();
  319. if (ret)
  320. debug("init_dwmmc failed\n");
  321. return ret;
  322. }
  323. #endif
  324. int dram_init(void)
  325. {
  326. gd->ram_size = PHYS_SDRAM_1_SIZE;
  327. return 0;
  328. }
  329. void dram_init_banksize(void)
  330. {
  331. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  332. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  333. }
  334. /* Use the Watchdog to cause reset */
  335. void reset_cpu(ulong addr)
  336. {
  337. /* TODO program the watchdog */
  338. }