musb_hcd.c 27 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Mentor USB OTG Core host controller driver.
  4. *
  5. * Copyright (c) 2008 Texas Instruments
  6. *
  7. * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
  8. */
  9. #include <common.h>
  10. #include <log.h>
  11. #include <usb.h>
  12. #include <linux/delay.h>
  13. #include "musb_hcd.h"
  14. /* MSC control transfers */
  15. #define USB_MSC_BBB_RESET 0xFF
  16. #define USB_MSC_BBB_GET_MAX_LUN 0xFE
  17. /* Endpoint configuration information */
  18. static const struct musb_epinfo epinfo[3] = {
  19. {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
  20. {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
  21. {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
  22. };
  23. /* --- Virtual Root Hub ---------------------------------------------------- */
  24. #ifdef MUSB_NO_MULTIPOINT
  25. static int rh_devnum;
  26. static u32 port_status;
  27. #include <usbroothubdes.h>
  28. #endif
  29. /*
  30. * This function writes the data toggle value.
  31. */
  32. static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
  33. {
  34. u16 toggle = usb_gettoggle(dev, ep, dir_out);
  35. u16 csr;
  36. if (dir_out) {
  37. csr = readw(&musbr->txcsr);
  38. if (!toggle) {
  39. if (csr & MUSB_TXCSR_MODE)
  40. csr = MUSB_TXCSR_CLRDATATOG;
  41. else
  42. csr = 0;
  43. writew(csr, &musbr->txcsr);
  44. } else {
  45. csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
  46. writew(csr, &musbr->txcsr);
  47. csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
  48. writew(csr, &musbr->txcsr);
  49. }
  50. } else {
  51. if (!toggle) {
  52. csr = readw(&musbr->txcsr);
  53. if (csr & MUSB_TXCSR_MODE)
  54. csr = MUSB_RXCSR_CLRDATATOG;
  55. else
  56. csr = 0;
  57. writew(csr, &musbr->rxcsr);
  58. } else {
  59. csr = readw(&musbr->rxcsr);
  60. csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
  61. writew(csr, &musbr->rxcsr);
  62. csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
  63. writew(csr, &musbr->rxcsr);
  64. }
  65. }
  66. }
  67. /*
  68. * This function checks if RxStall has occurred on the endpoint. If a RxStall
  69. * has occurred, the RxStall is cleared and 1 is returned. If RxStall has
  70. * not occurred, 0 is returned.
  71. */
  72. static u8 check_stall(u8 ep, u8 dir_out)
  73. {
  74. u16 csr;
  75. /* For endpoint 0 */
  76. if (!ep) {
  77. csr = readw(&musbr->txcsr);
  78. if (csr & MUSB_CSR0_H_RXSTALL) {
  79. csr &= ~MUSB_CSR0_H_RXSTALL;
  80. writew(csr, &musbr->txcsr);
  81. return 1;
  82. }
  83. } else { /* For non-ep0 */
  84. if (dir_out) { /* is it tx ep */
  85. csr = readw(&musbr->txcsr);
  86. if (csr & MUSB_TXCSR_H_RXSTALL) {
  87. csr &= ~MUSB_TXCSR_H_RXSTALL;
  88. writew(csr, &musbr->txcsr);
  89. return 1;
  90. }
  91. } else { /* is it rx ep */
  92. csr = readw(&musbr->rxcsr);
  93. if (csr & MUSB_RXCSR_H_RXSTALL) {
  94. csr &= ~MUSB_RXCSR_H_RXSTALL;
  95. writew(csr, &musbr->rxcsr);
  96. return 1;
  97. }
  98. }
  99. }
  100. return 0;
  101. }
  102. /*
  103. * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
  104. * error and -2 for stall.
  105. */
  106. static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
  107. {
  108. u16 csr;
  109. int result = 1;
  110. int timeout = CONFIG_USB_MUSB_TIMEOUT;
  111. while (result > 0) {
  112. csr = readw(&musbr->txcsr);
  113. if (csr & MUSB_CSR0_H_ERROR) {
  114. csr &= ~MUSB_CSR0_H_ERROR;
  115. writew(csr, &musbr->txcsr);
  116. dev->status = USB_ST_CRC_ERR;
  117. result = -1;
  118. break;
  119. }
  120. switch (bit_mask) {
  121. case MUSB_CSR0_TXPKTRDY:
  122. if (!(csr & MUSB_CSR0_TXPKTRDY)) {
  123. if (check_stall(MUSB_CONTROL_EP, 0)) {
  124. dev->status = USB_ST_STALLED;
  125. result = -2;
  126. } else
  127. result = 0;
  128. }
  129. break;
  130. case MUSB_CSR0_RXPKTRDY:
  131. if (check_stall(MUSB_CONTROL_EP, 0)) {
  132. dev->status = USB_ST_STALLED;
  133. result = -2;
  134. } else
  135. if (csr & MUSB_CSR0_RXPKTRDY)
  136. result = 0;
  137. break;
  138. case MUSB_CSR0_H_REQPKT:
  139. if (!(csr & MUSB_CSR0_H_REQPKT)) {
  140. if (check_stall(MUSB_CONTROL_EP, 0)) {
  141. dev->status = USB_ST_STALLED;
  142. result = -2;
  143. } else
  144. result = 0;
  145. }
  146. break;
  147. }
  148. /* Check the timeout */
  149. if (--timeout)
  150. udelay(1);
  151. else {
  152. dev->status = USB_ST_CRC_ERR;
  153. result = -1;
  154. break;
  155. }
  156. }
  157. return result;
  158. }
  159. /*
  160. * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
  161. */
  162. static int wait_until_txep_ready(struct usb_device *dev, u8 ep)
  163. {
  164. u16 csr;
  165. int timeout = CONFIG_USB_MUSB_TIMEOUT;
  166. do {
  167. if (check_stall(ep, 1)) {
  168. dev->status = USB_ST_STALLED;
  169. return 0;
  170. }
  171. csr = readw(&musbr->txcsr);
  172. if (csr & MUSB_TXCSR_H_ERROR) {
  173. dev->status = USB_ST_CRC_ERR;
  174. return 0;
  175. }
  176. /* Check the timeout */
  177. if (--timeout)
  178. udelay(1);
  179. else {
  180. dev->status = USB_ST_CRC_ERR;
  181. return -1;
  182. }
  183. } while (csr & MUSB_TXCSR_TXPKTRDY);
  184. return 1;
  185. }
  186. /*
  187. * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
  188. */
  189. static int wait_until_rxep_ready(struct usb_device *dev, u8 ep)
  190. {
  191. u16 csr;
  192. int timeout = CONFIG_USB_MUSB_TIMEOUT;
  193. do {
  194. if (check_stall(ep, 0)) {
  195. dev->status = USB_ST_STALLED;
  196. return 0;
  197. }
  198. csr = readw(&musbr->rxcsr);
  199. if (csr & MUSB_RXCSR_H_ERROR) {
  200. dev->status = USB_ST_CRC_ERR;
  201. return 0;
  202. }
  203. /* Check the timeout */
  204. if (--timeout)
  205. udelay(1);
  206. else {
  207. dev->status = USB_ST_CRC_ERR;
  208. return -1;
  209. }
  210. } while (!(csr & MUSB_RXCSR_RXPKTRDY));
  211. return 1;
  212. }
  213. /*
  214. * This function performs the setup phase of the control transfer
  215. */
  216. static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
  217. {
  218. int result;
  219. u16 csr;
  220. /* write the control request to ep0 fifo */
  221. write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
  222. /* enable transfer of setup packet */
  223. csr = readw(&musbr->txcsr);
  224. csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
  225. writew(csr, &musbr->txcsr);
  226. /* wait until the setup packet is transmitted */
  227. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  228. dev->act_len = 0;
  229. return result;
  230. }
  231. /*
  232. * This function handles the control transfer in data phase
  233. */
  234. static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
  235. {
  236. u16 csr;
  237. u32 rxlen = 0;
  238. u32 nextlen = 0;
  239. u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
  240. u8 *rxbuff = (u8 *)buffer;
  241. u8 rxedlength;
  242. int result;
  243. while (rxlen < len) {
  244. /* Determine the next read length */
  245. nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
  246. /* Set the ReqPkt bit */
  247. csr = readw(&musbr->txcsr);
  248. writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
  249. result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
  250. if (result < 0)
  251. return result;
  252. /* Actual number of bytes received by usb */
  253. rxedlength = readb(&musbr->rxcount);
  254. /* Read the data from the RxFIFO */
  255. read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
  256. /* Clear the RxPktRdy Bit */
  257. csr = readw(&musbr->txcsr);
  258. csr &= ~MUSB_CSR0_RXPKTRDY;
  259. writew(csr, &musbr->txcsr);
  260. /* short packet? */
  261. if (rxedlength != nextlen) {
  262. dev->act_len += rxedlength;
  263. break;
  264. }
  265. rxlen += nextlen;
  266. dev->act_len = rxlen;
  267. }
  268. return 0;
  269. }
  270. /*
  271. * This function handles the control transfer out data phase
  272. */
  273. static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
  274. {
  275. u16 csr;
  276. u32 txlen = 0;
  277. u32 nextlen = 0;
  278. u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
  279. u8 *txbuff = (u8 *)buffer;
  280. int result = 0;
  281. while (txlen < len) {
  282. /* Determine the next write length */
  283. nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
  284. /* Load the data to send in FIFO */
  285. write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
  286. /* Set TXPKTRDY bit */
  287. csr = readw(&musbr->txcsr);
  288. csr |= MUSB_CSR0_TXPKTRDY;
  289. csr |= MUSB_CSR0_H_DIS_PING;
  290. writew(csr, &musbr->txcsr);
  291. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  292. if (result < 0)
  293. break;
  294. txlen += nextlen;
  295. dev->act_len = txlen;
  296. }
  297. return result;
  298. }
  299. /*
  300. * This function handles the control transfer out status phase
  301. */
  302. static int ctrlreq_out_status_phase(struct usb_device *dev)
  303. {
  304. u16 csr;
  305. int result;
  306. /* Set the StatusPkt bit */
  307. csr = readw(&musbr->txcsr);
  308. csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
  309. csr |= MUSB_CSR0_H_DIS_PING;
  310. writew(csr, &musbr->txcsr);
  311. /* Wait until TXPKTRDY bit is cleared */
  312. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  313. return result;
  314. }
  315. /*
  316. * This function handles the control transfer in status phase
  317. */
  318. static int ctrlreq_in_status_phase(struct usb_device *dev)
  319. {
  320. u16 csr;
  321. int result;
  322. /* Set the StatusPkt bit and ReqPkt bit */
  323. csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
  324. csr |= MUSB_CSR0_H_DIS_PING;
  325. writew(csr, &musbr->txcsr);
  326. result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
  327. /* clear StatusPkt bit and RxPktRdy bit */
  328. csr = readw(&musbr->txcsr);
  329. csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
  330. writew(csr, &musbr->txcsr);
  331. return result;
  332. }
  333. /*
  334. * determines the speed of the device (High/Full/Slow)
  335. */
  336. static u8 get_dev_speed(struct usb_device *dev)
  337. {
  338. return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
  339. ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
  340. MUSB_TYPE_SPEED_FULL);
  341. }
  342. /*
  343. * configure the hub address and the port address.
  344. */
  345. static void config_hub_port(struct usb_device *dev, u8 ep)
  346. {
  347. u8 chid;
  348. u8 hub;
  349. /* Find out the nearest parent which is high speed */
  350. while (dev->parent->parent != NULL)
  351. if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
  352. dev = dev->parent;
  353. else
  354. break;
  355. /* determine the port address at that hub */
  356. hub = dev->parent->devnum;
  357. for (chid = 0; chid < USB_MAXCHILDREN; chid++)
  358. if (dev->parent->children[chid] == dev)
  359. break;
  360. #ifndef MUSB_NO_MULTIPOINT
  361. /* configure the hub address and the port address */
  362. writeb(hub, &musbr->tar[ep].txhubaddr);
  363. writeb((chid + 1), &musbr->tar[ep].txhubport);
  364. writeb(hub, &musbr->tar[ep].rxhubaddr);
  365. writeb((chid + 1), &musbr->tar[ep].rxhubport);
  366. #endif
  367. }
  368. #ifdef MUSB_NO_MULTIPOINT
  369. static void musb_port_reset(int do_reset)
  370. {
  371. u8 power = readb(&musbr->power);
  372. if (do_reset) {
  373. power &= 0xf0;
  374. writeb(power | MUSB_POWER_RESET, &musbr->power);
  375. port_status |= USB_PORT_STAT_RESET;
  376. port_status &= ~USB_PORT_STAT_ENABLE;
  377. udelay(30000);
  378. } else {
  379. writeb(power & ~MUSB_POWER_RESET, &musbr->power);
  380. power = readb(&musbr->power);
  381. if (power & MUSB_POWER_HSMODE)
  382. port_status |= USB_PORT_STAT_HIGH_SPEED;
  383. port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
  384. port_status |= USB_PORT_STAT_ENABLE
  385. | (USB_PORT_STAT_C_RESET << 16)
  386. | (USB_PORT_STAT_C_ENABLE << 16);
  387. }
  388. }
  389. /*
  390. * root hub control
  391. */
  392. static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  393. void *buffer, int transfer_len,
  394. struct devrequest *cmd)
  395. {
  396. int leni = transfer_len;
  397. int len = 0;
  398. int stat = 0;
  399. u32 datab[4];
  400. const u8 *data_buf = (u8 *) datab;
  401. u16 bmRType_bReq;
  402. u16 wValue;
  403. u16 wIndex;
  404. u16 wLength;
  405. u16 int_usb;
  406. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  407. debug("Root-Hub submit IRQ: NOT implemented\n");
  408. return 0;
  409. }
  410. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  411. wValue = swap_16(cmd->value);
  412. wIndex = swap_16(cmd->index);
  413. wLength = swap_16(cmd->length);
  414. debug("--- HUB ----------------------------------------\n");
  415. debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
  416. bmRType_bReq, wValue, wIndex, wLength);
  417. debug("------------------------------------------------\n");
  418. switch (bmRType_bReq) {
  419. case RH_GET_STATUS:
  420. debug("RH_GET_STATUS\n");
  421. *(__u16 *) data_buf = swap_16(1);
  422. len = 2;
  423. break;
  424. case RH_GET_STATUS | RH_INTERFACE:
  425. debug("RH_GET_STATUS | RH_INTERFACE\n");
  426. *(__u16 *) data_buf = swap_16(0);
  427. len = 2;
  428. break;
  429. case RH_GET_STATUS | RH_ENDPOINT:
  430. debug("RH_GET_STATUS | RH_ENDPOINT\n");
  431. *(__u16 *) data_buf = swap_16(0);
  432. len = 2;
  433. break;
  434. case RH_GET_STATUS | RH_CLASS:
  435. debug("RH_GET_STATUS | RH_CLASS\n");
  436. *(__u32 *) data_buf = swap_32(0);
  437. len = 4;
  438. break;
  439. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  440. debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
  441. int_usb = readw(&musbr->intrusb);
  442. if (int_usb & MUSB_INTR_CONNECT) {
  443. port_status |= USB_PORT_STAT_CONNECTION
  444. | (USB_PORT_STAT_C_CONNECTION << 16);
  445. port_status |= USB_PORT_STAT_HIGH_SPEED
  446. | USB_PORT_STAT_ENABLE;
  447. }
  448. if (port_status & USB_PORT_STAT_RESET)
  449. musb_port_reset(0);
  450. *(__u32 *) data_buf = swap_32(port_status);
  451. len = 4;
  452. break;
  453. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  454. debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
  455. switch (wValue) {
  456. case RH_ENDPOINT_STALL:
  457. debug("C_HUB_ENDPOINT_STALL\n");
  458. len = 0;
  459. break;
  460. }
  461. port_status &= ~(1 << wValue);
  462. break;
  463. case RH_CLEAR_FEATURE | RH_CLASS:
  464. debug("RH_CLEAR_FEATURE | RH_CLASS\n");
  465. switch (wValue) {
  466. case RH_C_HUB_LOCAL_POWER:
  467. debug("C_HUB_LOCAL_POWER\n");
  468. len = 0;
  469. break;
  470. case RH_C_HUB_OVER_CURRENT:
  471. debug("C_HUB_OVER_CURRENT\n");
  472. len = 0;
  473. break;
  474. }
  475. port_status &= ~(1 << wValue);
  476. break;
  477. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  478. debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
  479. switch (wValue) {
  480. case RH_PORT_ENABLE:
  481. len = 0;
  482. break;
  483. case RH_PORT_SUSPEND:
  484. len = 0;
  485. break;
  486. case RH_PORT_POWER:
  487. len = 0;
  488. break;
  489. case RH_C_PORT_CONNECTION:
  490. len = 0;
  491. break;
  492. case RH_C_PORT_ENABLE:
  493. len = 0;
  494. break;
  495. case RH_C_PORT_SUSPEND:
  496. len = 0;
  497. break;
  498. case RH_C_PORT_OVER_CURRENT:
  499. len = 0;
  500. break;
  501. case RH_C_PORT_RESET:
  502. len = 0;
  503. break;
  504. default:
  505. debug("invalid wValue\n");
  506. stat = USB_ST_STALLED;
  507. }
  508. port_status &= ~(1 << wValue);
  509. break;
  510. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  511. debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
  512. switch (wValue) {
  513. case RH_PORT_SUSPEND:
  514. len = 0;
  515. break;
  516. case RH_PORT_RESET:
  517. musb_port_reset(1);
  518. len = 0;
  519. break;
  520. case RH_PORT_POWER:
  521. len = 0;
  522. break;
  523. case RH_PORT_ENABLE:
  524. len = 0;
  525. break;
  526. default:
  527. debug("invalid wValue\n");
  528. stat = USB_ST_STALLED;
  529. }
  530. port_status |= 1 << wValue;
  531. break;
  532. case RH_SET_ADDRESS:
  533. debug("RH_SET_ADDRESS\n");
  534. rh_devnum = wValue;
  535. len = 0;
  536. break;
  537. case RH_GET_DESCRIPTOR:
  538. debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
  539. switch (wValue) {
  540. case (USB_DT_DEVICE << 8): /* device descriptor */
  541. len = min_t(unsigned int,
  542. leni, min_t(unsigned int,
  543. sizeof(root_hub_dev_des),
  544. wLength));
  545. data_buf = root_hub_dev_des;
  546. break;
  547. case (USB_DT_CONFIG << 8): /* configuration descriptor */
  548. len = min_t(unsigned int,
  549. leni, min_t(unsigned int,
  550. sizeof(root_hub_config_des),
  551. wLength));
  552. data_buf = root_hub_config_des;
  553. break;
  554. case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
  555. len = min_t(unsigned int,
  556. leni, min_t(unsigned int,
  557. sizeof(root_hub_str_index0),
  558. wLength));
  559. data_buf = root_hub_str_index0;
  560. break;
  561. case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
  562. len = min_t(unsigned int,
  563. leni, min_t(unsigned int,
  564. sizeof(root_hub_str_index1),
  565. wLength));
  566. data_buf = root_hub_str_index1;
  567. break;
  568. default:
  569. debug("invalid wValue\n");
  570. stat = USB_ST_STALLED;
  571. }
  572. break;
  573. case RH_GET_DESCRIPTOR | RH_CLASS: {
  574. u8 *_data_buf = (u8 *) datab;
  575. debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
  576. _data_buf[0] = 0x09; /* min length; */
  577. _data_buf[1] = 0x29;
  578. _data_buf[2] = 0x1; /* 1 port */
  579. _data_buf[3] = 0x01; /* per-port power switching */
  580. _data_buf[3] |= 0x10; /* no overcurrent reporting */
  581. /* Corresponds to data_buf[4-7] */
  582. _data_buf[4] = 0;
  583. _data_buf[5] = 5;
  584. _data_buf[6] = 0;
  585. _data_buf[7] = 0x02;
  586. _data_buf[8] = 0xff;
  587. len = min_t(unsigned int, leni,
  588. min_t(unsigned int, data_buf[0], wLength));
  589. break;
  590. }
  591. case RH_GET_CONFIGURATION:
  592. debug("RH_GET_CONFIGURATION\n");
  593. *(__u8 *) data_buf = 0x01;
  594. len = 1;
  595. break;
  596. case RH_SET_CONFIGURATION:
  597. debug("RH_SET_CONFIGURATION\n");
  598. len = 0;
  599. break;
  600. default:
  601. debug("*** *** *** unsupported root hub command *** *** ***\n");
  602. stat = USB_ST_STALLED;
  603. }
  604. len = min_t(int, len, leni);
  605. if (buffer != data_buf)
  606. memcpy(buffer, data_buf, len);
  607. dev->act_len = len;
  608. dev->status = stat;
  609. debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
  610. return stat;
  611. }
  612. static void musb_rh_init(void)
  613. {
  614. rh_devnum = 0;
  615. port_status = 0;
  616. }
  617. #else
  618. static void musb_rh_init(void) {}
  619. #endif
  620. /*
  621. * do a control transfer
  622. */
  623. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  624. int len, struct devrequest *setup)
  625. {
  626. int devnum = usb_pipedevice(pipe);
  627. u8 devspeed;
  628. #ifdef MUSB_NO_MULTIPOINT
  629. /* Control message is for the HUB? */
  630. if (devnum == rh_devnum) {
  631. int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
  632. if (stat)
  633. return stat;
  634. }
  635. #endif
  636. /* select control endpoint */
  637. writeb(MUSB_CONTROL_EP, &musbr->index);
  638. readw(&musbr->txcsr);
  639. #ifndef MUSB_NO_MULTIPOINT
  640. /* target addr and (for multipoint) hub addr/port */
  641. writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
  642. writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
  643. #endif
  644. /* configure the hub address and the port number as required */
  645. devspeed = get_dev_speed(dev);
  646. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  647. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  648. config_hub_port(dev, MUSB_CONTROL_EP);
  649. writeb(devspeed << 6, &musbr->txtype);
  650. } else {
  651. writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
  652. #ifndef MUSB_NO_MULTIPOINT
  653. writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
  654. writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
  655. writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
  656. writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
  657. #endif
  658. }
  659. /* Control transfer setup phase */
  660. if (ctrlreq_setup_phase(dev, setup) < 0)
  661. return 0;
  662. switch (setup->request) {
  663. case USB_REQ_GET_DESCRIPTOR:
  664. case USB_REQ_GET_CONFIGURATION:
  665. case USB_REQ_GET_INTERFACE:
  666. case USB_REQ_GET_STATUS:
  667. case USB_MSC_BBB_GET_MAX_LUN:
  668. /* control transfer in-data-phase */
  669. if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
  670. return 0;
  671. /* control transfer out-status-phase */
  672. if (ctrlreq_out_status_phase(dev) < 0)
  673. return 0;
  674. break;
  675. case USB_REQ_SET_ADDRESS:
  676. case USB_REQ_SET_CONFIGURATION:
  677. case USB_REQ_SET_FEATURE:
  678. case USB_REQ_SET_INTERFACE:
  679. case USB_REQ_CLEAR_FEATURE:
  680. case USB_MSC_BBB_RESET:
  681. /* control transfer in status phase */
  682. if (ctrlreq_in_status_phase(dev) < 0)
  683. return 0;
  684. break;
  685. case USB_REQ_SET_DESCRIPTOR:
  686. /* control transfer out data phase */
  687. if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
  688. return 0;
  689. /* control transfer in status phase */
  690. if (ctrlreq_in_status_phase(dev) < 0)
  691. return 0;
  692. break;
  693. default:
  694. /* unhandled control transfer */
  695. return -1;
  696. }
  697. dev->status = 0;
  698. dev->act_len = len;
  699. #ifdef MUSB_NO_MULTIPOINT
  700. /* Set device address to USB_FADDR register */
  701. if (setup->request == USB_REQ_SET_ADDRESS)
  702. writeb(dev->devnum, &musbr->faddr);
  703. #endif
  704. return len;
  705. }
  706. /*
  707. * do a bulk transfer
  708. */
  709. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  710. void *buffer, int len)
  711. {
  712. int dir_out = usb_pipeout(pipe);
  713. int ep = usb_pipeendpoint(pipe);
  714. #ifndef MUSB_NO_MULTIPOINT
  715. int devnum = usb_pipedevice(pipe);
  716. #endif
  717. u8 type;
  718. u16 csr;
  719. u32 txlen = 0;
  720. u32 nextlen = 0;
  721. u8 devspeed;
  722. /* select bulk endpoint */
  723. writeb(MUSB_BULK_EP, &musbr->index);
  724. #ifndef MUSB_NO_MULTIPOINT
  725. /* write the address of the device */
  726. if (dir_out)
  727. writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
  728. else
  729. writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
  730. #endif
  731. /* configure the hub address and the port number as required */
  732. devspeed = get_dev_speed(dev);
  733. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  734. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  735. /*
  736. * MUSB is in high speed and the destination device is full
  737. * speed device. So configure the hub address and port
  738. * address registers.
  739. */
  740. config_hub_port(dev, MUSB_BULK_EP);
  741. } else {
  742. #ifndef MUSB_NO_MULTIPOINT
  743. if (dir_out) {
  744. writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
  745. writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
  746. } else {
  747. writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
  748. writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
  749. }
  750. #endif
  751. devspeed = musb_cfg.musb_speed;
  752. }
  753. /* Write the saved toggle bit value */
  754. write_toggle(dev, ep, dir_out);
  755. if (dir_out) { /* bulk-out transfer */
  756. /* Program the TxType register */
  757. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  758. (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
  759. (ep & MUSB_TYPE_REMOTE_END);
  760. writeb(type, &musbr->txtype);
  761. /* Write maximum packet size to the TxMaxp register */
  762. writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
  763. while (txlen < len) {
  764. nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
  765. (len-txlen) : dev->epmaxpacketout[ep];
  766. /* Write the data to the FIFO */
  767. write_fifo(MUSB_BULK_EP, nextlen,
  768. (void *)(((u8 *)buffer) + txlen));
  769. /* Set the TxPktRdy bit */
  770. csr = readw(&musbr->txcsr);
  771. writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
  772. /* Wait until the TxPktRdy bit is cleared */
  773. if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) {
  774. readw(&musbr->txcsr);
  775. usb_settoggle(dev, ep, dir_out,
  776. (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
  777. dev->act_len = txlen;
  778. return 0;
  779. }
  780. txlen += nextlen;
  781. }
  782. /* Keep a copy of the data toggle bit */
  783. csr = readw(&musbr->txcsr);
  784. usb_settoggle(dev, ep, dir_out,
  785. (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
  786. } else { /* bulk-in transfer */
  787. /* Write the saved toggle bit value */
  788. write_toggle(dev, ep, dir_out);
  789. /* Program the RxType register */
  790. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  791. (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
  792. (ep & MUSB_TYPE_REMOTE_END);
  793. writeb(type, &musbr->rxtype);
  794. /* Write the maximum packet size to the RxMaxp register */
  795. writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
  796. while (txlen < len) {
  797. nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
  798. (len-txlen) : dev->epmaxpacketin[ep];
  799. /* Set the ReqPkt bit */
  800. csr = readw(&musbr->rxcsr);
  801. writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
  802. /* Wait until the RxPktRdy bit is set */
  803. if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) {
  804. csr = readw(&musbr->rxcsr);
  805. usb_settoggle(dev, ep, dir_out,
  806. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  807. csr &= ~MUSB_RXCSR_RXPKTRDY;
  808. writew(csr, &musbr->rxcsr);
  809. dev->act_len = txlen;
  810. return 0;
  811. }
  812. /* Read the data from the FIFO */
  813. read_fifo(MUSB_BULK_EP, nextlen,
  814. (void *)(((u8 *)buffer) + txlen));
  815. /* Clear the RxPktRdy bit */
  816. csr = readw(&musbr->rxcsr);
  817. csr &= ~MUSB_RXCSR_RXPKTRDY;
  818. writew(csr, &musbr->rxcsr);
  819. txlen += nextlen;
  820. }
  821. /* Keep a copy of the data toggle bit */
  822. csr = readw(&musbr->rxcsr);
  823. usb_settoggle(dev, ep, dir_out,
  824. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  825. }
  826. /* bulk transfer is complete */
  827. dev->status = 0;
  828. dev->act_len = len;
  829. return 0;
  830. }
  831. /*
  832. * This function initializes the usb controller module.
  833. */
  834. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  835. {
  836. u8 power;
  837. u32 timeout;
  838. musb_rh_init();
  839. if (musb_platform_init() == -1)
  840. return -1;
  841. /* Configure all the endpoint FIFO's and start usb controller */
  842. musbr = musb_cfg.regs;
  843. musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
  844. musb_start();
  845. /*
  846. * Wait until musb is enabled in host mode with a timeout. There
  847. * should be a usb device connected.
  848. */
  849. timeout = musb_cfg.timeout;
  850. while (--timeout)
  851. if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
  852. break;
  853. /* if musb core is not in host mode, then return */
  854. if (!timeout)
  855. return -1;
  856. /* start usb bus reset */
  857. power = readb(&musbr->power);
  858. writeb(power | MUSB_POWER_RESET, &musbr->power);
  859. /* After initiating a usb reset, wait for about 20ms to 30ms */
  860. udelay(30000);
  861. /* stop usb bus reset */
  862. power = readb(&musbr->power);
  863. power &= ~MUSB_POWER_RESET;
  864. writeb(power, &musbr->power);
  865. /* Determine if the connected device is a high/full/low speed device */
  866. musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
  867. MUSB_TYPE_SPEED_HIGH :
  868. ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
  869. MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
  870. return 0;
  871. }
  872. /*
  873. * This function stops the operation of the davinci usb module.
  874. */
  875. int usb_lowlevel_stop(int index)
  876. {
  877. /* Reset the USB module */
  878. musb_platform_deinit();
  879. writeb(0, &musbr->devctl);
  880. return 0;
  881. }
  882. /*
  883. * This function supports usb interrupt transfers. Currently, usb interrupt
  884. * transfers are not supported.
  885. */
  886. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  887. int len, int interval, bool nonblock)
  888. {
  889. int dir_out = usb_pipeout(pipe);
  890. int ep = usb_pipeendpoint(pipe);
  891. #ifndef MUSB_NO_MULTIPOINT
  892. int devnum = usb_pipedevice(pipe);
  893. #endif
  894. u8 type;
  895. u16 csr;
  896. u32 txlen = 0;
  897. u32 nextlen = 0;
  898. u8 devspeed;
  899. /* select interrupt endpoint */
  900. writeb(MUSB_INTR_EP, &musbr->index);
  901. #ifndef MUSB_NO_MULTIPOINT
  902. /* write the address of the device */
  903. if (dir_out)
  904. writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
  905. else
  906. writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
  907. #endif
  908. /* configure the hub address and the port number as required */
  909. devspeed = get_dev_speed(dev);
  910. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  911. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  912. /*
  913. * MUSB is in high speed and the destination device is full
  914. * speed device. So configure the hub address and port
  915. * address registers.
  916. */
  917. config_hub_port(dev, MUSB_INTR_EP);
  918. } else {
  919. #ifndef MUSB_NO_MULTIPOINT
  920. if (dir_out) {
  921. writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
  922. writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
  923. } else {
  924. writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
  925. writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
  926. }
  927. #endif
  928. devspeed = musb_cfg.musb_speed;
  929. }
  930. /* Write the saved toggle bit value */
  931. write_toggle(dev, ep, dir_out);
  932. if (!dir_out) { /* intrrupt-in transfer */
  933. /* Write the saved toggle bit value */
  934. write_toggle(dev, ep, dir_out);
  935. writeb(interval, &musbr->rxinterval);
  936. /* Program the RxType register */
  937. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  938. (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
  939. (ep & MUSB_TYPE_REMOTE_END);
  940. writeb(type, &musbr->rxtype);
  941. /* Write the maximum packet size to the RxMaxp register */
  942. writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
  943. while (txlen < len) {
  944. nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
  945. (len-txlen) : dev->epmaxpacketin[ep];
  946. /* Set the ReqPkt bit */
  947. csr = readw(&musbr->rxcsr);
  948. writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
  949. /* Wait until the RxPktRdy bit is set */
  950. if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) {
  951. csr = readw(&musbr->rxcsr);
  952. usb_settoggle(dev, ep, dir_out,
  953. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  954. csr &= ~MUSB_RXCSR_RXPKTRDY;
  955. writew(csr, &musbr->rxcsr);
  956. dev->act_len = txlen;
  957. return 0;
  958. }
  959. /* Read the data from the FIFO */
  960. read_fifo(MUSB_INTR_EP, nextlen,
  961. (void *)(((u8 *)buffer) + txlen));
  962. /* Clear the RxPktRdy bit */
  963. csr = readw(&musbr->rxcsr);
  964. csr &= ~MUSB_RXCSR_RXPKTRDY;
  965. writew(csr, &musbr->rxcsr);
  966. txlen += nextlen;
  967. }
  968. /* Keep a copy of the data toggle bit */
  969. csr = readw(&musbr->rxcsr);
  970. usb_settoggle(dev, ep, dir_out,
  971. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  972. }
  973. /* interrupt transfer is complete */
  974. dev->irq_status = 0;
  975. dev->irq_act_len = len;
  976. dev->irq_handle(dev);
  977. dev->status = 0;
  978. dev->act_len = len;
  979. return 0;
  980. }