musb_regs.h 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * MUSB OTG driver register defines
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. */
  9. #ifndef __MUSB_REGS_H__
  10. #define __MUSB_REGS_H__
  11. #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
  12. /*
  13. * MUSB Register bits
  14. */
  15. /* POWER */
  16. #define MUSB_POWER_ISOUPDATE 0x80
  17. #define MUSB_POWER_SOFTCONN 0x40
  18. #define MUSB_POWER_HSENAB 0x20
  19. #define MUSB_POWER_HSMODE 0x10
  20. #define MUSB_POWER_RESET 0x08
  21. #define MUSB_POWER_RESUME 0x04
  22. #define MUSB_POWER_SUSPENDM 0x02
  23. #define MUSB_POWER_ENSUSPEND 0x01
  24. /* INTRUSB */
  25. #define MUSB_INTR_SUSPEND 0x01
  26. #define MUSB_INTR_RESUME 0x02
  27. #define MUSB_INTR_RESET 0x04
  28. #define MUSB_INTR_BABBLE 0x04
  29. #define MUSB_INTR_SOF 0x08
  30. #define MUSB_INTR_CONNECT 0x10
  31. #define MUSB_INTR_DISCONNECT 0x20
  32. #define MUSB_INTR_SESSREQ 0x40
  33. #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
  34. /* DEVCTL */
  35. #define MUSB_DEVCTL_BDEVICE 0x80
  36. #define MUSB_DEVCTL_FSDEV 0x40
  37. #define MUSB_DEVCTL_LSDEV 0x20
  38. #define MUSB_DEVCTL_VBUS 0x18
  39. #define MUSB_DEVCTL_VBUS_SHIFT 3
  40. #define MUSB_DEVCTL_HM 0x04
  41. #define MUSB_DEVCTL_HR 0x02
  42. #define MUSB_DEVCTL_SESSION 0x01
  43. /* MUSB ULPI VBUSCONTROL */
  44. #define MUSB_ULPI_USE_EXTVBUS 0x01
  45. #define MUSB_ULPI_USE_EXTVBUSIND 0x02
  46. /* ULPI_REG_CONTROL */
  47. #define MUSB_ULPI_REG_REQ (1 << 0)
  48. #define MUSB_ULPI_REG_CMPLT (1 << 1)
  49. #define MUSB_ULPI_RDN_WR (1 << 2)
  50. /* TESTMODE */
  51. #define MUSB_TEST_FORCE_HOST 0x80
  52. #define MUSB_TEST_FIFO_ACCESS 0x40
  53. #define MUSB_TEST_FORCE_FS 0x20
  54. #define MUSB_TEST_FORCE_HS 0x10
  55. #define MUSB_TEST_PACKET 0x08
  56. #define MUSB_TEST_K 0x04
  57. #define MUSB_TEST_J 0x02
  58. #define MUSB_TEST_SE0_NAK 0x01
  59. /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
  60. #define MUSB_FIFOSZ_DPB 0x10
  61. /* Allocation size (8, 16, 32, ... 4096) */
  62. #define MUSB_FIFOSZ_SIZE 0x0f
  63. /* CSR0 */
  64. #define MUSB_CSR0_FLUSHFIFO 0x0100
  65. #define MUSB_CSR0_TXPKTRDY 0x0002
  66. #define MUSB_CSR0_RXPKTRDY 0x0001
  67. /* CSR0 in Peripheral mode */
  68. #define MUSB_CSR0_P_SVDSETUPEND 0x0080
  69. #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
  70. #define MUSB_CSR0_P_SENDSTALL 0x0020
  71. #define MUSB_CSR0_P_SETUPEND 0x0010
  72. #define MUSB_CSR0_P_DATAEND 0x0008
  73. #define MUSB_CSR0_P_SENTSTALL 0x0004
  74. /* CSR0 in Host mode */
  75. #define MUSB_CSR0_H_DIS_PING 0x0800
  76. #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
  77. #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
  78. #define MUSB_CSR0_H_NAKTIMEOUT 0x0080
  79. #define MUSB_CSR0_H_STATUSPKT 0x0040
  80. #define MUSB_CSR0_H_REQPKT 0x0020
  81. #define MUSB_CSR0_H_ERROR 0x0010
  82. #define MUSB_CSR0_H_SETUPPKT 0x0008
  83. #define MUSB_CSR0_H_RXSTALL 0x0004
  84. /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
  85. #define MUSB_CSR0_P_WZC_BITS \
  86. (MUSB_CSR0_P_SENTSTALL)
  87. #define MUSB_CSR0_H_WZC_BITS \
  88. (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
  89. | MUSB_CSR0_RXPKTRDY)
  90. /* TxType/RxType */
  91. #define MUSB_TYPE_SPEED 0xc0
  92. #define MUSB_TYPE_SPEED_SHIFT 6
  93. #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
  94. #define MUSB_TYPE_PROTO_SHIFT 4
  95. #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
  96. /* CONFIGDATA */
  97. #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
  98. #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
  99. #define MUSB_CONFIGDATA_BIGENDIAN 0x20
  100. #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
  101. #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
  102. #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
  103. #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
  104. #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
  105. /* TXCSR in Peripheral and Host mode */
  106. #define MUSB_TXCSR_AUTOSET 0x8000
  107. #define MUSB_TXCSR_DMAENAB 0x1000
  108. #define MUSB_TXCSR_FRCDATATOG 0x0800
  109. #define MUSB_TXCSR_DMAMODE 0x0400
  110. #define MUSB_TXCSR_CLRDATATOG 0x0040
  111. #define MUSB_TXCSR_FLUSHFIFO 0x0008
  112. #define MUSB_TXCSR_FIFONOTEMPTY 0x0002
  113. #define MUSB_TXCSR_TXPKTRDY 0x0001
  114. /* TXCSR in Peripheral mode */
  115. #define MUSB_TXCSR_P_ISO 0x4000
  116. #define MUSB_TXCSR_P_INCOMPTX 0x0080
  117. #define MUSB_TXCSR_P_SENTSTALL 0x0020
  118. #define MUSB_TXCSR_P_SENDSTALL 0x0010
  119. #define MUSB_TXCSR_P_UNDERRUN 0x0004
  120. /* TXCSR in Host mode */
  121. #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
  122. #define MUSB_TXCSR_H_DATATOGGLE 0x0100
  123. #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
  124. #define MUSB_TXCSR_H_RXSTALL 0x0020
  125. #define MUSB_TXCSR_H_ERROR 0x0004
  126. /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
  127. #define MUSB_TXCSR_P_WZC_BITS \
  128. (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
  129. | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
  130. #define MUSB_TXCSR_H_WZC_BITS \
  131. (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
  132. | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
  133. /* RXCSR in Peripheral and Host mode */
  134. #define MUSB_RXCSR_AUTOCLEAR 0x8000
  135. #define MUSB_RXCSR_DMAENAB 0x2000
  136. #define MUSB_RXCSR_DISNYET 0x1000
  137. #define MUSB_RXCSR_PID_ERR 0x1000
  138. #define MUSB_RXCSR_DMAMODE 0x0800
  139. #define MUSB_RXCSR_INCOMPRX 0x0100
  140. #define MUSB_RXCSR_CLRDATATOG 0x0080
  141. #define MUSB_RXCSR_FLUSHFIFO 0x0010
  142. #define MUSB_RXCSR_DATAERROR 0x0008
  143. #define MUSB_RXCSR_FIFOFULL 0x0002
  144. #define MUSB_RXCSR_RXPKTRDY 0x0001
  145. /* RXCSR in Peripheral mode */
  146. #define MUSB_RXCSR_P_ISO 0x4000
  147. #define MUSB_RXCSR_P_SENTSTALL 0x0040
  148. #define MUSB_RXCSR_P_SENDSTALL 0x0020
  149. #define MUSB_RXCSR_P_OVERRUN 0x0004
  150. /* RXCSR in Host mode */
  151. #define MUSB_RXCSR_H_AUTOREQ 0x4000
  152. #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
  153. #define MUSB_RXCSR_H_DATATOGGLE 0x0200
  154. #define MUSB_RXCSR_H_RXSTALL 0x0040
  155. #define MUSB_RXCSR_H_REQPKT 0x0020
  156. #define MUSB_RXCSR_H_ERROR 0x0004
  157. /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
  158. #define MUSB_RXCSR_P_WZC_BITS \
  159. (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
  160. | MUSB_RXCSR_RXPKTRDY)
  161. #define MUSB_RXCSR_H_WZC_BITS \
  162. (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
  163. | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
  164. /* HUBADDR */
  165. #define MUSB_HUBADDR_MULTI_TT 0x80
  166. /* SUNXI has different reg addresses, but identical r/w functions */
  167. #ifndef CONFIG_ARCH_SUNXI
  168. /*
  169. * Common USB registers
  170. */
  171. #define MUSB_FADDR 0x00 /* 8-bit */
  172. #define MUSB_POWER 0x01 /* 8-bit */
  173. #define MUSB_INTRTX 0x02 /* 16-bit */
  174. #define MUSB_INTRRX 0x04
  175. #define MUSB_INTRTXE 0x06
  176. #define MUSB_INTRRXE 0x08
  177. #define MUSB_INTRUSB 0x0A /* 8 bit */
  178. #define MUSB_INTRUSBE 0x0B /* 8 bit */
  179. #define MUSB_FRAME 0x0C
  180. #define MUSB_INDEX 0x0E /* 8 bit */
  181. #define MUSB_TESTMODE 0x0F /* 8 bit */
  182. /* Get offset for a given FIFO from musb->mregs */
  183. #if defined(CONFIG_USB_MUSB_TUSB6010) || \
  184. defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
  185. #define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
  186. #else
  187. #define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
  188. #endif
  189. /*
  190. * Additional Control Registers
  191. */
  192. #define MUSB_DEVCTL 0x60 /* 8 bit */
  193. /* These are always controlled through the INDEX register */
  194. #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
  195. #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
  196. #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
  197. #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
  198. /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
  199. #define MUSB_HWVERS 0x6C /* 8 bit */
  200. #define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
  201. #define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
  202. #define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
  203. #define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
  204. #define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
  205. #define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
  206. #define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
  207. #define MUSB_EPINFO 0x78 /* 8 bit */
  208. #define MUSB_RAMINFO 0x79 /* 8 bit */
  209. #define MUSB_LINKINFO 0x7a /* 8 bit */
  210. #define MUSB_VPLEN 0x7b /* 8 bit */
  211. #define MUSB_HS_EOF1 0x7c /* 8 bit */
  212. #define MUSB_FS_EOF1 0x7d /* 8 bit */
  213. #define MUSB_LS_EOF1 0x7e /* 8 bit */
  214. /* Offsets to endpoint registers */
  215. #define MUSB_TXMAXP 0x00
  216. #define MUSB_TXCSR 0x02
  217. #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
  218. #define MUSB_RXMAXP 0x04
  219. #define MUSB_RXCSR 0x06
  220. #define MUSB_RXCOUNT 0x08
  221. #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
  222. #define MUSB_TXTYPE 0x0A
  223. #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
  224. #define MUSB_TXINTERVAL 0x0B
  225. #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
  226. #define MUSB_RXTYPE 0x0C
  227. #define MUSB_RXINTERVAL 0x0D
  228. #define MUSB_FIFOSIZE 0x0F
  229. #define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
  230. /* Offsets to endpoint registers in indexed model (using INDEX register) */
  231. #define MUSB_INDEXED_OFFSET(_epnum, _offset) \
  232. (0x10 + (_offset))
  233. /* Offsets to endpoint registers in flat models */
  234. #define MUSB_FLAT_OFFSET(_epnum, _offset) \
  235. (0x100 + (0x10*(_epnum)) + (_offset))
  236. #if defined(CONFIG_USB_MUSB_TUSB6010) || \
  237. defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
  238. /* TUSB6010 EP0 configuration register is special */
  239. #define MUSB_TUSB_OFFSET(_epnum, _offset) \
  240. (0x10 + _offset)
  241. #include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
  242. #endif
  243. #define MUSB_TXCSR_MODE 0x2000
  244. /* "bus control"/target registers, for host side multipoint (external hubs) */
  245. #define MUSB_TXFUNCADDR 0x00
  246. #define MUSB_TXHUBADDR 0x02
  247. #define MUSB_TXHUBPORT 0x03
  248. #define MUSB_RXFUNCADDR 0x04
  249. #define MUSB_RXHUBADDR 0x06
  250. #define MUSB_RXHUBPORT 0x07
  251. #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
  252. (0x80 + (8*(_epnum)) + (_offset))
  253. #else /* CONFIG_ARCH_SUNXI */
  254. /*
  255. * Common USB registers
  256. */
  257. #define MUSB_FADDR 0x0098
  258. #define MUSB_POWER 0x0040
  259. #define MUSB_INTRTX 0x0044
  260. #define MUSB_INTRRX 0x0046
  261. #define MUSB_INTRTXE 0x0048
  262. #define MUSB_INTRRXE 0x004A
  263. #define MUSB_INTRUSB 0x004C
  264. #define MUSB_INTRUSBE 0x0050
  265. #define MUSB_FRAME 0x0054
  266. #define MUSB_INDEX 0x0042
  267. #define MUSB_TESTMODE 0x007C
  268. /* Get offset for a given FIFO from musb->mregs */
  269. #define MUSB_FIFO_OFFSET(epnum) (0x00 + ((epnum) * 4))
  270. /*
  271. * Additional Control Registers
  272. */
  273. #define MUSB_DEVCTL 0x0041
  274. /* These are always controlled through the INDEX register */
  275. #define MUSB_TXFIFOSZ 0x0090
  276. #define MUSB_RXFIFOSZ 0x0094
  277. #define MUSB_TXFIFOADD 0x0092
  278. #define MUSB_RXFIFOADD 0x0096
  279. #define MUSB_EPINFO 0x0078
  280. #define MUSB_RAMINFO 0x0079
  281. #define MUSB_LINKINFO 0x007A
  282. #define MUSB_VPLEN 0x007B
  283. #define MUSB_HS_EOF1 0x007C
  284. #define MUSB_FS_EOF1 0x007D
  285. #define MUSB_LS_EOF1 0x007E
  286. /* Offsets to endpoint registers */
  287. #define MUSB_TXMAXP 0x0080
  288. #define MUSB_TXCSR 0x0082
  289. #define MUSB_CSR0 0x0082
  290. #define MUSB_RXMAXP 0x0084
  291. #define MUSB_RXCSR 0x0086
  292. #define MUSB_RXCOUNT 0x0088
  293. #define MUSB_COUNT0 0x0088
  294. #define MUSB_TXTYPE 0x008C
  295. #define MUSB_TYPE0 0x008C
  296. #define MUSB_TXINTERVAL 0x008D
  297. #define MUSB_NAKLIMIT0 0x008D
  298. #define MUSB_RXTYPE 0x008E
  299. #define MUSB_RXINTERVAL 0x008F
  300. #define MUSB_CONFIGDATA 0x00b0 /* musb_read_configdata adds 0x10 ! */
  301. #define MUSB_FIFOSIZE 0x0090
  302. /* Offsets to endpoint registers in indexed model (using INDEX register) */
  303. #define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset)
  304. #define MUSB_TXCSR_MODE 0x2000
  305. /* "bus control"/target registers, for host side multipoint (external hubs) */
  306. #define MUSB_TXFUNCADDR 0x0098
  307. #define MUSB_TXHUBADDR 0x009A
  308. #define MUSB_TXHUBPORT 0x009B
  309. #define MUSB_RXFUNCADDR 0x009C
  310. #define MUSB_RXHUBADDR 0x009E
  311. #define MUSB_RXHUBPORT 0x009F
  312. /* Endpoint is selected with MUSB_INDEX. */
  313. #define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset)
  314. #endif /* CONFIG_ARCH_SUNXI */
  315. static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
  316. {
  317. musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
  318. }
  319. static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
  320. {
  321. musb_writew(mbase, MUSB_TXFIFOADD, c_off);
  322. }
  323. static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
  324. {
  325. musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
  326. }
  327. static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
  328. {
  329. musb_writew(mbase, MUSB_RXFIFOADD, c_off);
  330. }
  331. static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
  332. {
  333. #ifndef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
  334. musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
  335. #endif
  336. }
  337. static inline u8 musb_read_txfifosz(void __iomem *mbase)
  338. {
  339. return musb_readb(mbase, MUSB_TXFIFOSZ);
  340. }
  341. static inline u16 musb_read_txfifoadd(void __iomem *mbase)
  342. {
  343. return musb_readw(mbase, MUSB_TXFIFOADD);
  344. }
  345. static inline u8 musb_read_rxfifosz(void __iomem *mbase)
  346. {
  347. return musb_readb(mbase, MUSB_RXFIFOSZ);
  348. }
  349. static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
  350. {
  351. return musb_readw(mbase, MUSB_RXFIFOADD);
  352. }
  353. static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
  354. {
  355. #ifdef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
  356. return 0;
  357. #else
  358. return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
  359. #endif
  360. }
  361. static inline u8 musb_read_configdata(void __iomem *mbase)
  362. {
  363. #ifdef CONFIG_USB_MUSB_FIXED_CONFIGDATA
  364. /* <Sigh> allwinner saves a reg, and we need to hardcode this */
  365. return 0xde;
  366. #else
  367. musb_writeb(mbase, MUSB_INDEX, 0);
  368. return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
  369. #endif
  370. }
  371. static inline u16 musb_read_hwvers(void __iomem *mbase)
  372. {
  373. #ifdef CONFIG_ARCH_SUNXI
  374. return 0; /* Unknown version */
  375. #else
  376. return musb_readw(mbase, MUSB_HWVERS);
  377. #endif
  378. }
  379. static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
  380. {
  381. return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
  382. }
  383. static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
  384. u8 qh_addr_reg)
  385. {
  386. musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
  387. }
  388. static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
  389. u8 qh_h_addr_reg)
  390. {
  391. musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
  392. }
  393. static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
  394. u8 qh_h_port_reg)
  395. {
  396. musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
  397. }
  398. static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
  399. u8 qh_addr_reg)
  400. {
  401. musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
  402. qh_addr_reg);
  403. }
  404. static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
  405. u8 qh_addr_reg)
  406. {
  407. musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
  408. qh_addr_reg);
  409. }
  410. static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
  411. u8 qh_h_port_reg)
  412. {
  413. musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
  414. qh_h_port_reg);
  415. }
  416. static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
  417. {
  418. return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
  419. }
  420. static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
  421. {
  422. return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
  423. }
  424. static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
  425. {
  426. return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
  427. }
  428. static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
  429. {
  430. return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
  431. }
  432. static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
  433. {
  434. return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
  435. }
  436. static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
  437. {
  438. return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
  439. }
  440. #endif /* __MUSB_REGS_H__ */