meson-gxl.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson GXL Internal PHY Driver
  4. *
  5. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  6. * Copyright (C) 2016 BayLibre, SAS. All rights reserved.
  7. * Author: Neil Armstrong <narmstrong@baylibre.com>
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <linux/bitops.h>
  12. #include <dm.h>
  13. #include <phy.h>
  14. /* This function is provided to cope with the possible failures of this phy
  15. * during aneg process. When aneg fails, the PHY reports that aneg is done
  16. * but the value found in MII_LPA is wrong:
  17. * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
  18. * the link partner (LP) supports aneg but the LP never acked our base
  19. * code word, it is likely that we never sent it to begin with.
  20. * - Late failures: MII_LPA is filled with a value which seems to make sense
  21. * but it actually is not what the LP is advertising. It seems that we
  22. * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
  23. * If this particular bit is not set when aneg is reported being done,
  24. * it means MII_LPA is likely to be wrong.
  25. *
  26. * In both case, forcing a restart of the aneg process solve the problem.
  27. * When this failure happens, the first retry is usually successful but,
  28. * in some cases, it may take up to 6 retries to get a decent result
  29. */
  30. int meson_gxl_startup(struct phy_device *phydev)
  31. {
  32. unsigned int retries = 10;
  33. int ret, wol, lpa, exp;
  34. restart_aneg:
  35. ret = genphy_update_link(phydev);
  36. if (ret)
  37. return ret;
  38. if (phydev->autoneg == AUTONEG_ENABLE) {
  39. /* Need to access WOL bank, make sure the access is open */
  40. ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
  41. if (ret)
  42. return ret;
  43. ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
  44. if (ret)
  45. return ret;
  46. ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
  47. if (ret)
  48. return ret;
  49. ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
  50. if (ret)
  51. return ret;
  52. /* Request LPI_STATUS WOL register */
  53. ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80);
  54. if (ret)
  55. return ret;
  56. /* Read LPI_STATUS value */
  57. wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
  58. if (wol < 0)
  59. return wol;
  60. lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
  61. if (lpa < 0)
  62. return lpa;
  63. exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION);
  64. if (exp < 0)
  65. return exp;
  66. if (!(wol & BIT(12)) ||
  67. ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
  68. /* Looks like aneg failed after all */
  69. if (!retries) {
  70. printf("%s LPA corruption max attempts\n",
  71. phydev->dev->name);
  72. return -ETIMEDOUT;
  73. }
  74. printf("%s LPA corruption - aneg restart\n",
  75. phydev->dev->name);
  76. ret = genphy_restart_aneg(phydev);
  77. if (ret)
  78. return ret;
  79. --retries;
  80. goto restart_aneg;
  81. }
  82. }
  83. return genphy_parse_link(phydev);
  84. }
  85. static int meson_gxl_phy_config(struct phy_device *phydev)
  86. {
  87. /* Enable Analog and DSP register Bank access by */
  88. phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
  89. phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
  90. phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
  91. phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
  92. /* Write Analog register 23 */
  93. phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
  94. phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
  95. /* Enable fractional PLL */
  96. phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
  97. phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
  98. /* Program fraction FR_PLL_DIV1 */
  99. phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
  100. phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
  101. /* Program fraction FR_PLL_DIV1 */
  102. phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
  103. phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
  104. return genphy_config(phydev);
  105. }
  106. static struct phy_driver meson_gxl_phy_driver = {
  107. .name = "Meson GXL Internal PHY",
  108. .uid = 0x01814400,
  109. .mask = 0xfffffff0,
  110. .features = PHY_BASIC_FEATURES,
  111. .config = &meson_gxl_phy_config,
  112. .startup = &meson_gxl_startup,
  113. .shutdown = &genphy_shutdown,
  114. };
  115. int phy_meson_gxl_init(void)
  116. {
  117. phy_register(&meson_gxl_phy_driver);
  118. return 0;
  119. }