nand_base.c 135 KB

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  1. /*
  2. * Overview:
  3. * This is the generic MTD driver for NAND flash devices. It should be
  4. * capable of working with almost all NAND chips currently available.
  5. *
  6. * Additional technical information is available on
  7. * http://www.linux-mtd.infradead.org/doc/nand.html
  8. *
  9. * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  10. * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
  11. *
  12. * Credits:
  13. * David Woodhouse for adding multichip support
  14. *
  15. * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  16. * rework for 2K page size chips
  17. *
  18. * TODO:
  19. * Enable cached programming for 2k page size chips
  20. * Check, if mtd->ecctype should be set to MTD_ECC_HW
  21. * if we have HW ECC support.
  22. * BBT table is not serialized, has to be fixed
  23. *
  24. * This program is free software; you can redistribute it and/or modify
  25. * it under the terms of the GNU General Public License version 2 as
  26. * published by the Free Software Foundation.
  27. *
  28. */
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <common.h>
  31. #include <log.h>
  32. #include <malloc.h>
  33. #include <watchdog.h>
  34. #include <dm/devres.h>
  35. #include <linux/bitops.h>
  36. #include <linux/bug.h>
  37. #include <linux/delay.h>
  38. #include <linux/err.h>
  39. #include <linux/compat.h>
  40. #include <linux/mtd/mtd.h>
  41. #include <linux/mtd/rawnand.h>
  42. #include <linux/mtd/nand_ecc.h>
  43. #include <linux/mtd/nand_bch.h>
  44. #ifdef CONFIG_MTD_PARTITIONS
  45. #include <linux/mtd/partitions.h>
  46. #endif
  47. #include <asm/io.h>
  48. #include <linux/errno.h>
  49. /* Define default oob placement schemes for large and small page devices */
  50. #ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
  51. static struct nand_ecclayout nand_oob_8 = {
  52. .eccbytes = 3,
  53. .eccpos = {0, 1, 2},
  54. .oobfree = {
  55. {.offset = 3,
  56. .length = 2},
  57. {.offset = 6,
  58. .length = 2} }
  59. };
  60. static struct nand_ecclayout nand_oob_16 = {
  61. .eccbytes = 6,
  62. .eccpos = {0, 1, 2, 3, 6, 7},
  63. .oobfree = {
  64. {.offset = 8,
  65. . length = 8} }
  66. };
  67. static struct nand_ecclayout nand_oob_64 = {
  68. .eccbytes = 24,
  69. .eccpos = {
  70. 40, 41, 42, 43, 44, 45, 46, 47,
  71. 48, 49, 50, 51, 52, 53, 54, 55,
  72. 56, 57, 58, 59, 60, 61, 62, 63},
  73. .oobfree = {
  74. {.offset = 2,
  75. .length = 38} }
  76. };
  77. static struct nand_ecclayout nand_oob_128 = {
  78. .eccbytes = 48,
  79. .eccpos = {
  80. 80, 81, 82, 83, 84, 85, 86, 87,
  81. 88, 89, 90, 91, 92, 93, 94, 95,
  82. 96, 97, 98, 99, 100, 101, 102, 103,
  83. 104, 105, 106, 107, 108, 109, 110, 111,
  84. 112, 113, 114, 115, 116, 117, 118, 119,
  85. 120, 121, 122, 123, 124, 125, 126, 127},
  86. .oobfree = {
  87. {.offset = 2,
  88. .length = 78} }
  89. };
  90. #endif
  91. static int nand_get_device(struct mtd_info *mtd, int new_state);
  92. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  93. struct mtd_oob_ops *ops);
  94. /*
  95. * For devices which display every fart in the system on a separate LED. Is
  96. * compiled away when LED support is disabled.
  97. */
  98. DEFINE_LED_TRIGGER(nand_led_trigger);
  99. static int check_offs_len(struct mtd_info *mtd,
  100. loff_t ofs, uint64_t len)
  101. {
  102. struct nand_chip *chip = mtd_to_nand(mtd);
  103. int ret = 0;
  104. /* Start address must align on block boundary */
  105. if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
  106. pr_debug("%s: unaligned address\n", __func__);
  107. ret = -EINVAL;
  108. }
  109. /* Length must align on block boundary */
  110. if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
  111. pr_debug("%s: length not block aligned\n", __func__);
  112. ret = -EINVAL;
  113. }
  114. return ret;
  115. }
  116. /**
  117. * nand_release_device - [GENERIC] release chip
  118. * @mtd: MTD device structure
  119. *
  120. * Release chip lock and wake up anyone waiting on the device.
  121. */
  122. static void nand_release_device(struct mtd_info *mtd)
  123. {
  124. struct nand_chip *chip = mtd_to_nand(mtd);
  125. /* De-select the NAND device */
  126. chip->select_chip(mtd, -1);
  127. }
  128. /**
  129. * nand_read_byte - [DEFAULT] read one byte from the chip
  130. * @mtd: MTD device structure
  131. *
  132. * Default read function for 8bit buswidth
  133. */
  134. uint8_t nand_read_byte(struct mtd_info *mtd)
  135. {
  136. struct nand_chip *chip = mtd_to_nand(mtd);
  137. return readb(chip->IO_ADDR_R);
  138. }
  139. /**
  140. * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
  141. * @mtd: MTD device structure
  142. *
  143. * Default read function for 16bit buswidth with endianness conversion.
  144. *
  145. */
  146. static uint8_t nand_read_byte16(struct mtd_info *mtd)
  147. {
  148. struct nand_chip *chip = mtd_to_nand(mtd);
  149. return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
  150. }
  151. /**
  152. * nand_read_word - [DEFAULT] read one word from the chip
  153. * @mtd: MTD device structure
  154. *
  155. * Default read function for 16bit buswidth without endianness conversion.
  156. */
  157. static u16 nand_read_word(struct mtd_info *mtd)
  158. {
  159. struct nand_chip *chip = mtd_to_nand(mtd);
  160. return readw(chip->IO_ADDR_R);
  161. }
  162. /**
  163. * nand_select_chip - [DEFAULT] control CE line
  164. * @mtd: MTD device structure
  165. * @chipnr: chipnumber to select, -1 for deselect
  166. *
  167. * Default select function for 1 chip devices.
  168. */
  169. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  170. {
  171. struct nand_chip *chip = mtd_to_nand(mtd);
  172. switch (chipnr) {
  173. case -1:
  174. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  175. break;
  176. case 0:
  177. break;
  178. default:
  179. BUG();
  180. }
  181. }
  182. /**
  183. * nand_write_byte - [DEFAULT] write single byte to chip
  184. * @mtd: MTD device structure
  185. * @byte: value to write
  186. *
  187. * Default function to write a byte to I/O[7:0]
  188. */
  189. static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
  190. {
  191. struct nand_chip *chip = mtd_to_nand(mtd);
  192. chip->write_buf(mtd, &byte, 1);
  193. }
  194. /**
  195. * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
  196. * @mtd: MTD device structure
  197. * @byte: value to write
  198. *
  199. * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
  200. */
  201. static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
  202. {
  203. struct nand_chip *chip = mtd_to_nand(mtd);
  204. uint16_t word = byte;
  205. /*
  206. * It's not entirely clear what should happen to I/O[15:8] when writing
  207. * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
  208. *
  209. * When the host supports a 16-bit bus width, only data is
  210. * transferred at the 16-bit width. All address and command line
  211. * transfers shall use only the lower 8-bits of the data bus. During
  212. * command transfers, the host may place any value on the upper
  213. * 8-bits of the data bus. During address transfers, the host shall
  214. * set the upper 8-bits of the data bus to 00h.
  215. *
  216. * One user of the write_byte callback is nand_onfi_set_features. The
  217. * four parameters are specified to be written to I/O[7:0], but this is
  218. * neither an address nor a command transfer. Let's assume a 0 on the
  219. * upper I/O lines is OK.
  220. */
  221. chip->write_buf(mtd, (uint8_t *)&word, 2);
  222. }
  223. static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
  224. {
  225. int i;
  226. for (i = 0; i < len; i++)
  227. writeb(buf[i], addr);
  228. }
  229. static void ioread8_rep(void *addr, uint8_t *buf, int len)
  230. {
  231. int i;
  232. for (i = 0; i < len; i++)
  233. buf[i] = readb(addr);
  234. }
  235. static void ioread16_rep(void *addr, void *buf, int len)
  236. {
  237. int i;
  238. u16 *p = (u16 *) buf;
  239. for (i = 0; i < len; i++)
  240. p[i] = readw(addr);
  241. }
  242. static void iowrite16_rep(void *addr, void *buf, int len)
  243. {
  244. int i;
  245. u16 *p = (u16 *) buf;
  246. for (i = 0; i < len; i++)
  247. writew(p[i], addr);
  248. }
  249. /**
  250. * nand_write_buf - [DEFAULT] write buffer to chip
  251. * @mtd: MTD device structure
  252. * @buf: data buffer
  253. * @len: number of bytes to write
  254. *
  255. * Default write function for 8bit buswidth.
  256. */
  257. void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  258. {
  259. struct nand_chip *chip = mtd_to_nand(mtd);
  260. iowrite8_rep(chip->IO_ADDR_W, buf, len);
  261. }
  262. /**
  263. * nand_read_buf - [DEFAULT] read chip data into buffer
  264. * @mtd: MTD device structure
  265. * @buf: buffer to store date
  266. * @len: number of bytes to read
  267. *
  268. * Default read function for 8bit buswidth.
  269. */
  270. void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  271. {
  272. struct nand_chip *chip = mtd_to_nand(mtd);
  273. ioread8_rep(chip->IO_ADDR_R, buf, len);
  274. }
  275. /**
  276. * nand_write_buf16 - [DEFAULT] write buffer to chip
  277. * @mtd: MTD device structure
  278. * @buf: data buffer
  279. * @len: number of bytes to write
  280. *
  281. * Default write function for 16bit buswidth.
  282. */
  283. void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  284. {
  285. struct nand_chip *chip = mtd_to_nand(mtd);
  286. u16 *p = (u16 *) buf;
  287. iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
  288. }
  289. /**
  290. * nand_read_buf16 - [DEFAULT] read chip data into buffer
  291. * @mtd: MTD device structure
  292. * @buf: buffer to store date
  293. * @len: number of bytes to read
  294. *
  295. * Default read function for 16bit buswidth.
  296. */
  297. void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  298. {
  299. struct nand_chip *chip = mtd_to_nand(mtd);
  300. u16 *p = (u16 *) buf;
  301. ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
  302. }
  303. /**
  304. * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  305. * @mtd: MTD device structure
  306. * @ofs: offset from device start
  307. *
  308. * Check, if the block is bad.
  309. */
  310. static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
  311. {
  312. int page, res = 0, i = 0;
  313. struct nand_chip *chip = mtd_to_nand(mtd);
  314. u16 bad;
  315. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  316. ofs += mtd->erasesize - mtd->writesize;
  317. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  318. do {
  319. if (chip->options & NAND_BUSWIDTH_16) {
  320. chip->cmdfunc(mtd, NAND_CMD_READOOB,
  321. chip->badblockpos & 0xFE, page);
  322. bad = cpu_to_le16(chip->read_word(mtd));
  323. if (chip->badblockpos & 0x1)
  324. bad >>= 8;
  325. else
  326. bad &= 0xFF;
  327. } else {
  328. chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
  329. page);
  330. bad = chip->read_byte(mtd);
  331. }
  332. if (likely(chip->badblockbits == 8))
  333. res = bad != 0xFF;
  334. else
  335. res = hweight8(bad) < chip->badblockbits;
  336. ofs += mtd->writesize;
  337. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  338. i++;
  339. } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
  340. return res;
  341. }
  342. /**
  343. * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
  344. * @mtd: MTD device structure
  345. * @ofs: offset from device start
  346. *
  347. * This is the default implementation, which can be overridden by a hardware
  348. * specific driver. It provides the details for writing a bad block marker to a
  349. * block.
  350. */
  351. static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
  352. {
  353. struct nand_chip *chip = mtd_to_nand(mtd);
  354. struct mtd_oob_ops ops;
  355. uint8_t buf[2] = { 0, 0 };
  356. int ret = 0, res, i = 0;
  357. memset(&ops, 0, sizeof(ops));
  358. ops.oobbuf = buf;
  359. ops.ooboffs = chip->badblockpos;
  360. if (chip->options & NAND_BUSWIDTH_16) {
  361. ops.ooboffs &= ~0x01;
  362. ops.len = ops.ooblen = 2;
  363. } else {
  364. ops.len = ops.ooblen = 1;
  365. }
  366. ops.mode = MTD_OPS_PLACE_OOB;
  367. /* Write to first/last page(s) if necessary */
  368. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  369. ofs += mtd->erasesize - mtd->writesize;
  370. do {
  371. res = nand_do_write_oob(mtd, ofs, &ops);
  372. if (!ret)
  373. ret = res;
  374. i++;
  375. ofs += mtd->writesize;
  376. } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
  377. return ret;
  378. }
  379. /**
  380. * nand_block_markbad_lowlevel - mark a block bad
  381. * @mtd: MTD device structure
  382. * @ofs: offset from device start
  383. *
  384. * This function performs the generic NAND bad block marking steps (i.e., bad
  385. * block table(s) and/or marker(s)). We only allow the hardware driver to
  386. * specify how to write bad block markers to OOB (chip->block_markbad).
  387. *
  388. * We try operations in the following order:
  389. * (1) erase the affected block, to allow OOB marker to be written cleanly
  390. * (2) write bad block marker to OOB area of affected block (unless flag
  391. * NAND_BBT_NO_OOB_BBM is present)
  392. * (3) update the BBT
  393. * Note that we retain the first error encountered in (2) or (3), finish the
  394. * procedures, and dump the error in the end.
  395. */
  396. static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
  397. {
  398. struct nand_chip *chip = mtd_to_nand(mtd);
  399. int res, ret = 0;
  400. if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
  401. struct erase_info einfo;
  402. /* Attempt erase before marking OOB */
  403. memset(&einfo, 0, sizeof(einfo));
  404. einfo.mtd = mtd;
  405. einfo.addr = ofs;
  406. einfo.len = 1ULL << chip->phys_erase_shift;
  407. nand_erase_nand(mtd, &einfo, 0);
  408. /* Write bad block marker to OOB */
  409. nand_get_device(mtd, FL_WRITING);
  410. ret = chip->block_markbad(mtd, ofs);
  411. nand_release_device(mtd);
  412. }
  413. /* Mark block bad in BBT */
  414. if (chip->bbt) {
  415. res = nand_markbad_bbt(mtd, ofs);
  416. if (!ret)
  417. ret = res;
  418. }
  419. if (!ret)
  420. mtd->ecc_stats.badblocks++;
  421. return ret;
  422. }
  423. /**
  424. * nand_check_wp - [GENERIC] check if the chip is write protected
  425. * @mtd: MTD device structure
  426. *
  427. * Check, if the device is write protected. The function expects, that the
  428. * device is already selected.
  429. */
  430. static int nand_check_wp(struct mtd_info *mtd)
  431. {
  432. struct nand_chip *chip = mtd_to_nand(mtd);
  433. u8 status;
  434. int ret;
  435. /* Broken xD cards report WP despite being writable */
  436. if (chip->options & NAND_BROKEN_XD)
  437. return 0;
  438. /* Check the WP bit */
  439. ret = nand_status_op(chip, &status);
  440. if (ret)
  441. return ret;
  442. return status & NAND_STATUS_WP ? 0 : 1;
  443. }
  444. /**
  445. * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
  446. * @mtd: MTD device structure
  447. * @ofs: offset from device start
  448. *
  449. * Check if the block is marked as reserved.
  450. */
  451. static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
  452. {
  453. struct nand_chip *chip = mtd_to_nand(mtd);
  454. if (!chip->bbt)
  455. return 0;
  456. /* Return info from the table */
  457. return nand_isreserved_bbt(mtd, ofs);
  458. }
  459. /**
  460. * nand_block_checkbad - [GENERIC] Check if a block is marked bad
  461. * @mtd: MTD device structure
  462. * @ofs: offset from device start
  463. * @allowbbt: 1, if its allowed to access the bbt area
  464. *
  465. * Check, if the block is bad. Either by reading the bad block table or
  466. * calling of the scan function.
  467. */
  468. static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
  469. {
  470. struct nand_chip *chip = mtd_to_nand(mtd);
  471. if (!(chip->options & NAND_SKIP_BBTSCAN) &&
  472. !(chip->options & NAND_BBT_SCANNED)) {
  473. chip->options |= NAND_BBT_SCANNED;
  474. chip->scan_bbt(mtd);
  475. }
  476. if (!chip->bbt)
  477. return chip->block_bad(mtd, ofs);
  478. /* Return info from the table */
  479. return nand_isbad_bbt(mtd, ofs, allowbbt);
  480. }
  481. /**
  482. * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
  483. * @mtd: MTD device structure
  484. *
  485. * Wait for the ready pin after a command, and warn if a timeout occurs.
  486. */
  487. void nand_wait_ready(struct mtd_info *mtd)
  488. {
  489. struct nand_chip *chip = mtd_to_nand(mtd);
  490. u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
  491. u32 time_start;
  492. time_start = get_timer(0);
  493. /* Wait until command is processed or timeout occurs */
  494. while (get_timer(time_start) < timeo) {
  495. if (chip->dev_ready)
  496. if (chip->dev_ready(mtd))
  497. break;
  498. }
  499. if (!chip->dev_ready(mtd))
  500. pr_warn("timeout while waiting for chip to become ready\n");
  501. }
  502. EXPORT_SYMBOL_GPL(nand_wait_ready);
  503. /**
  504. * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
  505. * @mtd: MTD device structure
  506. * @timeo: Timeout in ms
  507. *
  508. * Wait for status ready (i.e. command done) or timeout.
  509. */
  510. static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
  511. {
  512. register struct nand_chip *chip = mtd_to_nand(mtd);
  513. u32 time_start;
  514. int ret;
  515. timeo = (CONFIG_SYS_HZ * timeo) / 1000;
  516. time_start = get_timer(0);
  517. while (get_timer(time_start) < timeo) {
  518. u8 status;
  519. ret = nand_read_data_op(chip, &status, sizeof(status), true);
  520. if (ret)
  521. return;
  522. if (status & NAND_STATUS_READY)
  523. break;
  524. WATCHDOG_RESET();
  525. }
  526. };
  527. /**
  528. * nand_command - [DEFAULT] Send command to NAND device
  529. * @mtd: MTD device structure
  530. * @command: the command to be sent
  531. * @column: the column address for this command, -1 if none
  532. * @page_addr: the page address for this command, -1 if none
  533. *
  534. * Send command to NAND device. This function is used for small page devices
  535. * (512 Bytes per page).
  536. */
  537. static void nand_command(struct mtd_info *mtd, unsigned int command,
  538. int column, int page_addr)
  539. {
  540. register struct nand_chip *chip = mtd_to_nand(mtd);
  541. int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
  542. /* Write out the command to the device */
  543. if (command == NAND_CMD_SEQIN) {
  544. int readcmd;
  545. if (column >= mtd->writesize) {
  546. /* OOB area */
  547. column -= mtd->writesize;
  548. readcmd = NAND_CMD_READOOB;
  549. } else if (column < 256) {
  550. /* First 256 bytes --> READ0 */
  551. readcmd = NAND_CMD_READ0;
  552. } else {
  553. column -= 256;
  554. readcmd = NAND_CMD_READ1;
  555. }
  556. chip->cmd_ctrl(mtd, readcmd, ctrl);
  557. ctrl &= ~NAND_CTRL_CHANGE;
  558. }
  559. chip->cmd_ctrl(mtd, command, ctrl);
  560. /* Address cycle, when necessary */
  561. ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
  562. /* Serially input address */
  563. if (column != -1) {
  564. /* Adjust columns for 16 bit buswidth */
  565. if (chip->options & NAND_BUSWIDTH_16 &&
  566. !nand_opcode_8bits(command))
  567. column >>= 1;
  568. chip->cmd_ctrl(mtd, column, ctrl);
  569. ctrl &= ~NAND_CTRL_CHANGE;
  570. }
  571. if (page_addr != -1) {
  572. chip->cmd_ctrl(mtd, page_addr, ctrl);
  573. ctrl &= ~NAND_CTRL_CHANGE;
  574. chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
  575. if (chip->options & NAND_ROW_ADDR_3)
  576. chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
  577. }
  578. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  579. /*
  580. * Program and erase have their own busy handlers status and sequential
  581. * in needs no delay
  582. */
  583. switch (command) {
  584. case NAND_CMD_PAGEPROG:
  585. case NAND_CMD_ERASE1:
  586. case NAND_CMD_ERASE2:
  587. case NAND_CMD_SEQIN:
  588. case NAND_CMD_STATUS:
  589. case NAND_CMD_READID:
  590. case NAND_CMD_SET_FEATURES:
  591. return;
  592. case NAND_CMD_RESET:
  593. if (chip->dev_ready)
  594. break;
  595. udelay(chip->chip_delay);
  596. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  597. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  598. chip->cmd_ctrl(mtd,
  599. NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  600. /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
  601. nand_wait_status_ready(mtd, 250);
  602. return;
  603. /* This applies to read commands */
  604. default:
  605. /*
  606. * If we don't have access to the busy pin, we apply the given
  607. * command delay
  608. */
  609. if (!chip->dev_ready) {
  610. udelay(chip->chip_delay);
  611. return;
  612. }
  613. }
  614. /*
  615. * Apply this short delay always to ensure that we do wait tWB in
  616. * any case on any machine.
  617. */
  618. ndelay(100);
  619. nand_wait_ready(mtd);
  620. }
  621. /**
  622. * nand_command_lp - [DEFAULT] Send command to NAND large page device
  623. * @mtd: MTD device structure
  624. * @command: the command to be sent
  625. * @column: the column address for this command, -1 if none
  626. * @page_addr: the page address for this command, -1 if none
  627. *
  628. * Send command to NAND device. This is the version for the new large page
  629. * devices. We don't have the separate regions as we have in the small page
  630. * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
  631. */
  632. static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
  633. int column, int page_addr)
  634. {
  635. register struct nand_chip *chip = mtd_to_nand(mtd);
  636. /* Emulate NAND_CMD_READOOB */
  637. if (command == NAND_CMD_READOOB) {
  638. column += mtd->writesize;
  639. command = NAND_CMD_READ0;
  640. }
  641. /* Command latch cycle */
  642. chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  643. if (column != -1 || page_addr != -1) {
  644. int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
  645. /* Serially input address */
  646. if (column != -1) {
  647. /* Adjust columns for 16 bit buswidth */
  648. if (chip->options & NAND_BUSWIDTH_16 &&
  649. !nand_opcode_8bits(command))
  650. column >>= 1;
  651. chip->cmd_ctrl(mtd, column, ctrl);
  652. ctrl &= ~NAND_CTRL_CHANGE;
  653. chip->cmd_ctrl(mtd, column >> 8, ctrl);
  654. }
  655. if (page_addr != -1) {
  656. chip->cmd_ctrl(mtd, page_addr, ctrl);
  657. chip->cmd_ctrl(mtd, page_addr >> 8,
  658. NAND_NCE | NAND_ALE);
  659. if (chip->options & NAND_ROW_ADDR_3)
  660. chip->cmd_ctrl(mtd, page_addr >> 16,
  661. NAND_NCE | NAND_ALE);
  662. }
  663. }
  664. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  665. /*
  666. * Program and erase have their own busy handlers status, sequential
  667. * in and status need no delay.
  668. */
  669. switch (command) {
  670. case NAND_CMD_CACHEDPROG:
  671. case NAND_CMD_PAGEPROG:
  672. case NAND_CMD_ERASE1:
  673. case NAND_CMD_ERASE2:
  674. case NAND_CMD_SEQIN:
  675. case NAND_CMD_RNDIN:
  676. case NAND_CMD_STATUS:
  677. case NAND_CMD_READID:
  678. case NAND_CMD_SET_FEATURES:
  679. return;
  680. case NAND_CMD_RESET:
  681. if (chip->dev_ready)
  682. break;
  683. udelay(chip->chip_delay);
  684. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  685. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  686. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  687. NAND_NCE | NAND_CTRL_CHANGE);
  688. /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
  689. nand_wait_status_ready(mtd, 250);
  690. return;
  691. case NAND_CMD_RNDOUT:
  692. /* No ready / busy check necessary */
  693. chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
  694. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  695. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  696. NAND_NCE | NAND_CTRL_CHANGE);
  697. return;
  698. case NAND_CMD_READ0:
  699. chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
  700. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  701. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  702. NAND_NCE | NAND_CTRL_CHANGE);
  703. /* This applies to read commands */
  704. default:
  705. /*
  706. * If we don't have access to the busy pin, we apply the given
  707. * command delay.
  708. */
  709. if (!chip->dev_ready) {
  710. udelay(chip->chip_delay);
  711. return;
  712. }
  713. }
  714. /*
  715. * Apply this short delay always to ensure that we do wait tWB in
  716. * any case on any machine.
  717. */
  718. ndelay(100);
  719. nand_wait_ready(mtd);
  720. }
  721. /**
  722. * panic_nand_get_device - [GENERIC] Get chip for selected access
  723. * @chip: the nand chip descriptor
  724. * @mtd: MTD device structure
  725. * @new_state: the state which is requested
  726. *
  727. * Used when in panic, no locks are taken.
  728. */
  729. static void panic_nand_get_device(struct nand_chip *chip,
  730. struct mtd_info *mtd, int new_state)
  731. {
  732. /* Hardware controller shared among independent devices */
  733. chip->controller->active = chip;
  734. chip->state = new_state;
  735. }
  736. /**
  737. * nand_get_device - [GENERIC] Get chip for selected access
  738. * @mtd: MTD device structure
  739. * @new_state: the state which is requested
  740. *
  741. * Get the device and lock it for exclusive access
  742. */
  743. static int
  744. nand_get_device(struct mtd_info *mtd, int new_state)
  745. {
  746. struct nand_chip *chip = mtd_to_nand(mtd);
  747. chip->state = new_state;
  748. return 0;
  749. }
  750. /**
  751. * panic_nand_wait - [GENERIC] wait until the command is done
  752. * @mtd: MTD device structure
  753. * @chip: NAND chip structure
  754. * @timeo: timeout
  755. *
  756. * Wait for command done. This is a helper function for nand_wait used when
  757. * we are in interrupt context. May happen when in panic and trying to write
  758. * an oops through mtdoops.
  759. */
  760. static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
  761. unsigned long timeo)
  762. {
  763. int i;
  764. for (i = 0; i < timeo; i++) {
  765. if (chip->dev_ready) {
  766. if (chip->dev_ready(mtd))
  767. break;
  768. } else {
  769. int ret;
  770. u8 status;
  771. ret = nand_read_data_op(chip, &status, sizeof(status),
  772. true);
  773. if (ret)
  774. return;
  775. if (status & NAND_STATUS_READY)
  776. break;
  777. }
  778. mdelay(1);
  779. }
  780. }
  781. /**
  782. * nand_wait - [DEFAULT] wait until the command is done
  783. * @mtd: MTD device structure
  784. * @chip: NAND chip structure
  785. *
  786. * Wait for command done. This applies to erase and program only.
  787. */
  788. static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
  789. {
  790. unsigned long timeo = 400;
  791. u8 status;
  792. int ret;
  793. led_trigger_event(nand_led_trigger, LED_FULL);
  794. /*
  795. * Apply this short delay always to ensure that we do wait tWB in any
  796. * case on any machine.
  797. */
  798. ndelay(100);
  799. ret = nand_status_op(chip, NULL);
  800. if (ret)
  801. return ret;
  802. u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
  803. u32 time_start;
  804. time_start = get_timer(0);
  805. while (get_timer(time_start) < timer) {
  806. if (chip->dev_ready) {
  807. if (chip->dev_ready(mtd))
  808. break;
  809. } else {
  810. ret = nand_read_data_op(chip, &status,
  811. sizeof(status), true);
  812. if (ret)
  813. return ret;
  814. if (status & NAND_STATUS_READY)
  815. break;
  816. }
  817. }
  818. led_trigger_event(nand_led_trigger, LED_OFF);
  819. ret = nand_read_data_op(chip, &status, sizeof(status), true);
  820. if (ret)
  821. return ret;
  822. /* This can happen if in case of timeout or buggy dev_ready */
  823. WARN_ON(!(status & NAND_STATUS_READY));
  824. return status;
  825. }
  826. /**
  827. * nand_reset_data_interface - Reset data interface and timings
  828. * @chip: The NAND chip
  829. * @chipnr: Internal die id
  830. *
  831. * Reset the Data interface and timings to ONFI mode 0.
  832. *
  833. * Returns 0 for success or negative error code otherwise.
  834. */
  835. static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
  836. {
  837. struct mtd_info *mtd = nand_to_mtd(chip);
  838. const struct nand_data_interface *conf;
  839. int ret;
  840. if (!chip->setup_data_interface)
  841. return 0;
  842. /*
  843. * The ONFI specification says:
  844. * "
  845. * To transition from NV-DDR or NV-DDR2 to the SDR data
  846. * interface, the host shall use the Reset (FFh) command
  847. * using SDR timing mode 0. A device in any timing mode is
  848. * required to recognize Reset (FFh) command issued in SDR
  849. * timing mode 0.
  850. * "
  851. *
  852. * Configure the data interface in SDR mode and set the
  853. * timings to timing mode 0.
  854. */
  855. conf = nand_get_default_data_interface();
  856. ret = chip->setup_data_interface(mtd, chipnr, conf);
  857. if (ret)
  858. pr_err("Failed to configure data interface to SDR timing mode 0\n");
  859. return ret;
  860. }
  861. /**
  862. * nand_setup_data_interface - Setup the best data interface and timings
  863. * @chip: The NAND chip
  864. * @chipnr: Internal die id
  865. *
  866. * Find and configure the best data interface and NAND timings supported by
  867. * the chip and the driver.
  868. * First tries to retrieve supported timing modes from ONFI information,
  869. * and if the NAND chip does not support ONFI, relies on the
  870. * ->onfi_timing_mode_default specified in the nand_ids table.
  871. *
  872. * Returns 0 for success or negative error code otherwise.
  873. */
  874. static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
  875. {
  876. struct mtd_info *mtd = nand_to_mtd(chip);
  877. int ret;
  878. if (!chip->setup_data_interface || !chip->data_interface)
  879. return 0;
  880. /*
  881. * Ensure the timing mode has been changed on the chip side
  882. * before changing timings on the controller side.
  883. */
  884. if (chip->onfi_version) {
  885. u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
  886. chip->onfi_timing_mode_default,
  887. };
  888. ret = chip->onfi_set_features(mtd, chip,
  889. ONFI_FEATURE_ADDR_TIMING_MODE,
  890. tmode_param);
  891. if (ret)
  892. goto err;
  893. }
  894. ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
  895. err:
  896. return ret;
  897. }
  898. /**
  899. * nand_init_data_interface - find the best data interface and timings
  900. * @chip: The NAND chip
  901. *
  902. * Find the best data interface and NAND timings supported by the chip
  903. * and the driver.
  904. * First tries to retrieve supported timing modes from ONFI information,
  905. * and if the NAND chip does not support ONFI, relies on the
  906. * ->onfi_timing_mode_default specified in the nand_ids table. After this
  907. * function nand_chip->data_interface is initialized with the best timing mode
  908. * available.
  909. *
  910. * Returns 0 for success or negative error code otherwise.
  911. */
  912. static int nand_init_data_interface(struct nand_chip *chip)
  913. {
  914. struct mtd_info *mtd = nand_to_mtd(chip);
  915. int modes, mode, ret;
  916. if (!chip->setup_data_interface)
  917. return 0;
  918. /*
  919. * First try to identify the best timings from ONFI parameters and
  920. * if the NAND does not support ONFI, fallback to the default ONFI
  921. * timing mode.
  922. */
  923. modes = onfi_get_async_timing_mode(chip);
  924. if (modes == ONFI_TIMING_MODE_UNKNOWN) {
  925. if (!chip->onfi_timing_mode_default)
  926. return 0;
  927. modes = GENMASK(chip->onfi_timing_mode_default, 0);
  928. }
  929. chip->data_interface = kzalloc(sizeof(*chip->data_interface),
  930. GFP_KERNEL);
  931. if (!chip->data_interface)
  932. return -ENOMEM;
  933. for (mode = fls(modes) - 1; mode >= 0; mode--) {
  934. ret = onfi_init_data_interface(chip, chip->data_interface,
  935. NAND_SDR_IFACE, mode);
  936. if (ret)
  937. continue;
  938. /* Pass -1 to only */
  939. ret = chip->setup_data_interface(mtd,
  940. NAND_DATA_IFACE_CHECK_ONLY,
  941. chip->data_interface);
  942. if (!ret) {
  943. chip->onfi_timing_mode_default = mode;
  944. break;
  945. }
  946. }
  947. return 0;
  948. }
  949. static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
  950. {
  951. kfree(chip->data_interface);
  952. }
  953. /**
  954. * nand_read_page_op - Do a READ PAGE operation
  955. * @chip: The NAND chip
  956. * @page: page to read
  957. * @offset_in_page: offset within the page
  958. * @buf: buffer used to store the data
  959. * @len: length of the buffer
  960. *
  961. * This function issues a READ PAGE operation.
  962. * This function does not select/unselect the CS line.
  963. *
  964. * Returns 0 on success, a negative error code otherwise.
  965. */
  966. int nand_read_page_op(struct nand_chip *chip, unsigned int page,
  967. unsigned int offset_in_page, void *buf, unsigned int len)
  968. {
  969. struct mtd_info *mtd = nand_to_mtd(chip);
  970. if (len && !buf)
  971. return -EINVAL;
  972. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  973. return -EINVAL;
  974. chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page);
  975. if (len)
  976. chip->read_buf(mtd, buf, len);
  977. return 0;
  978. }
  979. EXPORT_SYMBOL_GPL(nand_read_page_op);
  980. /**
  981. * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
  982. * @chip: The NAND chip
  983. * @page: parameter page to read
  984. * @buf: buffer used to store the data
  985. * @len: length of the buffer
  986. *
  987. * This function issues a READ PARAMETER PAGE operation.
  988. * This function does not select/unselect the CS line.
  989. *
  990. * Returns 0 on success, a negative error code otherwise.
  991. */
  992. static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
  993. unsigned int len)
  994. {
  995. struct mtd_info *mtd = nand_to_mtd(chip);
  996. unsigned int i;
  997. u8 *p = buf;
  998. if (len && !buf)
  999. return -EINVAL;
  1000. chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1);
  1001. for (i = 0; i < len; i++)
  1002. p[i] = chip->read_byte(mtd);
  1003. return 0;
  1004. }
  1005. /**
  1006. * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
  1007. * @chip: The NAND chip
  1008. * @offset_in_page: offset within the page
  1009. * @buf: buffer used to store the data
  1010. * @len: length of the buffer
  1011. * @force_8bit: force 8-bit bus access
  1012. *
  1013. * This function issues a CHANGE READ COLUMN operation.
  1014. * This function does not select/unselect the CS line.
  1015. *
  1016. * Returns 0 on success, a negative error code otherwise.
  1017. */
  1018. int nand_change_read_column_op(struct nand_chip *chip,
  1019. unsigned int offset_in_page, void *buf,
  1020. unsigned int len, bool force_8bit)
  1021. {
  1022. struct mtd_info *mtd = nand_to_mtd(chip);
  1023. if (len && !buf)
  1024. return -EINVAL;
  1025. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1026. return -EINVAL;
  1027. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1);
  1028. if (len)
  1029. chip->read_buf(mtd, buf, len);
  1030. return 0;
  1031. }
  1032. EXPORT_SYMBOL_GPL(nand_change_read_column_op);
  1033. /**
  1034. * nand_read_oob_op - Do a READ OOB operation
  1035. * @chip: The NAND chip
  1036. * @page: page to read
  1037. * @offset_in_oob: offset within the OOB area
  1038. * @buf: buffer used to store the data
  1039. * @len: length of the buffer
  1040. *
  1041. * This function issues a READ OOB operation.
  1042. * This function does not select/unselect the CS line.
  1043. *
  1044. * Returns 0 on success, a negative error code otherwise.
  1045. */
  1046. int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
  1047. unsigned int offset_in_oob, void *buf, unsigned int len)
  1048. {
  1049. struct mtd_info *mtd = nand_to_mtd(chip);
  1050. if (len && !buf)
  1051. return -EINVAL;
  1052. if (offset_in_oob + len > mtd->oobsize)
  1053. return -EINVAL;
  1054. chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page);
  1055. if (len)
  1056. chip->read_buf(mtd, buf, len);
  1057. return 0;
  1058. }
  1059. EXPORT_SYMBOL_GPL(nand_read_oob_op);
  1060. /**
  1061. * nand_prog_page_begin_op - starts a PROG PAGE operation
  1062. * @chip: The NAND chip
  1063. * @page: page to write
  1064. * @offset_in_page: offset within the page
  1065. * @buf: buffer containing the data to write to the page
  1066. * @len: length of the buffer
  1067. *
  1068. * This function issues the first half of a PROG PAGE operation.
  1069. * This function does not select/unselect the CS line.
  1070. *
  1071. * Returns 0 on success, a negative error code otherwise.
  1072. */
  1073. int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
  1074. unsigned int offset_in_page, const void *buf,
  1075. unsigned int len)
  1076. {
  1077. struct mtd_info *mtd = nand_to_mtd(chip);
  1078. if (len && !buf)
  1079. return -EINVAL;
  1080. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1081. return -EINVAL;
  1082. chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
  1083. if (buf)
  1084. chip->write_buf(mtd, buf, len);
  1085. return 0;
  1086. }
  1087. EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
  1088. /**
  1089. * nand_prog_page_end_op - ends a PROG PAGE operation
  1090. * @chip: The NAND chip
  1091. *
  1092. * This function issues the second half of a PROG PAGE operation.
  1093. * This function does not select/unselect the CS line.
  1094. *
  1095. * Returns 0 on success, a negative error code otherwise.
  1096. */
  1097. int nand_prog_page_end_op(struct nand_chip *chip)
  1098. {
  1099. struct mtd_info *mtd = nand_to_mtd(chip);
  1100. int status;
  1101. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1102. status = chip->waitfunc(mtd, chip);
  1103. if (status & NAND_STATUS_FAIL)
  1104. return -EIO;
  1105. return 0;
  1106. }
  1107. EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
  1108. /**
  1109. * nand_prog_page_op - Do a full PROG PAGE operation
  1110. * @chip: The NAND chip
  1111. * @page: page to write
  1112. * @offset_in_page: offset within the page
  1113. * @buf: buffer containing the data to write to the page
  1114. * @len: length of the buffer
  1115. *
  1116. * This function issues a full PROG PAGE operation.
  1117. * This function does not select/unselect the CS line.
  1118. *
  1119. * Returns 0 on success, a negative error code otherwise.
  1120. */
  1121. int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
  1122. unsigned int offset_in_page, const void *buf,
  1123. unsigned int len)
  1124. {
  1125. struct mtd_info *mtd = nand_to_mtd(chip);
  1126. int status;
  1127. if (!len || !buf)
  1128. return -EINVAL;
  1129. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1130. return -EINVAL;
  1131. chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
  1132. chip->write_buf(mtd, buf, len);
  1133. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1134. status = chip->waitfunc(mtd, chip);
  1135. if (status & NAND_STATUS_FAIL)
  1136. return -EIO;
  1137. return 0;
  1138. }
  1139. EXPORT_SYMBOL_GPL(nand_prog_page_op);
  1140. /**
  1141. * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
  1142. * @chip: The NAND chip
  1143. * @offset_in_page: offset within the page
  1144. * @buf: buffer containing the data to send to the NAND
  1145. * @len: length of the buffer
  1146. * @force_8bit: force 8-bit bus access
  1147. *
  1148. * This function issues a CHANGE WRITE COLUMN operation.
  1149. * This function does not select/unselect the CS line.
  1150. *
  1151. * Returns 0 on success, a negative error code otherwise.
  1152. */
  1153. int nand_change_write_column_op(struct nand_chip *chip,
  1154. unsigned int offset_in_page,
  1155. const void *buf, unsigned int len,
  1156. bool force_8bit)
  1157. {
  1158. struct mtd_info *mtd = nand_to_mtd(chip);
  1159. if (len && !buf)
  1160. return -EINVAL;
  1161. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1162. return -EINVAL;
  1163. chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1);
  1164. if (len)
  1165. chip->write_buf(mtd, buf, len);
  1166. return 0;
  1167. }
  1168. EXPORT_SYMBOL_GPL(nand_change_write_column_op);
  1169. /**
  1170. * nand_readid_op - Do a READID operation
  1171. * @chip: The NAND chip
  1172. * @addr: address cycle to pass after the READID command
  1173. * @buf: buffer used to store the ID
  1174. * @len: length of the buffer
  1175. *
  1176. * This function sends a READID command and reads back the ID returned by the
  1177. * NAND.
  1178. * This function does not select/unselect the CS line.
  1179. *
  1180. * Returns 0 on success, a negative error code otherwise.
  1181. */
  1182. int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
  1183. unsigned int len)
  1184. {
  1185. struct mtd_info *mtd = nand_to_mtd(chip);
  1186. unsigned int i;
  1187. u8 *id = buf;
  1188. if (len && !buf)
  1189. return -EINVAL;
  1190. chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1);
  1191. for (i = 0; i < len; i++)
  1192. id[i] = chip->read_byte(mtd);
  1193. return 0;
  1194. }
  1195. EXPORT_SYMBOL_GPL(nand_readid_op);
  1196. /**
  1197. * nand_status_op - Do a STATUS operation
  1198. * @chip: The NAND chip
  1199. * @status: out variable to store the NAND status
  1200. *
  1201. * This function sends a STATUS command and reads back the status returned by
  1202. * the NAND.
  1203. * This function does not select/unselect the CS line.
  1204. *
  1205. * Returns 0 on success, a negative error code otherwise.
  1206. */
  1207. int nand_status_op(struct nand_chip *chip, u8 *status)
  1208. {
  1209. struct mtd_info *mtd = nand_to_mtd(chip);
  1210. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  1211. if (status)
  1212. *status = chip->read_byte(mtd);
  1213. return 0;
  1214. }
  1215. EXPORT_SYMBOL_GPL(nand_status_op);
  1216. /**
  1217. * nand_exit_status_op - Exit a STATUS operation
  1218. * @chip: The NAND chip
  1219. *
  1220. * This function sends a READ0 command to cancel the effect of the STATUS
  1221. * command to avoid reading only the status until a new read command is sent.
  1222. *
  1223. * This function does not select/unselect the CS line.
  1224. *
  1225. * Returns 0 on success, a negative error code otherwise.
  1226. */
  1227. int nand_exit_status_op(struct nand_chip *chip)
  1228. {
  1229. struct mtd_info *mtd = nand_to_mtd(chip);
  1230. chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
  1231. return 0;
  1232. }
  1233. EXPORT_SYMBOL_GPL(nand_exit_status_op);
  1234. /**
  1235. * nand_erase_op - Do an erase operation
  1236. * @chip: The NAND chip
  1237. * @eraseblock: block to erase
  1238. *
  1239. * This function sends an ERASE command and waits for the NAND to be ready
  1240. * before returning.
  1241. * This function does not select/unselect the CS line.
  1242. *
  1243. * Returns 0 on success, a negative error code otherwise.
  1244. */
  1245. int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
  1246. {
  1247. struct mtd_info *mtd = nand_to_mtd(chip);
  1248. unsigned int page = eraseblock <<
  1249. (chip->phys_erase_shift - chip->page_shift);
  1250. int status;
  1251. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
  1252. chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
  1253. status = chip->waitfunc(mtd, chip);
  1254. if (status < 0)
  1255. return status;
  1256. if (status & NAND_STATUS_FAIL)
  1257. return -EIO;
  1258. return 0;
  1259. }
  1260. EXPORT_SYMBOL_GPL(nand_erase_op);
  1261. /**
  1262. * nand_set_features_op - Do a SET FEATURES operation
  1263. * @chip: The NAND chip
  1264. * @feature: feature id
  1265. * @data: 4 bytes of data
  1266. *
  1267. * This function sends a SET FEATURES command and waits for the NAND to be
  1268. * ready before returning.
  1269. * This function does not select/unselect the CS line.
  1270. *
  1271. * Returns 0 on success, a negative error code otherwise.
  1272. */
  1273. static int nand_set_features_op(struct nand_chip *chip, u8 feature,
  1274. const void *data)
  1275. {
  1276. struct mtd_info *mtd = nand_to_mtd(chip);
  1277. const u8 *params = data;
  1278. int i, status;
  1279. chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1);
  1280. for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
  1281. chip->write_byte(mtd, params[i]);
  1282. status = chip->waitfunc(mtd, chip);
  1283. if (status & NAND_STATUS_FAIL)
  1284. return -EIO;
  1285. return 0;
  1286. }
  1287. /**
  1288. * nand_get_features_op - Do a GET FEATURES operation
  1289. * @chip: The NAND chip
  1290. * @feature: feature id
  1291. * @data: 4 bytes of data
  1292. *
  1293. * This function sends a GET FEATURES command and waits for the NAND to be
  1294. * ready before returning.
  1295. * This function does not select/unselect the CS line.
  1296. *
  1297. * Returns 0 on success, a negative error code otherwise.
  1298. */
  1299. static int nand_get_features_op(struct nand_chip *chip, u8 feature,
  1300. void *data)
  1301. {
  1302. struct mtd_info *mtd = nand_to_mtd(chip);
  1303. u8 *params = data;
  1304. int i;
  1305. chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1);
  1306. for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
  1307. params[i] = chip->read_byte(mtd);
  1308. return 0;
  1309. }
  1310. /**
  1311. * nand_reset_op - Do a reset operation
  1312. * @chip: The NAND chip
  1313. *
  1314. * This function sends a RESET command and waits for the NAND to be ready
  1315. * before returning.
  1316. * This function does not select/unselect the CS line.
  1317. *
  1318. * Returns 0 on success, a negative error code otherwise.
  1319. */
  1320. int nand_reset_op(struct nand_chip *chip)
  1321. {
  1322. struct mtd_info *mtd = nand_to_mtd(chip);
  1323. chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  1324. return 0;
  1325. }
  1326. EXPORT_SYMBOL_GPL(nand_reset_op);
  1327. /**
  1328. * nand_read_data_op - Read data from the NAND
  1329. * @chip: The NAND chip
  1330. * @buf: buffer used to store the data
  1331. * @len: length of the buffer
  1332. * @force_8bit: force 8-bit bus access
  1333. *
  1334. * This function does a raw data read on the bus. Usually used after launching
  1335. * another NAND operation like nand_read_page_op().
  1336. * This function does not select/unselect the CS line.
  1337. *
  1338. * Returns 0 on success, a negative error code otherwise.
  1339. */
  1340. int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
  1341. bool force_8bit)
  1342. {
  1343. struct mtd_info *mtd = nand_to_mtd(chip);
  1344. if (!len || !buf)
  1345. return -EINVAL;
  1346. if (force_8bit) {
  1347. u8 *p = buf;
  1348. unsigned int i;
  1349. for (i = 0; i < len; i++)
  1350. p[i] = chip->read_byte(mtd);
  1351. } else {
  1352. chip->read_buf(mtd, buf, len);
  1353. }
  1354. return 0;
  1355. }
  1356. EXPORT_SYMBOL_GPL(nand_read_data_op);
  1357. /**
  1358. * nand_write_data_op - Write data from the NAND
  1359. * @chip: The NAND chip
  1360. * @buf: buffer containing the data to send on the bus
  1361. * @len: length of the buffer
  1362. * @force_8bit: force 8-bit bus access
  1363. *
  1364. * This function does a raw data write on the bus. Usually used after launching
  1365. * another NAND operation like nand_write_page_begin_op().
  1366. * This function does not select/unselect the CS line.
  1367. *
  1368. * Returns 0 on success, a negative error code otherwise.
  1369. */
  1370. int nand_write_data_op(struct nand_chip *chip, const void *buf,
  1371. unsigned int len, bool force_8bit)
  1372. {
  1373. struct mtd_info *mtd = nand_to_mtd(chip);
  1374. if (!len || !buf)
  1375. return -EINVAL;
  1376. if (force_8bit) {
  1377. const u8 *p = buf;
  1378. unsigned int i;
  1379. for (i = 0; i < len; i++)
  1380. chip->write_byte(mtd, p[i]);
  1381. } else {
  1382. chip->write_buf(mtd, buf, len);
  1383. }
  1384. return 0;
  1385. }
  1386. EXPORT_SYMBOL_GPL(nand_write_data_op);
  1387. /**
  1388. * nand_reset - Reset and initialize a NAND device
  1389. * @chip: The NAND chip
  1390. * @chipnr: Internal die id
  1391. *
  1392. * Returns 0 for success or negative error code otherwise
  1393. */
  1394. int nand_reset(struct nand_chip *chip, int chipnr)
  1395. {
  1396. struct mtd_info *mtd = nand_to_mtd(chip);
  1397. int ret;
  1398. ret = nand_reset_data_interface(chip, chipnr);
  1399. if (ret)
  1400. return ret;
  1401. /*
  1402. * The CS line has to be released before we can apply the new NAND
  1403. * interface settings, hence this weird ->select_chip() dance.
  1404. */
  1405. chip->select_chip(mtd, chipnr);
  1406. ret = nand_reset_op(chip);
  1407. chip->select_chip(mtd, -1);
  1408. if (ret)
  1409. return ret;
  1410. chip->select_chip(mtd, chipnr);
  1411. ret = nand_setup_data_interface(chip, chipnr);
  1412. chip->select_chip(mtd, -1);
  1413. if (ret)
  1414. return ret;
  1415. return 0;
  1416. }
  1417. /**
  1418. * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
  1419. * @buf: buffer to test
  1420. * @len: buffer length
  1421. * @bitflips_threshold: maximum number of bitflips
  1422. *
  1423. * Check if a buffer contains only 0xff, which means the underlying region
  1424. * has been erased and is ready to be programmed.
  1425. * The bitflips_threshold specify the maximum number of bitflips before
  1426. * considering the region is not erased.
  1427. * Note: The logic of this function has been extracted from the memweight
  1428. * implementation, except that nand_check_erased_buf function exit before
  1429. * testing the whole buffer if the number of bitflips exceed the
  1430. * bitflips_threshold value.
  1431. *
  1432. * Returns a positive number of bitflips less than or equal to
  1433. * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
  1434. * threshold.
  1435. */
  1436. static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
  1437. {
  1438. const unsigned char *bitmap = buf;
  1439. int bitflips = 0;
  1440. int weight;
  1441. for (; len && ((uintptr_t)bitmap) % sizeof(long);
  1442. len--, bitmap++) {
  1443. weight = hweight8(*bitmap);
  1444. bitflips += BITS_PER_BYTE - weight;
  1445. if (unlikely(bitflips > bitflips_threshold))
  1446. return -EBADMSG;
  1447. }
  1448. for (; len >= 4; len -= 4, bitmap += 4) {
  1449. weight = hweight32(*((u32 *)bitmap));
  1450. bitflips += 32 - weight;
  1451. if (unlikely(bitflips > bitflips_threshold))
  1452. return -EBADMSG;
  1453. }
  1454. for (; len > 0; len--, bitmap++) {
  1455. weight = hweight8(*bitmap);
  1456. bitflips += BITS_PER_BYTE - weight;
  1457. if (unlikely(bitflips > bitflips_threshold))
  1458. return -EBADMSG;
  1459. }
  1460. return bitflips;
  1461. }
  1462. /**
  1463. * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
  1464. * 0xff data
  1465. * @data: data buffer to test
  1466. * @datalen: data length
  1467. * @ecc: ECC buffer
  1468. * @ecclen: ECC length
  1469. * @extraoob: extra OOB buffer
  1470. * @extraooblen: extra OOB length
  1471. * @bitflips_threshold: maximum number of bitflips
  1472. *
  1473. * Check if a data buffer and its associated ECC and OOB data contains only
  1474. * 0xff pattern, which means the underlying region has been erased and is
  1475. * ready to be programmed.
  1476. * The bitflips_threshold specify the maximum number of bitflips before
  1477. * considering the region as not erased.
  1478. *
  1479. * Note:
  1480. * 1/ ECC algorithms are working on pre-defined block sizes which are usually
  1481. * different from the NAND page size. When fixing bitflips, ECC engines will
  1482. * report the number of errors per chunk, and the NAND core infrastructure
  1483. * expect you to return the maximum number of bitflips for the whole page.
  1484. * This is why you should always use this function on a single chunk and
  1485. * not on the whole page. After checking each chunk you should update your
  1486. * max_bitflips value accordingly.
  1487. * 2/ When checking for bitflips in erased pages you should not only check
  1488. * the payload data but also their associated ECC data, because a user might
  1489. * have programmed almost all bits to 1 but a few. In this case, we
  1490. * shouldn't consider the chunk as erased, and checking ECC bytes prevent
  1491. * this case.
  1492. * 3/ The extraoob argument is optional, and should be used if some of your OOB
  1493. * data are protected by the ECC engine.
  1494. * It could also be used if you support subpages and want to attach some
  1495. * extra OOB data to an ECC chunk.
  1496. *
  1497. * Returns a positive number of bitflips less than or equal to
  1498. * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
  1499. * threshold. In case of success, the passed buffers are filled with 0xff.
  1500. */
  1501. int nand_check_erased_ecc_chunk(void *data, int datalen,
  1502. void *ecc, int ecclen,
  1503. void *extraoob, int extraooblen,
  1504. int bitflips_threshold)
  1505. {
  1506. int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
  1507. data_bitflips = nand_check_erased_buf(data, datalen,
  1508. bitflips_threshold);
  1509. if (data_bitflips < 0)
  1510. return data_bitflips;
  1511. bitflips_threshold -= data_bitflips;
  1512. ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
  1513. if (ecc_bitflips < 0)
  1514. return ecc_bitflips;
  1515. bitflips_threshold -= ecc_bitflips;
  1516. extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
  1517. bitflips_threshold);
  1518. if (extraoob_bitflips < 0)
  1519. return extraoob_bitflips;
  1520. if (data_bitflips)
  1521. memset(data, 0xff, datalen);
  1522. if (ecc_bitflips)
  1523. memset(ecc, 0xff, ecclen);
  1524. if (extraoob_bitflips)
  1525. memset(extraoob, 0xff, extraooblen);
  1526. return data_bitflips + ecc_bitflips + extraoob_bitflips;
  1527. }
  1528. EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
  1529. /**
  1530. * nand_read_page_raw - [INTERN] read raw page data without ecc
  1531. * @mtd: mtd info structure
  1532. * @chip: nand chip info structure
  1533. * @buf: buffer to store read data
  1534. * @oob_required: caller requires OOB data read to chip->oob_poi
  1535. * @page: page number to read
  1536. *
  1537. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  1538. */
  1539. static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1540. uint8_t *buf, int oob_required, int page)
  1541. {
  1542. int ret;
  1543. ret = nand_read_data_op(chip, buf, mtd->writesize, false);
  1544. if (ret)
  1545. return ret;
  1546. if (oob_required) {
  1547. ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
  1548. false);
  1549. if (ret)
  1550. return ret;
  1551. }
  1552. return 0;
  1553. }
  1554. /**
  1555. * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
  1556. * @mtd: mtd info structure
  1557. * @chip: nand chip info structure
  1558. * @buf: buffer to store read data
  1559. * @oob_required: caller requires OOB data read to chip->oob_poi
  1560. * @page: page number to read
  1561. *
  1562. * We need a special oob layout and handling even when OOB isn't used.
  1563. */
  1564. static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
  1565. struct nand_chip *chip, uint8_t *buf,
  1566. int oob_required, int page)
  1567. {
  1568. int eccsize = chip->ecc.size;
  1569. int eccbytes = chip->ecc.bytes;
  1570. uint8_t *oob = chip->oob_poi;
  1571. int steps, size, ret;
  1572. for (steps = chip->ecc.steps; steps > 0; steps--) {
  1573. ret = nand_read_data_op(chip, buf, eccsize, false);
  1574. if (ret)
  1575. return ret;
  1576. buf += eccsize;
  1577. if (chip->ecc.prepad) {
  1578. ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
  1579. false);
  1580. if (ret)
  1581. return ret;
  1582. oob += chip->ecc.prepad;
  1583. }
  1584. ret = nand_read_data_op(chip, oob, eccbytes, false);
  1585. if (ret)
  1586. return ret;
  1587. oob += eccbytes;
  1588. if (chip->ecc.postpad) {
  1589. ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
  1590. false);
  1591. if (ret)
  1592. return ret;
  1593. oob += chip->ecc.postpad;
  1594. }
  1595. }
  1596. size = mtd->oobsize - (oob - chip->oob_poi);
  1597. if (size) {
  1598. ret = nand_read_data_op(chip, oob, size, false);
  1599. if (ret)
  1600. return ret;
  1601. }
  1602. return 0;
  1603. }
  1604. /**
  1605. * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
  1606. * @mtd: mtd info structure
  1607. * @chip: nand chip info structure
  1608. * @buf: buffer to store read data
  1609. * @oob_required: caller requires OOB data read to chip->oob_poi
  1610. * @page: page number to read
  1611. */
  1612. static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  1613. uint8_t *buf, int oob_required, int page)
  1614. {
  1615. int i, eccsize = chip->ecc.size;
  1616. int eccbytes = chip->ecc.bytes;
  1617. int eccsteps = chip->ecc.steps;
  1618. uint8_t *p = buf;
  1619. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1620. uint8_t *ecc_code = chip->buffers->ecccode;
  1621. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1622. unsigned int max_bitflips = 0;
  1623. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  1624. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1625. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1626. for (i = 0; i < chip->ecc.total; i++)
  1627. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1628. eccsteps = chip->ecc.steps;
  1629. p = buf;
  1630. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1631. int stat;
  1632. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  1633. if (stat < 0) {
  1634. mtd->ecc_stats.failed++;
  1635. } else {
  1636. mtd->ecc_stats.corrected += stat;
  1637. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1638. }
  1639. }
  1640. return max_bitflips;
  1641. }
  1642. /**
  1643. * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
  1644. * @mtd: mtd info structure
  1645. * @chip: nand chip info structure
  1646. * @data_offs: offset of requested data within the page
  1647. * @readlen: data length
  1648. * @bufpoi: buffer to store read data
  1649. * @page: page number to read
  1650. */
  1651. static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
  1652. uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
  1653. int page)
  1654. {
  1655. int start_step, end_step, num_steps;
  1656. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1657. uint8_t *p;
  1658. int data_col_addr, i, gaps = 0;
  1659. int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
  1660. int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
  1661. int index;
  1662. unsigned int max_bitflips = 0;
  1663. int ret;
  1664. /* Column address within the page aligned to ECC size (256bytes) */
  1665. start_step = data_offs / chip->ecc.size;
  1666. end_step = (data_offs + readlen - 1) / chip->ecc.size;
  1667. num_steps = end_step - start_step + 1;
  1668. index = start_step * chip->ecc.bytes;
  1669. /* Data size aligned to ECC ecc.size */
  1670. datafrag_len = num_steps * chip->ecc.size;
  1671. eccfrag_len = num_steps * chip->ecc.bytes;
  1672. data_col_addr = start_step * chip->ecc.size;
  1673. /* If we read not a page aligned data */
  1674. if (data_col_addr != 0)
  1675. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
  1676. p = bufpoi + data_col_addr;
  1677. ret = nand_read_data_op(chip, p, datafrag_len, false);
  1678. if (ret)
  1679. return ret;
  1680. /* Calculate ECC */
  1681. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
  1682. chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
  1683. /*
  1684. * The performance is faster if we position offsets according to
  1685. * ecc.pos. Let's make sure that there are no gaps in ECC positions.
  1686. */
  1687. for (i = 0; i < eccfrag_len - 1; i++) {
  1688. if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
  1689. gaps = 1;
  1690. break;
  1691. }
  1692. }
  1693. if (gaps) {
  1694. ret = nand_change_read_column_op(chip, mtd->writesize,
  1695. chip->oob_poi, mtd->oobsize,
  1696. false);
  1697. if (ret)
  1698. return ret;
  1699. } else {
  1700. /*
  1701. * Send the command to read the particular ECC bytes take care
  1702. * about buswidth alignment in read_buf.
  1703. */
  1704. aligned_pos = eccpos[index] & ~(busw - 1);
  1705. aligned_len = eccfrag_len;
  1706. if (eccpos[index] & (busw - 1))
  1707. aligned_len++;
  1708. if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
  1709. aligned_len++;
  1710. ret = nand_change_read_column_op(chip,
  1711. mtd->writesize + aligned_pos,
  1712. &chip->oob_poi[aligned_pos],
  1713. aligned_len, false);
  1714. if (ret)
  1715. return ret;
  1716. }
  1717. for (i = 0; i < eccfrag_len; i++)
  1718. chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
  1719. p = bufpoi + data_col_addr;
  1720. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
  1721. int stat;
  1722. stat = chip->ecc.correct(mtd, p,
  1723. &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
  1724. if (stat == -EBADMSG &&
  1725. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1726. /* check for empty pages with bitflips */
  1727. stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
  1728. &chip->buffers->ecccode[i],
  1729. chip->ecc.bytes,
  1730. NULL, 0,
  1731. chip->ecc.strength);
  1732. }
  1733. if (stat < 0) {
  1734. mtd->ecc_stats.failed++;
  1735. } else {
  1736. mtd->ecc_stats.corrected += stat;
  1737. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1738. }
  1739. }
  1740. return max_bitflips;
  1741. }
  1742. /**
  1743. * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
  1744. * @mtd: mtd info structure
  1745. * @chip: nand chip info structure
  1746. * @buf: buffer to store read data
  1747. * @oob_required: caller requires OOB data read to chip->oob_poi
  1748. * @page: page number to read
  1749. *
  1750. * Not for syndrome calculating ECC controllers which need a special oob layout.
  1751. */
  1752. static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  1753. uint8_t *buf, int oob_required, int page)
  1754. {
  1755. int i, eccsize = chip->ecc.size;
  1756. int eccbytes = chip->ecc.bytes;
  1757. int eccsteps = chip->ecc.steps;
  1758. uint8_t *p = buf;
  1759. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1760. uint8_t *ecc_code = chip->buffers->ecccode;
  1761. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1762. unsigned int max_bitflips = 0;
  1763. int ret;
  1764. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1765. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1766. ret = nand_read_data_op(chip, p, eccsize, false);
  1767. if (ret)
  1768. return ret;
  1769. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1770. }
  1771. ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  1772. if (ret)
  1773. return ret;
  1774. for (i = 0; i < chip->ecc.total; i++)
  1775. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1776. eccsteps = chip->ecc.steps;
  1777. p = buf;
  1778. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1779. int stat;
  1780. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  1781. if (stat == -EBADMSG &&
  1782. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1783. /* check for empty pages with bitflips */
  1784. stat = nand_check_erased_ecc_chunk(p, eccsize,
  1785. &ecc_code[i], eccbytes,
  1786. NULL, 0,
  1787. chip->ecc.strength);
  1788. }
  1789. if (stat < 0) {
  1790. mtd->ecc_stats.failed++;
  1791. } else {
  1792. mtd->ecc_stats.corrected += stat;
  1793. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1794. }
  1795. }
  1796. return max_bitflips;
  1797. }
  1798. /**
  1799. * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
  1800. * @mtd: mtd info structure
  1801. * @chip: nand chip info structure
  1802. * @buf: buffer to store read data
  1803. * @oob_required: caller requires OOB data read to chip->oob_poi
  1804. * @page: page number to read
  1805. *
  1806. * Hardware ECC for large page chips, require OOB to be read first. For this
  1807. * ECC mode, the write_page method is re-used from ECC_HW. These methods
  1808. * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
  1809. * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
  1810. * the data area, by overwriting the NAND manufacturer bad block markings.
  1811. */
  1812. static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
  1813. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  1814. {
  1815. int i, eccsize = chip->ecc.size;
  1816. int eccbytes = chip->ecc.bytes;
  1817. int eccsteps = chip->ecc.steps;
  1818. uint8_t *p = buf;
  1819. uint8_t *ecc_code = chip->buffers->ecccode;
  1820. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1821. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1822. unsigned int max_bitflips = 0;
  1823. int ret;
  1824. /* Read the OOB area first */
  1825. ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
  1826. if (ret)
  1827. return ret;
  1828. ret = nand_read_page_op(chip, page, 0, NULL, 0);
  1829. if (ret)
  1830. return ret;
  1831. for (i = 0; i < chip->ecc.total; i++)
  1832. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1833. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1834. int stat;
  1835. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1836. ret = nand_read_data_op(chip, p, eccsize, false);
  1837. if (ret)
  1838. return ret;
  1839. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1840. stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
  1841. if (stat == -EBADMSG &&
  1842. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1843. /* check for empty pages with bitflips */
  1844. stat = nand_check_erased_ecc_chunk(p, eccsize,
  1845. &ecc_code[i], eccbytes,
  1846. NULL, 0,
  1847. chip->ecc.strength);
  1848. }
  1849. if (stat < 0) {
  1850. mtd->ecc_stats.failed++;
  1851. } else {
  1852. mtd->ecc_stats.corrected += stat;
  1853. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1854. }
  1855. }
  1856. return max_bitflips;
  1857. }
  1858. /**
  1859. * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
  1860. * @mtd: mtd info structure
  1861. * @chip: nand chip info structure
  1862. * @buf: buffer to store read data
  1863. * @oob_required: caller requires OOB data read to chip->oob_poi
  1864. * @page: page number to read
  1865. *
  1866. * The hw generator calculates the error syndrome automatically. Therefore we
  1867. * need a special oob layout and handling.
  1868. */
  1869. static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  1870. uint8_t *buf, int oob_required, int page)
  1871. {
  1872. int ret, i, eccsize = chip->ecc.size;
  1873. int eccbytes = chip->ecc.bytes;
  1874. int eccsteps = chip->ecc.steps;
  1875. int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  1876. uint8_t *p = buf;
  1877. uint8_t *oob = chip->oob_poi;
  1878. unsigned int max_bitflips = 0;
  1879. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1880. int stat;
  1881. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1882. ret = nand_read_data_op(chip, p, eccsize, false);
  1883. if (ret)
  1884. return ret;
  1885. if (chip->ecc.prepad) {
  1886. ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
  1887. false);
  1888. if (ret)
  1889. return ret;
  1890. oob += chip->ecc.prepad;
  1891. }
  1892. chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
  1893. ret = nand_read_data_op(chip, oob, eccbytes, false);
  1894. if (ret)
  1895. return ret;
  1896. stat = chip->ecc.correct(mtd, p, oob, NULL);
  1897. oob += eccbytes;
  1898. if (chip->ecc.postpad) {
  1899. ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
  1900. false);
  1901. if (ret)
  1902. return ret;
  1903. oob += chip->ecc.postpad;
  1904. }
  1905. if (stat == -EBADMSG &&
  1906. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1907. /* check for empty pages with bitflips */
  1908. stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
  1909. oob - eccpadbytes,
  1910. eccpadbytes,
  1911. NULL, 0,
  1912. chip->ecc.strength);
  1913. }
  1914. if (stat < 0) {
  1915. mtd->ecc_stats.failed++;
  1916. } else {
  1917. mtd->ecc_stats.corrected += stat;
  1918. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1919. }
  1920. }
  1921. /* Calculate remaining oob bytes */
  1922. i = mtd->oobsize - (oob - chip->oob_poi);
  1923. if (i) {
  1924. ret = nand_read_data_op(chip, oob, i, false);
  1925. if (ret)
  1926. return ret;
  1927. }
  1928. return max_bitflips;
  1929. }
  1930. /**
  1931. * nand_transfer_oob - [INTERN] Transfer oob to client buffer
  1932. * @chip: nand chip structure
  1933. * @oob: oob destination address
  1934. * @ops: oob ops structure
  1935. * @len: size of oob to transfer
  1936. */
  1937. static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
  1938. struct mtd_oob_ops *ops, size_t len)
  1939. {
  1940. switch (ops->mode) {
  1941. case MTD_OPS_PLACE_OOB:
  1942. case MTD_OPS_RAW:
  1943. memcpy(oob, chip->oob_poi + ops->ooboffs, len);
  1944. return oob + len;
  1945. case MTD_OPS_AUTO_OOB: {
  1946. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  1947. uint32_t boffs = 0, roffs = ops->ooboffs;
  1948. size_t bytes = 0;
  1949. for (; free->length && len; free++, len -= bytes) {
  1950. /* Read request not from offset 0? */
  1951. if (unlikely(roffs)) {
  1952. if (roffs >= free->length) {
  1953. roffs -= free->length;
  1954. continue;
  1955. }
  1956. boffs = free->offset + roffs;
  1957. bytes = min_t(size_t, len,
  1958. (free->length - roffs));
  1959. roffs = 0;
  1960. } else {
  1961. bytes = min_t(size_t, len, free->length);
  1962. boffs = free->offset;
  1963. }
  1964. memcpy(oob, chip->oob_poi + boffs, bytes);
  1965. oob += bytes;
  1966. }
  1967. return oob;
  1968. }
  1969. default:
  1970. BUG();
  1971. }
  1972. return NULL;
  1973. }
  1974. /**
  1975. * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
  1976. * @mtd: MTD device structure
  1977. * @retry_mode: the retry mode to use
  1978. *
  1979. * Some vendors supply a special command to shift the Vt threshold, to be used
  1980. * when there are too many bitflips in a page (i.e., ECC error). After setting
  1981. * a new threshold, the host should retry reading the page.
  1982. */
  1983. static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
  1984. {
  1985. struct nand_chip *chip = mtd_to_nand(mtd);
  1986. pr_debug("setting READ RETRY mode %d\n", retry_mode);
  1987. if (retry_mode >= chip->read_retries)
  1988. return -EINVAL;
  1989. if (!chip->setup_read_retry)
  1990. return -EOPNOTSUPP;
  1991. return chip->setup_read_retry(mtd, retry_mode);
  1992. }
  1993. /**
  1994. * nand_do_read_ops - [INTERN] Read data with ECC
  1995. * @mtd: MTD device structure
  1996. * @from: offset to read from
  1997. * @ops: oob ops structure
  1998. *
  1999. * Internal function. Called with chip held.
  2000. */
  2001. static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
  2002. struct mtd_oob_ops *ops)
  2003. {
  2004. int chipnr, page, realpage, col, bytes, aligned, oob_required;
  2005. struct nand_chip *chip = mtd_to_nand(mtd);
  2006. int ret = 0;
  2007. uint32_t readlen = ops->len;
  2008. uint32_t oobreadlen = ops->ooblen;
  2009. uint32_t max_oobsize = mtd_oobavail(mtd, ops);
  2010. uint8_t *bufpoi, *oob, *buf;
  2011. int use_bufpoi;
  2012. unsigned int max_bitflips = 0;
  2013. int retry_mode = 0;
  2014. bool ecc_fail = false;
  2015. chipnr = (int)(from >> chip->chip_shift);
  2016. chip->select_chip(mtd, chipnr);
  2017. realpage = (int)(from >> chip->page_shift);
  2018. page = realpage & chip->pagemask;
  2019. col = (int)(from & (mtd->writesize - 1));
  2020. buf = ops->datbuf;
  2021. oob = ops->oobbuf;
  2022. oob_required = oob ? 1 : 0;
  2023. while (1) {
  2024. unsigned int ecc_failures = mtd->ecc_stats.failed;
  2025. WATCHDOG_RESET();
  2026. bytes = min(mtd->writesize - col, readlen);
  2027. aligned = (bytes == mtd->writesize);
  2028. if (!aligned)
  2029. use_bufpoi = 1;
  2030. else if (chip->options & NAND_USE_BOUNCE_BUFFER)
  2031. use_bufpoi = !IS_ALIGNED((unsigned long)buf,
  2032. chip->buf_align);
  2033. else
  2034. use_bufpoi = 0;
  2035. /* Is the current page in the buffer? */
  2036. if (realpage != chip->pagebuf || oob) {
  2037. bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
  2038. if (use_bufpoi && aligned)
  2039. pr_debug("%s: using read bounce buffer for buf@%p\n",
  2040. __func__, buf);
  2041. read_retry:
  2042. if (nand_standard_page_accessors(&chip->ecc)) {
  2043. ret = nand_read_page_op(chip, page, 0, NULL, 0);
  2044. if (ret)
  2045. break;
  2046. }
  2047. /*
  2048. * Now read the page into the buffer. Absent an error,
  2049. * the read methods return max bitflips per ecc step.
  2050. */
  2051. if (unlikely(ops->mode == MTD_OPS_RAW))
  2052. ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
  2053. oob_required,
  2054. page);
  2055. else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
  2056. !oob)
  2057. ret = chip->ecc.read_subpage(mtd, chip,
  2058. col, bytes, bufpoi,
  2059. page);
  2060. else
  2061. ret = chip->ecc.read_page(mtd, chip, bufpoi,
  2062. oob_required, page);
  2063. if (ret < 0) {
  2064. if (use_bufpoi)
  2065. /* Invalidate page cache */
  2066. chip->pagebuf = -1;
  2067. break;
  2068. }
  2069. max_bitflips = max_t(unsigned int, max_bitflips, ret);
  2070. /* Transfer not aligned data */
  2071. if (use_bufpoi) {
  2072. if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
  2073. !(mtd->ecc_stats.failed - ecc_failures) &&
  2074. (ops->mode != MTD_OPS_RAW)) {
  2075. chip->pagebuf = realpage;
  2076. chip->pagebuf_bitflips = ret;
  2077. } else {
  2078. /* Invalidate page cache */
  2079. chip->pagebuf = -1;
  2080. }
  2081. memcpy(buf, chip->buffers->databuf + col, bytes);
  2082. }
  2083. if (unlikely(oob)) {
  2084. int toread = min(oobreadlen, max_oobsize);
  2085. if (toread) {
  2086. oob = nand_transfer_oob(chip,
  2087. oob, ops, toread);
  2088. oobreadlen -= toread;
  2089. }
  2090. }
  2091. if (chip->options & NAND_NEED_READRDY) {
  2092. /* Apply delay or wait for ready/busy pin */
  2093. if (!chip->dev_ready)
  2094. udelay(chip->chip_delay);
  2095. else
  2096. nand_wait_ready(mtd);
  2097. }
  2098. if (mtd->ecc_stats.failed - ecc_failures) {
  2099. if (retry_mode + 1 < chip->read_retries) {
  2100. retry_mode++;
  2101. ret = nand_setup_read_retry(mtd,
  2102. retry_mode);
  2103. if (ret < 0)
  2104. break;
  2105. /* Reset failures; retry */
  2106. mtd->ecc_stats.failed = ecc_failures;
  2107. goto read_retry;
  2108. } else {
  2109. /* No more retry modes; real failure */
  2110. ecc_fail = true;
  2111. }
  2112. }
  2113. buf += bytes;
  2114. } else {
  2115. memcpy(buf, chip->buffers->databuf + col, bytes);
  2116. buf += bytes;
  2117. max_bitflips = max_t(unsigned int, max_bitflips,
  2118. chip->pagebuf_bitflips);
  2119. }
  2120. readlen -= bytes;
  2121. /* Reset to retry mode 0 */
  2122. if (retry_mode) {
  2123. ret = nand_setup_read_retry(mtd, 0);
  2124. if (ret < 0)
  2125. break;
  2126. retry_mode = 0;
  2127. }
  2128. if (!readlen)
  2129. break;
  2130. /* For subsequent reads align to page boundary */
  2131. col = 0;
  2132. /* Increment page address */
  2133. realpage++;
  2134. page = realpage & chip->pagemask;
  2135. /* Check, if we cross a chip boundary */
  2136. if (!page) {
  2137. chipnr++;
  2138. chip->select_chip(mtd, -1);
  2139. chip->select_chip(mtd, chipnr);
  2140. }
  2141. }
  2142. chip->select_chip(mtd, -1);
  2143. ops->retlen = ops->len - (size_t) readlen;
  2144. if (oob)
  2145. ops->oobretlen = ops->ooblen - oobreadlen;
  2146. if (ret < 0)
  2147. return ret;
  2148. if (ecc_fail)
  2149. return -EBADMSG;
  2150. return max_bitflips;
  2151. }
  2152. /**
  2153. * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
  2154. * @mtd: mtd info structure
  2155. * @chip: nand chip info structure
  2156. * @page: page number to read
  2157. */
  2158. static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  2159. int page)
  2160. {
  2161. return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
  2162. }
  2163. /**
  2164. * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
  2165. * with syndromes
  2166. * @mtd: mtd info structure
  2167. * @chip: nand chip info structure
  2168. * @page: page number to read
  2169. */
  2170. static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  2171. int page)
  2172. {
  2173. int length = mtd->oobsize;
  2174. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  2175. int eccsize = chip->ecc.size;
  2176. uint8_t *bufpoi = chip->oob_poi;
  2177. int i, toread, sndrnd = 0, pos, ret;
  2178. ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
  2179. if (ret)
  2180. return ret;
  2181. for (i = 0; i < chip->ecc.steps; i++) {
  2182. if (sndrnd) {
  2183. int ret;
  2184. pos = eccsize + i * (eccsize + chunk);
  2185. if (mtd->writesize > 512)
  2186. ret = nand_change_read_column_op(chip, pos,
  2187. NULL, 0,
  2188. false);
  2189. else
  2190. ret = nand_read_page_op(chip, page, pos, NULL,
  2191. 0);
  2192. if (ret)
  2193. return ret;
  2194. } else
  2195. sndrnd = 1;
  2196. toread = min_t(int, length, chunk);
  2197. ret = nand_read_data_op(chip, bufpoi, toread, false);
  2198. if (ret)
  2199. return ret;
  2200. bufpoi += toread;
  2201. length -= toread;
  2202. }
  2203. if (length > 0) {
  2204. ret = nand_read_data_op(chip, bufpoi, length, false);
  2205. if (ret)
  2206. return ret;
  2207. }
  2208. return 0;
  2209. }
  2210. /**
  2211. * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
  2212. * @mtd: mtd info structure
  2213. * @chip: nand chip info structure
  2214. * @page: page number to write
  2215. */
  2216. static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  2217. int page)
  2218. {
  2219. return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
  2220. mtd->oobsize);
  2221. }
  2222. /**
  2223. * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
  2224. * with syndrome - only for large page flash
  2225. * @mtd: mtd info structure
  2226. * @chip: nand chip info structure
  2227. * @page: page number to write
  2228. */
  2229. static int nand_write_oob_syndrome(struct mtd_info *mtd,
  2230. struct nand_chip *chip, int page)
  2231. {
  2232. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  2233. int eccsize = chip->ecc.size, length = mtd->oobsize;
  2234. int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
  2235. const uint8_t *bufpoi = chip->oob_poi;
  2236. /*
  2237. * data-ecc-data-ecc ... ecc-oob
  2238. * or
  2239. * data-pad-ecc-pad-data-pad .... ecc-pad-oob
  2240. */
  2241. if (!chip->ecc.prepad && !chip->ecc.postpad) {
  2242. pos = steps * (eccsize + chunk);
  2243. steps = 0;
  2244. } else
  2245. pos = eccsize;
  2246. ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
  2247. if (ret)
  2248. return ret;
  2249. for (i = 0; i < steps; i++) {
  2250. if (sndcmd) {
  2251. if (mtd->writesize <= 512) {
  2252. uint32_t fill = 0xFFFFFFFF;
  2253. len = eccsize;
  2254. while (len > 0) {
  2255. int num = min_t(int, len, 4);
  2256. ret = nand_write_data_op(chip, &fill,
  2257. num, false);
  2258. if (ret)
  2259. return ret;
  2260. len -= num;
  2261. }
  2262. } else {
  2263. pos = eccsize + i * (eccsize + chunk);
  2264. ret = nand_change_write_column_op(chip, pos,
  2265. NULL, 0,
  2266. false);
  2267. if (ret)
  2268. return ret;
  2269. }
  2270. } else
  2271. sndcmd = 1;
  2272. len = min_t(int, length, chunk);
  2273. ret = nand_write_data_op(chip, bufpoi, len, false);
  2274. if (ret)
  2275. return ret;
  2276. bufpoi += len;
  2277. length -= len;
  2278. }
  2279. if (length > 0) {
  2280. ret = nand_write_data_op(chip, bufpoi, length, false);
  2281. if (ret)
  2282. return ret;
  2283. }
  2284. return nand_prog_page_end_op(chip);
  2285. }
  2286. /**
  2287. * nand_do_read_oob - [INTERN] NAND read out-of-band
  2288. * @mtd: MTD device structure
  2289. * @from: offset to read from
  2290. * @ops: oob operations description structure
  2291. *
  2292. * NAND read out-of-band data from the spare area.
  2293. */
  2294. static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
  2295. struct mtd_oob_ops *ops)
  2296. {
  2297. int page, realpage, chipnr;
  2298. struct nand_chip *chip = mtd_to_nand(mtd);
  2299. struct mtd_ecc_stats stats;
  2300. int readlen = ops->ooblen;
  2301. int len;
  2302. uint8_t *buf = ops->oobbuf;
  2303. int ret = 0;
  2304. pr_debug("%s: from = 0x%08Lx, len = %i\n",
  2305. __func__, (unsigned long long)from, readlen);
  2306. stats = mtd->ecc_stats;
  2307. len = mtd_oobavail(mtd, ops);
  2308. if (unlikely(ops->ooboffs >= len)) {
  2309. pr_debug("%s: attempt to start read outside oob\n",
  2310. __func__);
  2311. return -EINVAL;
  2312. }
  2313. /* Do not allow reads past end of device */
  2314. if (unlikely(from >= mtd->size ||
  2315. ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
  2316. (from >> chip->page_shift)) * len)) {
  2317. pr_debug("%s: attempt to read beyond end of device\n",
  2318. __func__);
  2319. return -EINVAL;
  2320. }
  2321. chipnr = (int)(from >> chip->chip_shift);
  2322. chip->select_chip(mtd, chipnr);
  2323. /* Shift to get page */
  2324. realpage = (int)(from >> chip->page_shift);
  2325. page = realpage & chip->pagemask;
  2326. while (1) {
  2327. WATCHDOG_RESET();
  2328. if (ops->mode == MTD_OPS_RAW)
  2329. ret = chip->ecc.read_oob_raw(mtd, chip, page);
  2330. else
  2331. ret = chip->ecc.read_oob(mtd, chip, page);
  2332. if (ret < 0)
  2333. break;
  2334. len = min(len, readlen);
  2335. buf = nand_transfer_oob(chip, buf, ops, len);
  2336. if (chip->options & NAND_NEED_READRDY) {
  2337. /* Apply delay or wait for ready/busy pin */
  2338. if (!chip->dev_ready)
  2339. udelay(chip->chip_delay);
  2340. else
  2341. nand_wait_ready(mtd);
  2342. }
  2343. readlen -= len;
  2344. if (!readlen)
  2345. break;
  2346. /* Increment page address */
  2347. realpage++;
  2348. page = realpage & chip->pagemask;
  2349. /* Check, if we cross a chip boundary */
  2350. if (!page) {
  2351. chipnr++;
  2352. chip->select_chip(mtd, -1);
  2353. chip->select_chip(mtd, chipnr);
  2354. }
  2355. }
  2356. chip->select_chip(mtd, -1);
  2357. ops->oobretlen = ops->ooblen - readlen;
  2358. if (ret < 0)
  2359. return ret;
  2360. if (mtd->ecc_stats.failed - stats.failed)
  2361. return -EBADMSG;
  2362. return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
  2363. }
  2364. /**
  2365. * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
  2366. * @mtd: MTD device structure
  2367. * @from: offset to read from
  2368. * @ops: oob operation description structure
  2369. *
  2370. * NAND read data and/or out-of-band data.
  2371. */
  2372. static int nand_read_oob(struct mtd_info *mtd, loff_t from,
  2373. struct mtd_oob_ops *ops)
  2374. {
  2375. int ret = -ENOTSUPP;
  2376. ops->retlen = 0;
  2377. /* Do not allow reads past end of device */
  2378. if (ops->datbuf && (from + ops->len) > mtd->size) {
  2379. pr_debug("%s: attempt to read beyond end of device\n",
  2380. __func__);
  2381. return -EINVAL;
  2382. }
  2383. nand_get_device(mtd, FL_READING);
  2384. switch (ops->mode) {
  2385. case MTD_OPS_PLACE_OOB:
  2386. case MTD_OPS_AUTO_OOB:
  2387. case MTD_OPS_RAW:
  2388. break;
  2389. default:
  2390. goto out;
  2391. }
  2392. if (!ops->datbuf)
  2393. ret = nand_do_read_oob(mtd, from, ops);
  2394. else
  2395. ret = nand_do_read_ops(mtd, from, ops);
  2396. out:
  2397. nand_release_device(mtd);
  2398. return ret;
  2399. }
  2400. /**
  2401. * nand_write_page_raw - [INTERN] raw page write function
  2402. * @mtd: mtd info structure
  2403. * @chip: nand chip info structure
  2404. * @buf: data buffer
  2405. * @oob_required: must write chip->oob_poi to OOB
  2406. * @page: page number to write
  2407. *
  2408. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  2409. */
  2410. static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  2411. const uint8_t *buf, int oob_required, int page)
  2412. {
  2413. int ret;
  2414. ret = nand_write_data_op(chip, buf, mtd->writesize, false);
  2415. if (ret)
  2416. return ret;
  2417. if (oob_required) {
  2418. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
  2419. false);
  2420. if (ret)
  2421. return ret;
  2422. }
  2423. return 0;
  2424. }
  2425. /**
  2426. * nand_write_page_raw_syndrome - [INTERN] raw page write function
  2427. * @mtd: mtd info structure
  2428. * @chip: nand chip info structure
  2429. * @buf: data buffer
  2430. * @oob_required: must write chip->oob_poi to OOB
  2431. * @page: page number to write
  2432. *
  2433. * We need a special oob layout and handling even when ECC isn't checked.
  2434. */
  2435. static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
  2436. struct nand_chip *chip,
  2437. const uint8_t *buf, int oob_required,
  2438. int page)
  2439. {
  2440. int eccsize = chip->ecc.size;
  2441. int eccbytes = chip->ecc.bytes;
  2442. uint8_t *oob = chip->oob_poi;
  2443. int steps, size, ret;
  2444. for (steps = chip->ecc.steps; steps > 0; steps--) {
  2445. ret = nand_write_data_op(chip, buf, eccsize, false);
  2446. if (ret)
  2447. return ret;
  2448. buf += eccsize;
  2449. if (chip->ecc.prepad) {
  2450. ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
  2451. false);
  2452. if (ret)
  2453. return ret;
  2454. oob += chip->ecc.prepad;
  2455. }
  2456. ret = nand_write_data_op(chip, oob, eccbytes, false);
  2457. if (ret)
  2458. return ret;
  2459. oob += eccbytes;
  2460. if (chip->ecc.postpad) {
  2461. ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
  2462. false);
  2463. if (ret)
  2464. return ret;
  2465. oob += chip->ecc.postpad;
  2466. }
  2467. }
  2468. size = mtd->oobsize - (oob - chip->oob_poi);
  2469. if (size) {
  2470. ret = nand_write_data_op(chip, oob, size, false);
  2471. if (ret)
  2472. return ret;
  2473. }
  2474. return 0;
  2475. }
  2476. /**
  2477. * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
  2478. * @mtd: mtd info structure
  2479. * @chip: nand chip info structure
  2480. * @buf: data buffer
  2481. * @oob_required: must write chip->oob_poi to OOB
  2482. * @page: page number to write
  2483. */
  2484. static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  2485. const uint8_t *buf, int oob_required,
  2486. int page)
  2487. {
  2488. int i, eccsize = chip->ecc.size;
  2489. int eccbytes = chip->ecc.bytes;
  2490. int eccsteps = chip->ecc.steps;
  2491. uint8_t *ecc_calc = chip->buffers->ecccalc;
  2492. const uint8_t *p = buf;
  2493. uint32_t *eccpos = chip->ecc.layout->eccpos;
  2494. /* Software ECC calculation */
  2495. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  2496. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  2497. for (i = 0; i < chip->ecc.total; i++)
  2498. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  2499. return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
  2500. }
  2501. /**
  2502. * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
  2503. * @mtd: mtd info structure
  2504. * @chip: nand chip info structure
  2505. * @buf: data buffer
  2506. * @oob_required: must write chip->oob_poi to OOB
  2507. * @page: page number to write
  2508. */
  2509. static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  2510. const uint8_t *buf, int oob_required,
  2511. int page)
  2512. {
  2513. int i, eccsize = chip->ecc.size;
  2514. int eccbytes = chip->ecc.bytes;
  2515. int eccsteps = chip->ecc.steps;
  2516. uint8_t *ecc_calc = chip->buffers->ecccalc;
  2517. const uint8_t *p = buf;
  2518. uint32_t *eccpos = chip->ecc.layout->eccpos;
  2519. int ret;
  2520. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2521. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  2522. ret = nand_write_data_op(chip, p, eccsize, false);
  2523. if (ret)
  2524. return ret;
  2525. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  2526. }
  2527. for (i = 0; i < chip->ecc.total; i++)
  2528. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  2529. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  2530. if (ret)
  2531. return ret;
  2532. return 0;
  2533. }
  2534. /**
  2535. * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
  2536. * @mtd: mtd info structure
  2537. * @chip: nand chip info structure
  2538. * @offset: column address of subpage within the page
  2539. * @data_len: data length
  2540. * @buf: data buffer
  2541. * @oob_required: must write chip->oob_poi to OOB
  2542. * @page: page number to write
  2543. */
  2544. static int nand_write_subpage_hwecc(struct mtd_info *mtd,
  2545. struct nand_chip *chip, uint32_t offset,
  2546. uint32_t data_len, const uint8_t *buf,
  2547. int oob_required, int page)
  2548. {
  2549. uint8_t *oob_buf = chip->oob_poi;
  2550. uint8_t *ecc_calc = chip->buffers->ecccalc;
  2551. int ecc_size = chip->ecc.size;
  2552. int ecc_bytes = chip->ecc.bytes;
  2553. int ecc_steps = chip->ecc.steps;
  2554. uint32_t *eccpos = chip->ecc.layout->eccpos;
  2555. uint32_t start_step = offset / ecc_size;
  2556. uint32_t end_step = (offset + data_len - 1) / ecc_size;
  2557. int oob_bytes = mtd->oobsize / ecc_steps;
  2558. int step, i;
  2559. int ret;
  2560. for (step = 0; step < ecc_steps; step++) {
  2561. /* configure controller for WRITE access */
  2562. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  2563. /* write data (untouched subpages already masked by 0xFF) */
  2564. ret = nand_write_data_op(chip, buf, ecc_size, false);
  2565. if (ret)
  2566. return ret;
  2567. /* mask ECC of un-touched subpages by padding 0xFF */
  2568. if ((step < start_step) || (step > end_step))
  2569. memset(ecc_calc, 0xff, ecc_bytes);
  2570. else
  2571. chip->ecc.calculate(mtd, buf, ecc_calc);
  2572. /* mask OOB of un-touched subpages by padding 0xFF */
  2573. /* if oob_required, preserve OOB metadata of written subpage */
  2574. if (!oob_required || (step < start_step) || (step > end_step))
  2575. memset(oob_buf, 0xff, oob_bytes);
  2576. buf += ecc_size;
  2577. ecc_calc += ecc_bytes;
  2578. oob_buf += oob_bytes;
  2579. }
  2580. /* copy calculated ECC for whole page to chip->buffer->oob */
  2581. /* this include masked-value(0xFF) for unwritten subpages */
  2582. ecc_calc = chip->buffers->ecccalc;
  2583. for (i = 0; i < chip->ecc.total; i++)
  2584. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  2585. /* write OOB buffer to NAND device */
  2586. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  2587. if (ret)
  2588. return ret;
  2589. return 0;
  2590. }
  2591. /**
  2592. * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
  2593. * @mtd: mtd info structure
  2594. * @chip: nand chip info structure
  2595. * @buf: data buffer
  2596. * @oob_required: must write chip->oob_poi to OOB
  2597. * @page: page number to write
  2598. *
  2599. * The hw generator calculates the error syndrome automatically. Therefore we
  2600. * need a special oob layout and handling.
  2601. */
  2602. static int nand_write_page_syndrome(struct mtd_info *mtd,
  2603. struct nand_chip *chip,
  2604. const uint8_t *buf, int oob_required,
  2605. int page)
  2606. {
  2607. int i, eccsize = chip->ecc.size;
  2608. int eccbytes = chip->ecc.bytes;
  2609. int eccsteps = chip->ecc.steps;
  2610. const uint8_t *p = buf;
  2611. uint8_t *oob = chip->oob_poi;
  2612. int ret;
  2613. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2614. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  2615. ret = nand_write_data_op(chip, p, eccsize, false);
  2616. if (ret)
  2617. return ret;
  2618. if (chip->ecc.prepad) {
  2619. ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
  2620. false);
  2621. if (ret)
  2622. return ret;
  2623. oob += chip->ecc.prepad;
  2624. }
  2625. chip->ecc.calculate(mtd, p, oob);
  2626. ret = nand_write_data_op(chip, oob, eccbytes, false);
  2627. if (ret)
  2628. return ret;
  2629. oob += eccbytes;
  2630. if (chip->ecc.postpad) {
  2631. ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
  2632. false);
  2633. if (ret)
  2634. return ret;
  2635. oob += chip->ecc.postpad;
  2636. }
  2637. }
  2638. /* Calculate remaining oob bytes */
  2639. i = mtd->oobsize - (oob - chip->oob_poi);
  2640. if (i) {
  2641. ret = nand_write_data_op(chip, oob, i, false);
  2642. if (ret)
  2643. return ret;
  2644. }
  2645. return 0;
  2646. }
  2647. /**
  2648. * nand_write_page - [REPLACEABLE] write one page
  2649. * @mtd: MTD device structure
  2650. * @chip: NAND chip descriptor
  2651. * @offset: address offset within the page
  2652. * @data_len: length of actual data to be written
  2653. * @buf: the data to write
  2654. * @oob_required: must write chip->oob_poi to OOB
  2655. * @page: page number to write
  2656. * @raw: use _raw version of write_page
  2657. */
  2658. static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  2659. uint32_t offset, int data_len, const uint8_t *buf,
  2660. int oob_required, int page, int raw)
  2661. {
  2662. int status, subpage;
  2663. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
  2664. chip->ecc.write_subpage)
  2665. subpage = offset || (data_len < mtd->writesize);
  2666. else
  2667. subpage = 0;
  2668. if (nand_standard_page_accessors(&chip->ecc)) {
  2669. status = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
  2670. if (status)
  2671. return status;
  2672. }
  2673. if (unlikely(raw))
  2674. status = chip->ecc.write_page_raw(mtd, chip, buf,
  2675. oob_required, page);
  2676. else if (subpage)
  2677. status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
  2678. buf, oob_required, page);
  2679. else
  2680. status = chip->ecc.write_page(mtd, chip, buf, oob_required,
  2681. page);
  2682. if (status < 0)
  2683. return status;
  2684. if (nand_standard_page_accessors(&chip->ecc))
  2685. return nand_prog_page_end_op(chip);
  2686. return 0;
  2687. }
  2688. /**
  2689. * nand_fill_oob - [INTERN] Transfer client buffer to oob
  2690. * @mtd: MTD device structure
  2691. * @oob: oob data buffer
  2692. * @len: oob data write length
  2693. * @ops: oob ops structure
  2694. */
  2695. static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
  2696. struct mtd_oob_ops *ops)
  2697. {
  2698. struct nand_chip *chip = mtd_to_nand(mtd);
  2699. /*
  2700. * Initialise to all 0xFF, to avoid the possibility of left over OOB
  2701. * data from a previous OOB read.
  2702. */
  2703. memset(chip->oob_poi, 0xff, mtd->oobsize);
  2704. switch (ops->mode) {
  2705. case MTD_OPS_PLACE_OOB:
  2706. case MTD_OPS_RAW:
  2707. memcpy(chip->oob_poi + ops->ooboffs, oob, len);
  2708. return oob + len;
  2709. case MTD_OPS_AUTO_OOB: {
  2710. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  2711. uint32_t boffs = 0, woffs = ops->ooboffs;
  2712. size_t bytes = 0;
  2713. for (; free->length && len; free++, len -= bytes) {
  2714. /* Write request not from offset 0? */
  2715. if (unlikely(woffs)) {
  2716. if (woffs >= free->length) {
  2717. woffs -= free->length;
  2718. continue;
  2719. }
  2720. boffs = free->offset + woffs;
  2721. bytes = min_t(size_t, len,
  2722. (free->length - woffs));
  2723. woffs = 0;
  2724. } else {
  2725. bytes = min_t(size_t, len, free->length);
  2726. boffs = free->offset;
  2727. }
  2728. memcpy(chip->oob_poi + boffs, oob, bytes);
  2729. oob += bytes;
  2730. }
  2731. return oob;
  2732. }
  2733. default:
  2734. BUG();
  2735. }
  2736. return NULL;
  2737. }
  2738. #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
  2739. /**
  2740. * nand_do_write_ops - [INTERN] NAND write with ECC
  2741. * @mtd: MTD device structure
  2742. * @to: offset to write to
  2743. * @ops: oob operations description structure
  2744. *
  2745. * NAND write with ECC.
  2746. */
  2747. static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
  2748. struct mtd_oob_ops *ops)
  2749. {
  2750. int chipnr, realpage, page, column;
  2751. struct nand_chip *chip = mtd_to_nand(mtd);
  2752. uint32_t writelen = ops->len;
  2753. uint32_t oobwritelen = ops->ooblen;
  2754. uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
  2755. uint8_t *oob = ops->oobbuf;
  2756. uint8_t *buf = ops->datbuf;
  2757. int ret;
  2758. int oob_required = oob ? 1 : 0;
  2759. ops->retlen = 0;
  2760. if (!writelen)
  2761. return 0;
  2762. /* Reject writes, which are not page aligned */
  2763. if (NOTALIGNED(to)) {
  2764. pr_notice("%s: attempt to write non page aligned data\n",
  2765. __func__);
  2766. return -EINVAL;
  2767. }
  2768. column = to & (mtd->writesize - 1);
  2769. chipnr = (int)(to >> chip->chip_shift);
  2770. chip->select_chip(mtd, chipnr);
  2771. /* Check, if it is write protected */
  2772. if (nand_check_wp(mtd)) {
  2773. ret = -EIO;
  2774. goto err_out;
  2775. }
  2776. realpage = (int)(to >> chip->page_shift);
  2777. page = realpage & chip->pagemask;
  2778. /* Invalidate the page cache, when we write to the cached page */
  2779. if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
  2780. ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
  2781. chip->pagebuf = -1;
  2782. /* Don't allow multipage oob writes with offset */
  2783. if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
  2784. ret = -EINVAL;
  2785. goto err_out;
  2786. }
  2787. while (1) {
  2788. int bytes = mtd->writesize;
  2789. uint8_t *wbuf = buf;
  2790. int use_bufpoi;
  2791. int part_pagewr = (column || writelen < mtd->writesize);
  2792. if (part_pagewr)
  2793. use_bufpoi = 1;
  2794. else if (chip->options & NAND_USE_BOUNCE_BUFFER)
  2795. use_bufpoi = !IS_ALIGNED((unsigned long)buf,
  2796. chip->buf_align);
  2797. else
  2798. use_bufpoi = 0;
  2799. WATCHDOG_RESET();
  2800. /* Partial page write?, or need to use bounce buffer */
  2801. if (use_bufpoi) {
  2802. pr_debug("%s: using write bounce buffer for buf@%p\n",
  2803. __func__, buf);
  2804. if (part_pagewr)
  2805. bytes = min_t(int, bytes - column, writelen);
  2806. chip->pagebuf = -1;
  2807. memset(chip->buffers->databuf, 0xff, mtd->writesize);
  2808. memcpy(&chip->buffers->databuf[column], buf, bytes);
  2809. wbuf = chip->buffers->databuf;
  2810. }
  2811. if (unlikely(oob)) {
  2812. size_t len = min(oobwritelen, oobmaxlen);
  2813. oob = nand_fill_oob(mtd, oob, len, ops);
  2814. oobwritelen -= len;
  2815. } else {
  2816. /* We still need to erase leftover OOB data */
  2817. memset(chip->oob_poi, 0xff, mtd->oobsize);
  2818. }
  2819. ret = chip->write_page(mtd, chip, column, bytes, wbuf,
  2820. oob_required, page,
  2821. (ops->mode == MTD_OPS_RAW));
  2822. if (ret)
  2823. break;
  2824. writelen -= bytes;
  2825. if (!writelen)
  2826. break;
  2827. column = 0;
  2828. buf += bytes;
  2829. realpage++;
  2830. page = realpage & chip->pagemask;
  2831. /* Check, if we cross a chip boundary */
  2832. if (!page) {
  2833. chipnr++;
  2834. chip->select_chip(mtd, -1);
  2835. chip->select_chip(mtd, chipnr);
  2836. }
  2837. }
  2838. ops->retlen = ops->len - writelen;
  2839. if (unlikely(oob))
  2840. ops->oobretlen = ops->ooblen;
  2841. err_out:
  2842. chip->select_chip(mtd, -1);
  2843. return ret;
  2844. }
  2845. /**
  2846. * panic_nand_write - [MTD Interface] NAND write with ECC
  2847. * @mtd: MTD device structure
  2848. * @to: offset to write to
  2849. * @len: number of bytes to write
  2850. * @retlen: pointer to variable to store the number of written bytes
  2851. * @buf: the data to write
  2852. *
  2853. * NAND write with ECC. Used when performing writes in interrupt context, this
  2854. * may for example be called by mtdoops when writing an oops while in panic.
  2855. */
  2856. static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
  2857. size_t *retlen, const uint8_t *buf)
  2858. {
  2859. struct nand_chip *chip = mtd_to_nand(mtd);
  2860. struct mtd_oob_ops ops;
  2861. int ret;
  2862. /* Wait for the device to get ready */
  2863. panic_nand_wait(mtd, chip, 400);
  2864. /* Grab the device */
  2865. panic_nand_get_device(chip, mtd, FL_WRITING);
  2866. memset(&ops, 0, sizeof(ops));
  2867. ops.len = len;
  2868. ops.datbuf = (uint8_t *)buf;
  2869. ops.mode = MTD_OPS_PLACE_OOB;
  2870. ret = nand_do_write_ops(mtd, to, &ops);
  2871. *retlen = ops.retlen;
  2872. return ret;
  2873. }
  2874. /**
  2875. * nand_do_write_oob - [MTD Interface] NAND write out-of-band
  2876. * @mtd: MTD device structure
  2877. * @to: offset to write to
  2878. * @ops: oob operation description structure
  2879. *
  2880. * NAND write out-of-band.
  2881. */
  2882. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  2883. struct mtd_oob_ops *ops)
  2884. {
  2885. int chipnr, page, status, len;
  2886. struct nand_chip *chip = mtd_to_nand(mtd);
  2887. pr_debug("%s: to = 0x%08x, len = %i\n",
  2888. __func__, (unsigned int)to, (int)ops->ooblen);
  2889. len = mtd_oobavail(mtd, ops);
  2890. /* Do not allow write past end of page */
  2891. if ((ops->ooboffs + ops->ooblen) > len) {
  2892. pr_debug("%s: attempt to write past end of page\n",
  2893. __func__);
  2894. return -EINVAL;
  2895. }
  2896. if (unlikely(ops->ooboffs >= len)) {
  2897. pr_debug("%s: attempt to start write outside oob\n",
  2898. __func__);
  2899. return -EINVAL;
  2900. }
  2901. /* Do not allow write past end of device */
  2902. if (unlikely(to >= mtd->size ||
  2903. ops->ooboffs + ops->ooblen >
  2904. ((mtd->size >> chip->page_shift) -
  2905. (to >> chip->page_shift)) * len)) {
  2906. pr_debug("%s: attempt to write beyond end of device\n",
  2907. __func__);
  2908. return -EINVAL;
  2909. }
  2910. chipnr = (int)(to >> chip->chip_shift);
  2911. /*
  2912. * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
  2913. * of my DiskOnChip 2000 test units) will clear the whole data page too
  2914. * if we don't do this. I have no clue why, but I seem to have 'fixed'
  2915. * it in the doc2000 driver in August 1999. dwmw2.
  2916. */
  2917. nand_reset(chip, chipnr);
  2918. chip->select_chip(mtd, chipnr);
  2919. /* Shift to get page */
  2920. page = (int)(to >> chip->page_shift);
  2921. /* Check, if it is write protected */
  2922. if (nand_check_wp(mtd)) {
  2923. chip->select_chip(mtd, -1);
  2924. return -EROFS;
  2925. }
  2926. /* Invalidate the page cache, if we write to the cached page */
  2927. if (page == chip->pagebuf)
  2928. chip->pagebuf = -1;
  2929. nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
  2930. if (ops->mode == MTD_OPS_RAW)
  2931. status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
  2932. else
  2933. status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
  2934. chip->select_chip(mtd, -1);
  2935. if (status)
  2936. return status;
  2937. ops->oobretlen = ops->ooblen;
  2938. return 0;
  2939. }
  2940. /**
  2941. * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
  2942. * @mtd: MTD device structure
  2943. * @to: offset to write to
  2944. * @ops: oob operation description structure
  2945. */
  2946. static int nand_write_oob(struct mtd_info *mtd, loff_t to,
  2947. struct mtd_oob_ops *ops)
  2948. {
  2949. int ret = -ENOTSUPP;
  2950. ops->retlen = 0;
  2951. /* Do not allow writes past end of device */
  2952. if (ops->datbuf && (to + ops->len) > mtd->size) {
  2953. pr_debug("%s: attempt to write beyond end of device\n",
  2954. __func__);
  2955. return -EINVAL;
  2956. }
  2957. nand_get_device(mtd, FL_WRITING);
  2958. switch (ops->mode) {
  2959. case MTD_OPS_PLACE_OOB:
  2960. case MTD_OPS_AUTO_OOB:
  2961. case MTD_OPS_RAW:
  2962. break;
  2963. default:
  2964. goto out;
  2965. }
  2966. if (!ops->datbuf)
  2967. ret = nand_do_write_oob(mtd, to, ops);
  2968. else
  2969. ret = nand_do_write_ops(mtd, to, ops);
  2970. out:
  2971. nand_release_device(mtd);
  2972. return ret;
  2973. }
  2974. /**
  2975. * single_erase - [GENERIC] NAND standard block erase command function
  2976. * @mtd: MTD device structure
  2977. * @page: the page address of the block which will be erased
  2978. *
  2979. * Standard erase command for NAND chips. Returns NAND status.
  2980. */
  2981. static int single_erase(struct mtd_info *mtd, int page)
  2982. {
  2983. struct nand_chip *chip = mtd_to_nand(mtd);
  2984. unsigned int eraseblock;
  2985. /* Send commands to erase a block */
  2986. eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
  2987. return nand_erase_op(chip, eraseblock);
  2988. }
  2989. /**
  2990. * nand_erase - [MTD Interface] erase block(s)
  2991. * @mtd: MTD device structure
  2992. * @instr: erase instruction
  2993. *
  2994. * Erase one ore more blocks.
  2995. */
  2996. static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
  2997. {
  2998. return nand_erase_nand(mtd, instr, 0);
  2999. }
  3000. /**
  3001. * nand_erase_nand - [INTERN] erase block(s)
  3002. * @mtd: MTD device structure
  3003. * @instr: erase instruction
  3004. * @allowbbt: allow erasing the bbt area
  3005. *
  3006. * Erase one ore more blocks.
  3007. */
  3008. int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  3009. int allowbbt)
  3010. {
  3011. int page, status, pages_per_block, ret, chipnr;
  3012. struct nand_chip *chip = mtd_to_nand(mtd);
  3013. loff_t len;
  3014. pr_debug("%s: start = 0x%012llx, len = %llu\n",
  3015. __func__, (unsigned long long)instr->addr,
  3016. (unsigned long long)instr->len);
  3017. if (check_offs_len(mtd, instr->addr, instr->len))
  3018. return -EINVAL;
  3019. /* Grab the lock and see if the device is available */
  3020. nand_get_device(mtd, FL_ERASING);
  3021. /* Shift to get first page */
  3022. page = (int)(instr->addr >> chip->page_shift);
  3023. chipnr = (int)(instr->addr >> chip->chip_shift);
  3024. /* Calculate pages in each block */
  3025. pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
  3026. /* Select the NAND device */
  3027. chip->select_chip(mtd, chipnr);
  3028. /* Check, if it is write protected */
  3029. if (nand_check_wp(mtd)) {
  3030. pr_debug("%s: device is write protected!\n",
  3031. __func__);
  3032. instr->state = MTD_ERASE_FAILED;
  3033. goto erase_exit;
  3034. }
  3035. /* Loop through the pages */
  3036. len = instr->len;
  3037. instr->state = MTD_ERASING;
  3038. while (len) {
  3039. WATCHDOG_RESET();
  3040. /* Check if we have a bad block, we do not erase bad blocks! */
  3041. if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
  3042. chip->page_shift, allowbbt)) {
  3043. pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
  3044. __func__, page);
  3045. instr->state = MTD_ERASE_FAILED;
  3046. instr->fail_addr =
  3047. ((loff_t)page << chip->page_shift);
  3048. goto erase_exit;
  3049. }
  3050. /*
  3051. * Invalidate the page cache, if we erase the block which
  3052. * contains the current cached page.
  3053. */
  3054. if (page <= chip->pagebuf && chip->pagebuf <
  3055. (page + pages_per_block))
  3056. chip->pagebuf = -1;
  3057. status = chip->erase(mtd, page & chip->pagemask);
  3058. /* See if block erase succeeded */
  3059. if (status & NAND_STATUS_FAIL) {
  3060. pr_debug("%s: failed erase, page 0x%08x\n",
  3061. __func__, page);
  3062. instr->state = MTD_ERASE_FAILED;
  3063. instr->fail_addr =
  3064. ((loff_t)page << chip->page_shift);
  3065. goto erase_exit;
  3066. }
  3067. /* Increment page address and decrement length */
  3068. len -= (1ULL << chip->phys_erase_shift);
  3069. page += pages_per_block;
  3070. /* Check, if we cross a chip boundary */
  3071. if (len && !(page & chip->pagemask)) {
  3072. chipnr++;
  3073. chip->select_chip(mtd, -1);
  3074. chip->select_chip(mtd, chipnr);
  3075. }
  3076. }
  3077. instr->state = MTD_ERASE_DONE;
  3078. erase_exit:
  3079. ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
  3080. /* Deselect and wake up anyone waiting on the device */
  3081. chip->select_chip(mtd, -1);
  3082. nand_release_device(mtd);
  3083. /* Do call back function */
  3084. if (!ret)
  3085. mtd_erase_callback(instr);
  3086. /* Return more or less happy */
  3087. return ret;
  3088. }
  3089. /**
  3090. * nand_sync - [MTD Interface] sync
  3091. * @mtd: MTD device structure
  3092. *
  3093. * Sync is actually a wait for chip ready function.
  3094. */
  3095. static void nand_sync(struct mtd_info *mtd)
  3096. {
  3097. pr_debug("%s: called\n", __func__);
  3098. /* Grab the lock and see if the device is available */
  3099. nand_get_device(mtd, FL_SYNCING);
  3100. /* Release it and go back */
  3101. nand_release_device(mtd);
  3102. }
  3103. /**
  3104. * nand_block_isbad - [MTD Interface] Check if block at offset is bad
  3105. * @mtd: MTD device structure
  3106. * @offs: offset relative to mtd start
  3107. */
  3108. static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
  3109. {
  3110. struct nand_chip *chip = mtd_to_nand(mtd);
  3111. int chipnr = (int)(offs >> chip->chip_shift);
  3112. int ret;
  3113. /* Select the NAND device */
  3114. nand_get_device(mtd, FL_READING);
  3115. chip->select_chip(mtd, chipnr);
  3116. ret = nand_block_checkbad(mtd, offs, 0);
  3117. chip->select_chip(mtd, -1);
  3118. nand_release_device(mtd);
  3119. return ret;
  3120. }
  3121. /**
  3122. * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
  3123. * @mtd: MTD device structure
  3124. * @ofs: offset relative to mtd start
  3125. */
  3126. static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
  3127. {
  3128. int ret;
  3129. ret = nand_block_isbad(mtd, ofs);
  3130. if (ret) {
  3131. /* If it was bad already, return success and do nothing */
  3132. if (ret > 0)
  3133. return 0;
  3134. return ret;
  3135. }
  3136. return nand_block_markbad_lowlevel(mtd, ofs);
  3137. }
  3138. /**
  3139. * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
  3140. * @mtd: MTD device structure
  3141. * @chip: nand chip info structure
  3142. * @addr: feature address.
  3143. * @subfeature_param: the subfeature parameters, a four bytes array.
  3144. */
  3145. static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
  3146. int addr, uint8_t *subfeature_param)
  3147. {
  3148. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3149. if (!chip->onfi_version ||
  3150. !(le16_to_cpu(chip->onfi_params.opt_cmd)
  3151. & ONFI_OPT_CMD_SET_GET_FEATURES))
  3152. return -ENOTSUPP;
  3153. #endif
  3154. return nand_set_features_op(chip, addr, subfeature_param);
  3155. }
  3156. /**
  3157. * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
  3158. * @mtd: MTD device structure
  3159. * @chip: nand chip info structure
  3160. * @addr: feature address.
  3161. * @subfeature_param: the subfeature parameters, a four bytes array.
  3162. */
  3163. static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
  3164. int addr, uint8_t *subfeature_param)
  3165. {
  3166. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3167. if (!chip->onfi_version ||
  3168. !(le16_to_cpu(chip->onfi_params.opt_cmd)
  3169. & ONFI_OPT_CMD_SET_GET_FEATURES))
  3170. return -ENOTSUPP;
  3171. #endif
  3172. return nand_get_features_op(chip, addr, subfeature_param);
  3173. }
  3174. /* Set default functions */
  3175. static void nand_set_defaults(struct nand_chip *chip, int busw)
  3176. {
  3177. /* check for proper chip_delay setup, set 20us if not */
  3178. if (!chip->chip_delay)
  3179. chip->chip_delay = 20;
  3180. /* check, if a user supplied command function given */
  3181. if (chip->cmdfunc == NULL)
  3182. chip->cmdfunc = nand_command;
  3183. /* check, if a user supplied wait function given */
  3184. if (chip->waitfunc == NULL)
  3185. chip->waitfunc = nand_wait;
  3186. if (!chip->select_chip)
  3187. chip->select_chip = nand_select_chip;
  3188. /* set for ONFI nand */
  3189. if (!chip->onfi_set_features)
  3190. chip->onfi_set_features = nand_onfi_set_features;
  3191. if (!chip->onfi_get_features)
  3192. chip->onfi_get_features = nand_onfi_get_features;
  3193. /* If called twice, pointers that depend on busw may need to be reset */
  3194. if (!chip->read_byte || chip->read_byte == nand_read_byte)
  3195. chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
  3196. if (!chip->read_word)
  3197. chip->read_word = nand_read_word;
  3198. if (!chip->block_bad)
  3199. chip->block_bad = nand_block_bad;
  3200. if (!chip->block_markbad)
  3201. chip->block_markbad = nand_default_block_markbad;
  3202. if (!chip->write_buf || chip->write_buf == nand_write_buf)
  3203. chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
  3204. if (!chip->write_byte || chip->write_byte == nand_write_byte)
  3205. chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
  3206. if (!chip->read_buf || chip->read_buf == nand_read_buf)
  3207. chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
  3208. if (!chip->scan_bbt)
  3209. chip->scan_bbt = nand_default_bbt;
  3210. if (!chip->controller) {
  3211. chip->controller = &chip->hwcontrol;
  3212. spin_lock_init(&chip->controller->lock);
  3213. init_waitqueue_head(&chip->controller->wq);
  3214. }
  3215. if (!chip->buf_align)
  3216. chip->buf_align = 1;
  3217. }
  3218. /* Sanitize ONFI strings so we can safely print them */
  3219. static void sanitize_string(char *s, size_t len)
  3220. {
  3221. ssize_t i;
  3222. /* Null terminate */
  3223. s[len - 1] = 0;
  3224. /* Remove non printable chars */
  3225. for (i = 0; i < len - 1; i++) {
  3226. if (s[i] < ' ' || s[i] > 127)
  3227. s[i] = '?';
  3228. }
  3229. /* Remove trailing spaces */
  3230. strim(s);
  3231. }
  3232. static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
  3233. {
  3234. int i;
  3235. while (len--) {
  3236. crc ^= *p++ << 8;
  3237. for (i = 0; i < 8; i++)
  3238. crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
  3239. }
  3240. return crc;
  3241. }
  3242. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3243. /* Parse the Extended Parameter Page. */
  3244. static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
  3245. struct nand_chip *chip, struct nand_onfi_params *p)
  3246. {
  3247. struct onfi_ext_param_page *ep;
  3248. struct onfi_ext_section *s;
  3249. struct onfi_ext_ecc_info *ecc;
  3250. uint8_t *cursor;
  3251. int ret;
  3252. int len;
  3253. int i;
  3254. len = le16_to_cpu(p->ext_param_page_length) * 16;
  3255. ep = kmalloc(len, GFP_KERNEL);
  3256. if (!ep)
  3257. return -ENOMEM;
  3258. /* Send our own NAND_CMD_PARAM. */
  3259. ret = nand_read_param_page_op(chip, 0, NULL, 0);
  3260. if (ret)
  3261. goto ext_out;
  3262. /* Use the Change Read Column command to skip the ONFI param pages. */
  3263. ret = nand_change_read_column_op(chip,
  3264. sizeof(*p) * p->num_of_param_pages,
  3265. ep, len, true);
  3266. if (ret)
  3267. goto ext_out;
  3268. ret = -EINVAL;
  3269. if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
  3270. != le16_to_cpu(ep->crc))) {
  3271. pr_debug("fail in the CRC.\n");
  3272. goto ext_out;
  3273. }
  3274. /*
  3275. * Check the signature.
  3276. * Do not strictly follow the ONFI spec, maybe changed in future.
  3277. */
  3278. if (strncmp((char *)ep->sig, "EPPS", 4)) {
  3279. pr_debug("The signature is invalid.\n");
  3280. goto ext_out;
  3281. }
  3282. /* find the ECC section. */
  3283. cursor = (uint8_t *)(ep + 1);
  3284. for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
  3285. s = ep->sections + i;
  3286. if (s->type == ONFI_SECTION_TYPE_2)
  3287. break;
  3288. cursor += s->length * 16;
  3289. }
  3290. if (i == ONFI_EXT_SECTION_MAX) {
  3291. pr_debug("We can not find the ECC section.\n");
  3292. goto ext_out;
  3293. }
  3294. /* get the info we want. */
  3295. ecc = (struct onfi_ext_ecc_info *)cursor;
  3296. if (!ecc->codeword_size) {
  3297. pr_debug("Invalid codeword size\n");
  3298. goto ext_out;
  3299. }
  3300. chip->ecc_strength_ds = ecc->ecc_bits;
  3301. chip->ecc_step_ds = 1 << ecc->codeword_size;
  3302. ret = 0;
  3303. ext_out:
  3304. kfree(ep);
  3305. return ret;
  3306. }
  3307. static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
  3308. {
  3309. struct nand_chip *chip = mtd_to_nand(mtd);
  3310. uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
  3311. return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
  3312. feature);
  3313. }
  3314. /*
  3315. * Configure chip properties from Micron vendor-specific ONFI table
  3316. */
  3317. static void nand_onfi_detect_micron(struct nand_chip *chip,
  3318. struct nand_onfi_params *p)
  3319. {
  3320. struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
  3321. if (le16_to_cpu(p->vendor_revision) < 1)
  3322. return;
  3323. chip->read_retries = micron->read_retry_options;
  3324. chip->setup_read_retry = nand_setup_read_retry_micron;
  3325. }
  3326. /*
  3327. * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
  3328. */
  3329. static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
  3330. int *busw)
  3331. {
  3332. struct nand_onfi_params *p = &chip->onfi_params;
  3333. char id[4];
  3334. int i, ret, val;
  3335. /* Try ONFI for unknown chip or LP */
  3336. ret = nand_readid_op(chip, 0x20, id, sizeof(id));
  3337. if (ret || strncmp(id, "ONFI", 4))
  3338. return 0;
  3339. ret = nand_read_param_page_op(chip, 0, NULL, 0);
  3340. if (ret)
  3341. return 0;
  3342. for (i = 0; i < 3; i++) {
  3343. ret = nand_read_data_op(chip, p, sizeof(*p), true);
  3344. if (ret)
  3345. return 0;
  3346. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
  3347. le16_to_cpu(p->crc)) {
  3348. break;
  3349. }
  3350. }
  3351. if (i == 3) {
  3352. pr_err("Could not find valid ONFI parameter page; aborting\n");
  3353. return 0;
  3354. }
  3355. /* Check version */
  3356. val = le16_to_cpu(p->revision);
  3357. if (val & (1 << 5))
  3358. chip->onfi_version = 23;
  3359. else if (val & (1 << 4))
  3360. chip->onfi_version = 22;
  3361. else if (val & (1 << 3))
  3362. chip->onfi_version = 21;
  3363. else if (val & (1 << 2))
  3364. chip->onfi_version = 20;
  3365. else if (val & (1 << 1))
  3366. chip->onfi_version = 10;
  3367. if (!chip->onfi_version) {
  3368. pr_info("unsupported ONFI version: %d\n", val);
  3369. return 0;
  3370. }
  3371. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  3372. sanitize_string(p->model, sizeof(p->model));
  3373. if (!mtd->name)
  3374. mtd->name = p->model;
  3375. mtd->writesize = le32_to_cpu(p->byte_per_page);
  3376. /*
  3377. * pages_per_block and blocks_per_lun may not be a power-of-2 size
  3378. * (don't ask me who thought of this...). MTD assumes that these
  3379. * dimensions will be power-of-2, so just truncate the remaining area.
  3380. */
  3381. mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  3382. mtd->erasesize *= mtd->writesize;
  3383. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  3384. /* See erasesize comment */
  3385. chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  3386. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  3387. chip->bits_per_cell = p->bits_per_cell;
  3388. if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
  3389. *busw = NAND_BUSWIDTH_16;
  3390. else
  3391. *busw = 0;
  3392. if (p->ecc_bits != 0xff) {
  3393. chip->ecc_strength_ds = p->ecc_bits;
  3394. chip->ecc_step_ds = 512;
  3395. } else if (chip->onfi_version >= 21 &&
  3396. (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
  3397. /*
  3398. * The nand_flash_detect_ext_param_page() uses the
  3399. * Change Read Column command which maybe not supported
  3400. * by the chip->cmdfunc. So try to update the chip->cmdfunc
  3401. * now. We do not replace user supplied command function.
  3402. */
  3403. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  3404. chip->cmdfunc = nand_command_lp;
  3405. /* The Extended Parameter Page is supported since ONFI 2.1. */
  3406. if (nand_flash_detect_ext_param_page(mtd, chip, p))
  3407. pr_warn("Failed to detect ONFI extended param page\n");
  3408. } else {
  3409. pr_warn("Could not retrieve ONFI ECC requirements\n");
  3410. }
  3411. if (p->jedec_id == NAND_MFR_MICRON)
  3412. nand_onfi_detect_micron(chip, p);
  3413. return 1;
  3414. }
  3415. #else
  3416. static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
  3417. int *busw)
  3418. {
  3419. return 0;
  3420. }
  3421. #endif
  3422. /*
  3423. * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
  3424. */
  3425. static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
  3426. int *busw)
  3427. {
  3428. struct nand_jedec_params *p = &chip->jedec_params;
  3429. struct jedec_ecc_info *ecc;
  3430. char id[5];
  3431. int i, val, ret;
  3432. /* Try JEDEC for unknown chip or LP */
  3433. ret = nand_readid_op(chip, 0x40, id, sizeof(id));
  3434. if (ret || strncmp(id, "JEDEC", sizeof(id)))
  3435. return 0;
  3436. ret = nand_read_param_page_op(chip, 0x40, NULL, 0);
  3437. if (ret)
  3438. return 0;
  3439. for (i = 0; i < 3; i++) {
  3440. ret = nand_read_data_op(chip, p, sizeof(*p), true);
  3441. if (ret)
  3442. return 0;
  3443. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
  3444. le16_to_cpu(p->crc))
  3445. break;
  3446. }
  3447. if (i == 3) {
  3448. pr_err("Could not find valid JEDEC parameter page; aborting\n");
  3449. return 0;
  3450. }
  3451. /* Check version */
  3452. val = le16_to_cpu(p->revision);
  3453. if (val & (1 << 2))
  3454. chip->jedec_version = 10;
  3455. else if (val & (1 << 1))
  3456. chip->jedec_version = 1; /* vendor specific version */
  3457. if (!chip->jedec_version) {
  3458. pr_info("unsupported JEDEC version: %d\n", val);
  3459. return 0;
  3460. }
  3461. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  3462. sanitize_string(p->model, sizeof(p->model));
  3463. if (!mtd->name)
  3464. mtd->name = p->model;
  3465. mtd->writesize = le32_to_cpu(p->byte_per_page);
  3466. /* Please reference to the comment for nand_flash_detect_onfi. */
  3467. mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  3468. mtd->erasesize *= mtd->writesize;
  3469. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  3470. /* Please reference to the comment for nand_flash_detect_onfi. */
  3471. chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  3472. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  3473. chip->bits_per_cell = p->bits_per_cell;
  3474. if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
  3475. *busw = NAND_BUSWIDTH_16;
  3476. else
  3477. *busw = 0;
  3478. /* ECC info */
  3479. ecc = &p->ecc_info[0];
  3480. if (ecc->codeword_size >= 9) {
  3481. chip->ecc_strength_ds = ecc->ecc_bits;
  3482. chip->ecc_step_ds = 1 << ecc->codeword_size;
  3483. } else {
  3484. pr_warn("Invalid codeword size\n");
  3485. }
  3486. return 1;
  3487. }
  3488. /*
  3489. * nand_id_has_period - Check if an ID string has a given wraparound period
  3490. * @id_data: the ID string
  3491. * @arrlen: the length of the @id_data array
  3492. * @period: the period of repitition
  3493. *
  3494. * Check if an ID string is repeated within a given sequence of bytes at
  3495. * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
  3496. * period of 3). This is a helper function for nand_id_len(). Returns non-zero
  3497. * if the repetition has a period of @period; otherwise, returns zero.
  3498. */
  3499. static int nand_id_has_period(u8 *id_data, int arrlen, int period)
  3500. {
  3501. int i, j;
  3502. for (i = 0; i < period; i++)
  3503. for (j = i + period; j < arrlen; j += period)
  3504. if (id_data[i] != id_data[j])
  3505. return 0;
  3506. return 1;
  3507. }
  3508. /*
  3509. * nand_id_len - Get the length of an ID string returned by CMD_READID
  3510. * @id_data: the ID string
  3511. * @arrlen: the length of the @id_data array
  3512. * Returns the length of the ID string, according to known wraparound/trailing
  3513. * zero patterns. If no pattern exists, returns the length of the array.
  3514. */
  3515. static int nand_id_len(u8 *id_data, int arrlen)
  3516. {
  3517. int last_nonzero, period;
  3518. /* Find last non-zero byte */
  3519. for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
  3520. if (id_data[last_nonzero])
  3521. break;
  3522. /* All zeros */
  3523. if (last_nonzero < 0)
  3524. return 0;
  3525. /* Calculate wraparound period */
  3526. for (period = 1; period < arrlen; period++)
  3527. if (nand_id_has_period(id_data, arrlen, period))
  3528. break;
  3529. /* There's a repeated pattern */
  3530. if (period < arrlen)
  3531. return period;
  3532. /* There are trailing zeros */
  3533. if (last_nonzero < arrlen - 1)
  3534. return last_nonzero + 1;
  3535. /* No pattern detected */
  3536. return arrlen;
  3537. }
  3538. /* Extract the bits of per cell from the 3rd byte of the extended ID */
  3539. static int nand_get_bits_per_cell(u8 cellinfo)
  3540. {
  3541. int bits;
  3542. bits = cellinfo & NAND_CI_CELLTYPE_MSK;
  3543. bits >>= NAND_CI_CELLTYPE_SHIFT;
  3544. return bits + 1;
  3545. }
  3546. /*
  3547. * Many new NAND share similar device ID codes, which represent the size of the
  3548. * chip. The rest of the parameters must be decoded according to generic or
  3549. * manufacturer-specific "extended ID" decoding patterns.
  3550. */
  3551. static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
  3552. u8 id_data[8], int *busw)
  3553. {
  3554. int extid, id_len;
  3555. /* The 3rd id byte holds MLC / multichip data */
  3556. chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
  3557. /* The 4th id byte is the important one */
  3558. extid = id_data[3];
  3559. id_len = nand_id_len(id_data, 8);
  3560. /*
  3561. * Field definitions are in the following datasheets:
  3562. * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
  3563. * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
  3564. * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
  3565. *
  3566. * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
  3567. * ID to decide what to do.
  3568. */
  3569. if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
  3570. !nand_is_slc(chip) && id_data[5] != 0x00) {
  3571. /* Calc pagesize */
  3572. mtd->writesize = 2048 << (extid & 0x03);
  3573. extid >>= 2;
  3574. /* Calc oobsize */
  3575. switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
  3576. case 1:
  3577. mtd->oobsize = 128;
  3578. break;
  3579. case 2:
  3580. mtd->oobsize = 218;
  3581. break;
  3582. case 3:
  3583. mtd->oobsize = 400;
  3584. break;
  3585. case 4:
  3586. mtd->oobsize = 436;
  3587. break;
  3588. case 5:
  3589. mtd->oobsize = 512;
  3590. break;
  3591. case 6:
  3592. mtd->oobsize = 640;
  3593. break;
  3594. case 7:
  3595. default: /* Other cases are "reserved" (unknown) */
  3596. mtd->oobsize = 1024;
  3597. break;
  3598. }
  3599. extid >>= 2;
  3600. /* Calc blocksize */
  3601. mtd->erasesize = (128 * 1024) <<
  3602. (((extid >> 1) & 0x04) | (extid & 0x03));
  3603. *busw = 0;
  3604. } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
  3605. !nand_is_slc(chip)) {
  3606. unsigned int tmp;
  3607. /* Calc pagesize */
  3608. mtd->writesize = 2048 << (extid & 0x03);
  3609. extid >>= 2;
  3610. /* Calc oobsize */
  3611. switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
  3612. case 0:
  3613. mtd->oobsize = 128;
  3614. break;
  3615. case 1:
  3616. mtd->oobsize = 224;
  3617. break;
  3618. case 2:
  3619. mtd->oobsize = 448;
  3620. break;
  3621. case 3:
  3622. mtd->oobsize = 64;
  3623. break;
  3624. case 4:
  3625. mtd->oobsize = 32;
  3626. break;
  3627. case 5:
  3628. mtd->oobsize = 16;
  3629. break;
  3630. default:
  3631. mtd->oobsize = 640;
  3632. break;
  3633. }
  3634. extid >>= 2;
  3635. /* Calc blocksize */
  3636. tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
  3637. if (tmp < 0x03)
  3638. mtd->erasesize = (128 * 1024) << tmp;
  3639. else if (tmp == 0x03)
  3640. mtd->erasesize = 768 * 1024;
  3641. else
  3642. mtd->erasesize = (64 * 1024) << tmp;
  3643. *busw = 0;
  3644. } else {
  3645. /* Calc pagesize */
  3646. mtd->writesize = 1024 << (extid & 0x03);
  3647. extid >>= 2;
  3648. /* Calc oobsize */
  3649. mtd->oobsize = (8 << (extid & 0x01)) *
  3650. (mtd->writesize >> 9);
  3651. extid >>= 2;
  3652. /* Calc blocksize. Blocksize is multiples of 64KiB */
  3653. mtd->erasesize = (64 * 1024) << (extid & 0x03);
  3654. extid >>= 2;
  3655. /* Get buswidth information */
  3656. *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
  3657. /*
  3658. * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
  3659. * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
  3660. * follows:
  3661. * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
  3662. * 110b -> 24nm
  3663. * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
  3664. */
  3665. if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
  3666. nand_is_slc(chip) &&
  3667. (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
  3668. !(id_data[4] & 0x80) /* !BENAND */) {
  3669. mtd->oobsize = 32 * mtd->writesize >> 9;
  3670. }
  3671. }
  3672. }
  3673. /*
  3674. * Old devices have chip data hardcoded in the device ID table. nand_decode_id
  3675. * decodes a matching ID table entry and assigns the MTD size parameters for
  3676. * the chip.
  3677. */
  3678. static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
  3679. struct nand_flash_dev *type, u8 id_data[8],
  3680. int *busw)
  3681. {
  3682. int maf_id = id_data[0];
  3683. mtd->erasesize = type->erasesize;
  3684. mtd->writesize = type->pagesize;
  3685. mtd->oobsize = mtd->writesize / 32;
  3686. *busw = type->options & NAND_BUSWIDTH_16;
  3687. /* All legacy ID NAND are small-page, SLC */
  3688. chip->bits_per_cell = 1;
  3689. /*
  3690. * Check for Spansion/AMD ID + repeating 5th, 6th byte since
  3691. * some Spansion chips have erasesize that conflicts with size
  3692. * listed in nand_ids table.
  3693. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
  3694. */
  3695. if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
  3696. && id_data[6] == 0x00 && id_data[7] == 0x00
  3697. && mtd->writesize == 512) {
  3698. mtd->erasesize = 128 * 1024;
  3699. mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
  3700. }
  3701. }
  3702. /*
  3703. * Set the bad block marker/indicator (BBM/BBI) patterns according to some
  3704. * heuristic patterns using various detected parameters (e.g., manufacturer,
  3705. * page size, cell-type information).
  3706. */
  3707. static void nand_decode_bbm_options(struct mtd_info *mtd,
  3708. struct nand_chip *chip, u8 id_data[8])
  3709. {
  3710. int maf_id = id_data[0];
  3711. /* Set the bad block position */
  3712. if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
  3713. chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
  3714. else
  3715. chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
  3716. /*
  3717. * Bad block marker is stored in the last page of each block on Samsung
  3718. * and Hynix MLC devices; stored in first two pages of each block on
  3719. * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
  3720. * AMD/Spansion, and Macronix. All others scan only the first page.
  3721. */
  3722. if (!nand_is_slc(chip) &&
  3723. (maf_id == NAND_MFR_SAMSUNG ||
  3724. maf_id == NAND_MFR_HYNIX))
  3725. chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
  3726. else if ((nand_is_slc(chip) &&
  3727. (maf_id == NAND_MFR_SAMSUNG ||
  3728. maf_id == NAND_MFR_HYNIX ||
  3729. maf_id == NAND_MFR_TOSHIBA ||
  3730. maf_id == NAND_MFR_AMD ||
  3731. maf_id == NAND_MFR_MACRONIX)) ||
  3732. (mtd->writesize == 2048 &&
  3733. maf_id == NAND_MFR_MICRON))
  3734. chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
  3735. }
  3736. static inline bool is_full_id_nand(struct nand_flash_dev *type)
  3737. {
  3738. return type->id_len;
  3739. }
  3740. static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
  3741. struct nand_flash_dev *type, u8 *id_data, int *busw)
  3742. {
  3743. if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
  3744. mtd->writesize = type->pagesize;
  3745. mtd->erasesize = type->erasesize;
  3746. mtd->oobsize = type->oobsize;
  3747. chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
  3748. chip->chipsize = (uint64_t)type->chipsize << 20;
  3749. chip->options |= type->options;
  3750. chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
  3751. chip->ecc_step_ds = NAND_ECC_STEP(type);
  3752. chip->onfi_timing_mode_default =
  3753. type->onfi_timing_mode_default;
  3754. *busw = type->options & NAND_BUSWIDTH_16;
  3755. if (!mtd->name)
  3756. mtd->name = type->name;
  3757. return true;
  3758. }
  3759. return false;
  3760. }
  3761. /*
  3762. * Get the flash and manufacturer id and lookup if the type is supported.
  3763. */
  3764. struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
  3765. struct nand_chip *chip,
  3766. int *maf_id, int *dev_id,
  3767. struct nand_flash_dev *type)
  3768. {
  3769. int busw, ret;
  3770. int maf_idx;
  3771. u8 id_data[8];
  3772. /*
  3773. * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
  3774. * after power-up.
  3775. */
  3776. ret = nand_reset(chip, 0);
  3777. if (ret)
  3778. return ERR_PTR(ret);
  3779. /* Select the device */
  3780. chip->select_chip(mtd, 0);
  3781. /* Send the command for reading device ID */
  3782. ret = nand_readid_op(chip, 0, id_data, 2);
  3783. if (ret)
  3784. return ERR_PTR(ret);
  3785. /* Read manufacturer and device IDs */
  3786. *maf_id = id_data[0];
  3787. *dev_id = id_data[1];
  3788. /*
  3789. * Try again to make sure, as some systems the bus-hold or other
  3790. * interface concerns can cause random data which looks like a
  3791. * possibly credible NAND flash to appear. If the two results do
  3792. * not match, ignore the device completely.
  3793. */
  3794. /* Read entire ID string */
  3795. ret = nand_readid_op(chip, 0, id_data, 8);
  3796. if (ret)
  3797. return ERR_PTR(ret);
  3798. if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
  3799. pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
  3800. *maf_id, *dev_id, id_data[0], id_data[1]);
  3801. return ERR_PTR(-ENODEV);
  3802. }
  3803. if (!type)
  3804. type = nand_flash_ids;
  3805. for (; type->name != NULL; type++) {
  3806. if (is_full_id_nand(type)) {
  3807. if (find_full_id_nand(mtd, chip, type, id_data, &busw))
  3808. goto ident_done;
  3809. } else if (*dev_id == type->dev_id) {
  3810. break;
  3811. }
  3812. }
  3813. chip->onfi_version = 0;
  3814. if (!type->name || !type->pagesize) {
  3815. /* Check if the chip is ONFI compliant */
  3816. if (nand_flash_detect_onfi(mtd, chip, &busw))
  3817. goto ident_done;
  3818. /* Check if the chip is JEDEC compliant */
  3819. if (nand_flash_detect_jedec(mtd, chip, &busw))
  3820. goto ident_done;
  3821. }
  3822. if (!type->name)
  3823. return ERR_PTR(-ENODEV);
  3824. if (!mtd->name)
  3825. mtd->name = type->name;
  3826. chip->chipsize = (uint64_t)type->chipsize << 20;
  3827. if (!type->pagesize) {
  3828. /* Decode parameters from extended ID */
  3829. nand_decode_ext_id(mtd, chip, id_data, &busw);
  3830. } else {
  3831. nand_decode_id(mtd, chip, type, id_data, &busw);
  3832. }
  3833. /* Get chip options */
  3834. chip->options |= type->options;
  3835. /*
  3836. * Check if chip is not a Samsung device. Do not clear the
  3837. * options for chips which do not have an extended id.
  3838. */
  3839. if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
  3840. chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
  3841. ident_done:
  3842. /* Try to identify manufacturer */
  3843. for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
  3844. if (nand_manuf_ids[maf_idx].id == *maf_id)
  3845. break;
  3846. }
  3847. if (chip->options & NAND_BUSWIDTH_AUTO) {
  3848. WARN_ON(chip->options & NAND_BUSWIDTH_16);
  3849. chip->options |= busw;
  3850. nand_set_defaults(chip, busw);
  3851. } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
  3852. /*
  3853. * Check, if buswidth is correct. Hardware drivers should set
  3854. * chip correct!
  3855. */
  3856. pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
  3857. *maf_id, *dev_id);
  3858. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
  3859. pr_warn("bus width %d instead %d bit\n",
  3860. (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
  3861. busw ? 16 : 8);
  3862. return ERR_PTR(-EINVAL);
  3863. }
  3864. nand_decode_bbm_options(mtd, chip, id_data);
  3865. /* Calculate the address shift from the page size */
  3866. chip->page_shift = ffs(mtd->writesize) - 1;
  3867. /* Convert chipsize to number of pages per chip -1 */
  3868. chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
  3869. chip->bbt_erase_shift = chip->phys_erase_shift =
  3870. ffs(mtd->erasesize) - 1;
  3871. if (chip->chipsize & 0xffffffff)
  3872. chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
  3873. else {
  3874. chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
  3875. chip->chip_shift += 32 - 1;
  3876. }
  3877. if (chip->chip_shift - chip->page_shift > 16)
  3878. chip->options |= NAND_ROW_ADDR_3;
  3879. chip->badblockbits = 8;
  3880. chip->erase = single_erase;
  3881. /* Do not replace user supplied command function! */
  3882. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  3883. chip->cmdfunc = nand_command_lp;
  3884. pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
  3885. *maf_id, *dev_id);
  3886. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3887. if (chip->onfi_version)
  3888. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3889. chip->onfi_params.model);
  3890. else if (chip->jedec_version)
  3891. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3892. chip->jedec_params.model);
  3893. else
  3894. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3895. type->name);
  3896. #else
  3897. if (chip->jedec_version)
  3898. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3899. chip->jedec_params.model);
  3900. else
  3901. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3902. type->name);
  3903. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3904. type->name);
  3905. #endif
  3906. pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
  3907. (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
  3908. mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
  3909. return type;
  3910. }
  3911. EXPORT_SYMBOL(nand_get_flash_type);
  3912. #if CONFIG_IS_ENABLED(OF_CONTROL)
  3913. static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
  3914. {
  3915. int ret, ecc_mode = -1, ecc_strength, ecc_step;
  3916. const char *str;
  3917. ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
  3918. if (ret == 16)
  3919. chip->options |= NAND_BUSWIDTH_16;
  3920. if (ofnode_read_bool(node, "nand-on-flash-bbt"))
  3921. chip->bbt_options |= NAND_BBT_USE_FLASH;
  3922. str = ofnode_read_string(node, "nand-ecc-mode");
  3923. if (str) {
  3924. if (!strcmp(str, "none"))
  3925. ecc_mode = NAND_ECC_NONE;
  3926. else if (!strcmp(str, "soft"))
  3927. ecc_mode = NAND_ECC_SOFT;
  3928. else if (!strcmp(str, "hw"))
  3929. ecc_mode = NAND_ECC_HW;
  3930. else if (!strcmp(str, "hw_syndrome"))
  3931. ecc_mode = NAND_ECC_HW_SYNDROME;
  3932. else if (!strcmp(str, "hw_oob_first"))
  3933. ecc_mode = NAND_ECC_HW_OOB_FIRST;
  3934. else if (!strcmp(str, "soft_bch"))
  3935. ecc_mode = NAND_ECC_SOFT_BCH;
  3936. }
  3937. ecc_strength = ofnode_read_s32_default(node,
  3938. "nand-ecc-strength", -1);
  3939. ecc_step = ofnode_read_s32_default(node,
  3940. "nand-ecc-step-size", -1);
  3941. if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
  3942. (!(ecc_step >= 0) && ecc_strength >= 0)) {
  3943. pr_err("must set both strength and step size in DT\n");
  3944. return -EINVAL;
  3945. }
  3946. if (ecc_mode >= 0)
  3947. chip->ecc.mode = ecc_mode;
  3948. if (ecc_strength >= 0)
  3949. chip->ecc.strength = ecc_strength;
  3950. if (ecc_step > 0)
  3951. chip->ecc.size = ecc_step;
  3952. if (ofnode_read_bool(node, "nand-ecc-maximize"))
  3953. chip->ecc.options |= NAND_ECC_MAXIMIZE;
  3954. return 0;
  3955. }
  3956. #else
  3957. static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
  3958. {
  3959. return 0;
  3960. }
  3961. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  3962. /**
  3963. * nand_scan_ident - [NAND Interface] Scan for the NAND device
  3964. * @mtd: MTD device structure
  3965. * @maxchips: number of chips to scan for
  3966. * @table: alternative NAND ID table
  3967. *
  3968. * This is the first phase of the normal nand_scan() function. It reads the
  3969. * flash ID and sets up MTD fields accordingly.
  3970. *
  3971. */
  3972. int nand_scan_ident(struct mtd_info *mtd, int maxchips,
  3973. struct nand_flash_dev *table)
  3974. {
  3975. int i, nand_maf_id, nand_dev_id;
  3976. struct nand_chip *chip = mtd_to_nand(mtd);
  3977. struct nand_flash_dev *type;
  3978. int ret;
  3979. if (ofnode_valid(chip->flash_node)) {
  3980. ret = nand_dt_init(mtd, chip, chip->flash_node);
  3981. if (ret)
  3982. return ret;
  3983. }
  3984. /* Set the default functions */
  3985. nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
  3986. /* Read the flash type */
  3987. type = nand_get_flash_type(mtd, chip, &nand_maf_id,
  3988. &nand_dev_id, table);
  3989. if (IS_ERR(type)) {
  3990. if (!(chip->options & NAND_SCAN_SILENT_NODEV))
  3991. pr_warn("No NAND device found\n");
  3992. chip->select_chip(mtd, -1);
  3993. return PTR_ERR(type);
  3994. }
  3995. /* Initialize the ->data_interface field. */
  3996. ret = nand_init_data_interface(chip);
  3997. if (ret)
  3998. return ret;
  3999. /*
  4000. * Setup the data interface correctly on the chip and controller side.
  4001. * This explicit call to nand_setup_data_interface() is only required
  4002. * for the first die, because nand_reset() has been called before
  4003. * ->data_interface and ->default_onfi_timing_mode were set.
  4004. * For the other dies, nand_reset() will automatically switch to the
  4005. * best mode for us.
  4006. */
  4007. ret = nand_setup_data_interface(chip, 0);
  4008. if (ret)
  4009. return ret;
  4010. chip->select_chip(mtd, -1);
  4011. /* Check for a chip array */
  4012. for (i = 1; i < maxchips; i++) {
  4013. u8 id[2];
  4014. /* See comment in nand_get_flash_type for reset */
  4015. nand_reset(chip, i);
  4016. chip->select_chip(mtd, i);
  4017. /* Send the command for reading device ID */
  4018. nand_readid_op(chip, 0, id, sizeof(id));
  4019. /* Read manufacturer and device IDs */
  4020. if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
  4021. chip->select_chip(mtd, -1);
  4022. break;
  4023. }
  4024. chip->select_chip(mtd, -1);
  4025. }
  4026. #ifdef DEBUG
  4027. if (i > 1)
  4028. pr_info("%d chips detected\n", i);
  4029. #endif
  4030. /* Store the number of chips and calc total size for mtd */
  4031. chip->numchips = i;
  4032. mtd->size = i * chip->chipsize;
  4033. return 0;
  4034. }
  4035. EXPORT_SYMBOL(nand_scan_ident);
  4036. /**
  4037. * nand_check_ecc_caps - check the sanity of preset ECC settings
  4038. * @chip: nand chip info structure
  4039. * @caps: ECC caps info structure
  4040. * @oobavail: OOB size that the ECC engine can use
  4041. *
  4042. * When ECC step size and strength are already set, check if they are supported
  4043. * by the controller and the calculated ECC bytes fit within the chip's OOB.
  4044. * On success, the calculated ECC bytes is set.
  4045. */
  4046. int nand_check_ecc_caps(struct nand_chip *chip,
  4047. const struct nand_ecc_caps *caps, int oobavail)
  4048. {
  4049. struct mtd_info *mtd = nand_to_mtd(chip);
  4050. const struct nand_ecc_step_info *stepinfo;
  4051. int preset_step = chip->ecc.size;
  4052. int preset_strength = chip->ecc.strength;
  4053. int nsteps, ecc_bytes;
  4054. int i, j;
  4055. if (WARN_ON(oobavail < 0))
  4056. return -EINVAL;
  4057. if (!preset_step || !preset_strength)
  4058. return -ENODATA;
  4059. nsteps = mtd->writesize / preset_step;
  4060. for (i = 0; i < caps->nstepinfos; i++) {
  4061. stepinfo = &caps->stepinfos[i];
  4062. if (stepinfo->stepsize != preset_step)
  4063. continue;
  4064. for (j = 0; j < stepinfo->nstrengths; j++) {
  4065. if (stepinfo->strengths[j] != preset_strength)
  4066. continue;
  4067. ecc_bytes = caps->calc_ecc_bytes(preset_step,
  4068. preset_strength);
  4069. if (WARN_ON_ONCE(ecc_bytes < 0))
  4070. return ecc_bytes;
  4071. if (ecc_bytes * nsteps > oobavail) {
  4072. pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
  4073. preset_step, preset_strength);
  4074. return -ENOSPC;
  4075. }
  4076. chip->ecc.bytes = ecc_bytes;
  4077. return 0;
  4078. }
  4079. }
  4080. pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
  4081. preset_step, preset_strength);
  4082. return -ENOTSUPP;
  4083. }
  4084. EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
  4085. /**
  4086. * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
  4087. * @chip: nand chip info structure
  4088. * @caps: ECC engine caps info structure
  4089. * @oobavail: OOB size that the ECC engine can use
  4090. *
  4091. * If a chip's ECC requirement is provided, try to meet it with the least
  4092. * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
  4093. * On success, the chosen ECC settings are set.
  4094. */
  4095. int nand_match_ecc_req(struct nand_chip *chip,
  4096. const struct nand_ecc_caps *caps, int oobavail)
  4097. {
  4098. struct mtd_info *mtd = nand_to_mtd(chip);
  4099. const struct nand_ecc_step_info *stepinfo;
  4100. int req_step = chip->ecc_step_ds;
  4101. int req_strength = chip->ecc_strength_ds;
  4102. int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
  4103. int best_step, best_strength, best_ecc_bytes;
  4104. int best_ecc_bytes_total = INT_MAX;
  4105. int i, j;
  4106. if (WARN_ON(oobavail < 0))
  4107. return -EINVAL;
  4108. /* No information provided by the NAND chip */
  4109. if (!req_step || !req_strength)
  4110. return -ENOTSUPP;
  4111. /* number of correctable bits the chip requires in a page */
  4112. req_corr = mtd->writesize / req_step * req_strength;
  4113. for (i = 0; i < caps->nstepinfos; i++) {
  4114. stepinfo = &caps->stepinfos[i];
  4115. step_size = stepinfo->stepsize;
  4116. for (j = 0; j < stepinfo->nstrengths; j++) {
  4117. strength = stepinfo->strengths[j];
  4118. /*
  4119. * If both step size and strength are smaller than the
  4120. * chip's requirement, it is not easy to compare the
  4121. * resulted reliability.
  4122. */
  4123. if (step_size < req_step && strength < req_strength)
  4124. continue;
  4125. if (mtd->writesize % step_size)
  4126. continue;
  4127. nsteps = mtd->writesize / step_size;
  4128. ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
  4129. if (WARN_ON_ONCE(ecc_bytes < 0))
  4130. continue;
  4131. ecc_bytes_total = ecc_bytes * nsteps;
  4132. if (ecc_bytes_total > oobavail ||
  4133. strength * nsteps < req_corr)
  4134. continue;
  4135. /*
  4136. * We assume the best is to meet the chip's requrement
  4137. * with the least number of ECC bytes.
  4138. */
  4139. if (ecc_bytes_total < best_ecc_bytes_total) {
  4140. best_ecc_bytes_total = ecc_bytes_total;
  4141. best_step = step_size;
  4142. best_strength = strength;
  4143. best_ecc_bytes = ecc_bytes;
  4144. }
  4145. }
  4146. }
  4147. if (best_ecc_bytes_total == INT_MAX)
  4148. return -ENOTSUPP;
  4149. chip->ecc.size = best_step;
  4150. chip->ecc.strength = best_strength;
  4151. chip->ecc.bytes = best_ecc_bytes;
  4152. return 0;
  4153. }
  4154. EXPORT_SYMBOL_GPL(nand_match_ecc_req);
  4155. /**
  4156. * nand_maximize_ecc - choose the max ECC strength available
  4157. * @chip: nand chip info structure
  4158. * @caps: ECC engine caps info structure
  4159. * @oobavail: OOB size that the ECC engine can use
  4160. *
  4161. * Choose the max ECC strength that is supported on the controller, and can fit
  4162. * within the chip's OOB. On success, the chosen ECC settings are set.
  4163. */
  4164. int nand_maximize_ecc(struct nand_chip *chip,
  4165. const struct nand_ecc_caps *caps, int oobavail)
  4166. {
  4167. struct mtd_info *mtd = nand_to_mtd(chip);
  4168. const struct nand_ecc_step_info *stepinfo;
  4169. int step_size, strength, nsteps, ecc_bytes, corr;
  4170. int best_corr = 0;
  4171. int best_step = 0;
  4172. int best_strength, best_ecc_bytes;
  4173. int i, j;
  4174. if (WARN_ON(oobavail < 0))
  4175. return -EINVAL;
  4176. for (i = 0; i < caps->nstepinfos; i++) {
  4177. stepinfo = &caps->stepinfos[i];
  4178. step_size = stepinfo->stepsize;
  4179. /* If chip->ecc.size is already set, respect it */
  4180. if (chip->ecc.size && step_size != chip->ecc.size)
  4181. continue;
  4182. for (j = 0; j < stepinfo->nstrengths; j++) {
  4183. strength = stepinfo->strengths[j];
  4184. if (mtd->writesize % step_size)
  4185. continue;
  4186. nsteps = mtd->writesize / step_size;
  4187. ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
  4188. if (WARN_ON_ONCE(ecc_bytes < 0))
  4189. continue;
  4190. if (ecc_bytes * nsteps > oobavail)
  4191. continue;
  4192. corr = strength * nsteps;
  4193. /*
  4194. * If the number of correctable bits is the same,
  4195. * bigger step_size has more reliability.
  4196. */
  4197. if (corr > best_corr ||
  4198. (corr == best_corr && step_size > best_step)) {
  4199. best_corr = corr;
  4200. best_step = step_size;
  4201. best_strength = strength;
  4202. best_ecc_bytes = ecc_bytes;
  4203. }
  4204. }
  4205. }
  4206. if (!best_corr)
  4207. return -ENOTSUPP;
  4208. chip->ecc.size = best_step;
  4209. chip->ecc.strength = best_strength;
  4210. chip->ecc.bytes = best_ecc_bytes;
  4211. return 0;
  4212. }
  4213. EXPORT_SYMBOL_GPL(nand_maximize_ecc);
  4214. /*
  4215. * Check if the chip configuration meet the datasheet requirements.
  4216. * If our configuration corrects A bits per B bytes and the minimum
  4217. * required correction level is X bits per Y bytes, then we must ensure
  4218. * both of the following are true:
  4219. *
  4220. * (1) A / B >= X / Y
  4221. * (2) A >= X
  4222. *
  4223. * Requirement (1) ensures we can correct for the required bitflip density.
  4224. * Requirement (2) ensures we can correct even when all bitflips are clumped
  4225. * in the same sector.
  4226. */
  4227. static bool nand_ecc_strength_good(struct mtd_info *mtd)
  4228. {
  4229. struct nand_chip *chip = mtd_to_nand(mtd);
  4230. struct nand_ecc_ctrl *ecc = &chip->ecc;
  4231. int corr, ds_corr;
  4232. if (ecc->size == 0 || chip->ecc_step_ds == 0)
  4233. /* Not enough information */
  4234. return true;
  4235. /*
  4236. * We get the number of corrected bits per page to compare
  4237. * the correction density.
  4238. */
  4239. corr = (mtd->writesize * ecc->strength) / ecc->size;
  4240. ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
  4241. return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
  4242. }
  4243. static bool invalid_ecc_page_accessors(struct nand_chip *chip)
  4244. {
  4245. struct nand_ecc_ctrl *ecc = &chip->ecc;
  4246. if (nand_standard_page_accessors(ecc))
  4247. return false;
  4248. /*
  4249. * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
  4250. * controller driver implements all the page accessors because
  4251. * default helpers are not suitable when the core does not
  4252. * send the READ0/PAGEPROG commands.
  4253. */
  4254. return (!ecc->read_page || !ecc->write_page ||
  4255. !ecc->read_page_raw || !ecc->write_page_raw ||
  4256. (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
  4257. (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
  4258. ecc->hwctl && ecc->calculate));
  4259. }
  4260. /**
  4261. * nand_scan_tail - [NAND Interface] Scan for the NAND device
  4262. * @mtd: MTD device structure
  4263. *
  4264. * This is the second phase of the normal nand_scan() function. It fills out
  4265. * all the uninitialized function pointers with the defaults and scans for a
  4266. * bad block table if appropriate.
  4267. */
  4268. int nand_scan_tail(struct mtd_info *mtd)
  4269. {
  4270. int i;
  4271. struct nand_chip *chip = mtd_to_nand(mtd);
  4272. struct nand_ecc_ctrl *ecc = &chip->ecc;
  4273. struct nand_buffers *nbuf;
  4274. /* New bad blocks should be marked in OOB, flash-based BBT, or both */
  4275. BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
  4276. !(chip->bbt_options & NAND_BBT_USE_FLASH));
  4277. if (invalid_ecc_page_accessors(chip)) {
  4278. pr_err("Invalid ECC page accessors setup\n");
  4279. return -EINVAL;
  4280. }
  4281. if (!(chip->options & NAND_OWN_BUFFERS)) {
  4282. nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
  4283. chip->buffers = nbuf;
  4284. } else {
  4285. if (!chip->buffers)
  4286. return -ENOMEM;
  4287. }
  4288. /* Set the internal oob buffer location, just after the page data */
  4289. chip->oob_poi = chip->buffers->databuf + mtd->writesize;
  4290. /*
  4291. * If no default placement scheme is given, select an appropriate one.
  4292. */
  4293. if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
  4294. switch (mtd->oobsize) {
  4295. #ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
  4296. case 8:
  4297. ecc->layout = &nand_oob_8;
  4298. break;
  4299. case 16:
  4300. ecc->layout = &nand_oob_16;
  4301. break;
  4302. case 64:
  4303. ecc->layout = &nand_oob_64;
  4304. break;
  4305. case 128:
  4306. ecc->layout = &nand_oob_128;
  4307. break;
  4308. #endif
  4309. default:
  4310. pr_warn("No oob scheme defined for oobsize %d\n",
  4311. mtd->oobsize);
  4312. BUG();
  4313. }
  4314. }
  4315. if (!chip->write_page)
  4316. chip->write_page = nand_write_page;
  4317. /*
  4318. * Check ECC mode, default to software if 3byte/512byte hardware ECC is
  4319. * selected and we have 256 byte pagesize fallback to software ECC
  4320. */
  4321. switch (ecc->mode) {
  4322. case NAND_ECC_HW_OOB_FIRST:
  4323. /* Similar to NAND_ECC_HW, but a separate read_page handle */
  4324. if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
  4325. pr_warn("No ECC functions supplied; hardware ECC not possible\n");
  4326. BUG();
  4327. }
  4328. if (!ecc->read_page)
  4329. ecc->read_page = nand_read_page_hwecc_oob_first;
  4330. case NAND_ECC_HW:
  4331. /* Use standard hwecc read page function? */
  4332. if (!ecc->read_page)
  4333. ecc->read_page = nand_read_page_hwecc;
  4334. if (!ecc->write_page)
  4335. ecc->write_page = nand_write_page_hwecc;
  4336. if (!ecc->read_page_raw)
  4337. ecc->read_page_raw = nand_read_page_raw;
  4338. if (!ecc->write_page_raw)
  4339. ecc->write_page_raw = nand_write_page_raw;
  4340. if (!ecc->read_oob)
  4341. ecc->read_oob = nand_read_oob_std;
  4342. if (!ecc->write_oob)
  4343. ecc->write_oob = nand_write_oob_std;
  4344. if (!ecc->read_subpage)
  4345. ecc->read_subpage = nand_read_subpage;
  4346. if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
  4347. ecc->write_subpage = nand_write_subpage_hwecc;
  4348. case NAND_ECC_HW_SYNDROME:
  4349. if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
  4350. (!ecc->read_page ||
  4351. ecc->read_page == nand_read_page_hwecc ||
  4352. !ecc->write_page ||
  4353. ecc->write_page == nand_write_page_hwecc)) {
  4354. pr_warn("No ECC functions supplied; hardware ECC not possible\n");
  4355. BUG();
  4356. }
  4357. /* Use standard syndrome read/write page function? */
  4358. if (!ecc->read_page)
  4359. ecc->read_page = nand_read_page_syndrome;
  4360. if (!ecc->write_page)
  4361. ecc->write_page = nand_write_page_syndrome;
  4362. if (!ecc->read_page_raw)
  4363. ecc->read_page_raw = nand_read_page_raw_syndrome;
  4364. if (!ecc->write_page_raw)
  4365. ecc->write_page_raw = nand_write_page_raw_syndrome;
  4366. if (!ecc->read_oob)
  4367. ecc->read_oob = nand_read_oob_syndrome;
  4368. if (!ecc->write_oob)
  4369. ecc->write_oob = nand_write_oob_syndrome;
  4370. if (mtd->writesize >= ecc->size) {
  4371. if (!ecc->strength) {
  4372. pr_warn("Driver must set ecc.strength when using hardware ECC\n");
  4373. BUG();
  4374. }
  4375. break;
  4376. }
  4377. pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
  4378. ecc->size, mtd->writesize);
  4379. ecc->mode = NAND_ECC_SOFT;
  4380. case NAND_ECC_SOFT:
  4381. ecc->calculate = nand_calculate_ecc;
  4382. ecc->correct = nand_correct_data;
  4383. ecc->read_page = nand_read_page_swecc;
  4384. ecc->read_subpage = nand_read_subpage;
  4385. ecc->write_page = nand_write_page_swecc;
  4386. ecc->read_page_raw = nand_read_page_raw;
  4387. ecc->write_page_raw = nand_write_page_raw;
  4388. ecc->read_oob = nand_read_oob_std;
  4389. ecc->write_oob = nand_write_oob_std;
  4390. if (!ecc->size)
  4391. ecc->size = 256;
  4392. ecc->bytes = 3;
  4393. ecc->strength = 1;
  4394. break;
  4395. case NAND_ECC_SOFT_BCH:
  4396. if (!mtd_nand_has_bch()) {
  4397. pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
  4398. BUG();
  4399. }
  4400. ecc->calculate = nand_bch_calculate_ecc;
  4401. ecc->correct = nand_bch_correct_data;
  4402. ecc->read_page = nand_read_page_swecc;
  4403. ecc->read_subpage = nand_read_subpage;
  4404. ecc->write_page = nand_write_page_swecc;
  4405. ecc->read_page_raw = nand_read_page_raw;
  4406. ecc->write_page_raw = nand_write_page_raw;
  4407. ecc->read_oob = nand_read_oob_std;
  4408. ecc->write_oob = nand_write_oob_std;
  4409. /*
  4410. * Board driver should supply ecc.size and ecc.strength values
  4411. * to select how many bits are correctable. Otherwise, default
  4412. * to 4 bits for large page devices.
  4413. */
  4414. if (!ecc->size && (mtd->oobsize >= 64)) {
  4415. ecc->size = 512;
  4416. ecc->strength = 4;
  4417. }
  4418. /* See nand_bch_init() for details. */
  4419. ecc->bytes = 0;
  4420. ecc->priv = nand_bch_init(mtd);
  4421. if (!ecc->priv) {
  4422. pr_warn("BCH ECC initialization failed!\n");
  4423. BUG();
  4424. }
  4425. break;
  4426. case NAND_ECC_NONE:
  4427. pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
  4428. ecc->read_page = nand_read_page_raw;
  4429. ecc->write_page = nand_write_page_raw;
  4430. ecc->read_oob = nand_read_oob_std;
  4431. ecc->read_page_raw = nand_read_page_raw;
  4432. ecc->write_page_raw = nand_write_page_raw;
  4433. ecc->write_oob = nand_write_oob_std;
  4434. ecc->size = mtd->writesize;
  4435. ecc->bytes = 0;
  4436. ecc->strength = 0;
  4437. break;
  4438. default:
  4439. pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
  4440. BUG();
  4441. }
  4442. /* For many systems, the standard OOB write also works for raw */
  4443. if (!ecc->read_oob_raw)
  4444. ecc->read_oob_raw = ecc->read_oob;
  4445. if (!ecc->write_oob_raw)
  4446. ecc->write_oob_raw = ecc->write_oob;
  4447. /*
  4448. * The number of bytes available for a client to place data into
  4449. * the out of band area.
  4450. */
  4451. mtd->oobavail = 0;
  4452. if (ecc->layout) {
  4453. for (i = 0; ecc->layout->oobfree[i].length; i++)
  4454. mtd->oobavail += ecc->layout->oobfree[i].length;
  4455. }
  4456. /* ECC sanity check: warn if it's too weak */
  4457. if (!nand_ecc_strength_good(mtd))
  4458. pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
  4459. mtd->name);
  4460. /*
  4461. * Set the number of read / write steps for one page depending on ECC
  4462. * mode.
  4463. */
  4464. ecc->steps = mtd->writesize / ecc->size;
  4465. if (ecc->steps * ecc->size != mtd->writesize) {
  4466. pr_warn("Invalid ECC parameters\n");
  4467. BUG();
  4468. }
  4469. ecc->total = ecc->steps * ecc->bytes;
  4470. /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
  4471. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
  4472. switch (ecc->steps) {
  4473. case 2:
  4474. mtd->subpage_sft = 1;
  4475. break;
  4476. case 4:
  4477. case 8:
  4478. case 16:
  4479. mtd->subpage_sft = 2;
  4480. break;
  4481. }
  4482. }
  4483. chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
  4484. /* Initialize state */
  4485. chip->state = FL_READY;
  4486. /* Invalidate the pagebuffer reference */
  4487. chip->pagebuf = -1;
  4488. /* Large page NAND with SOFT_ECC should support subpage reads */
  4489. switch (ecc->mode) {
  4490. case NAND_ECC_SOFT:
  4491. case NAND_ECC_SOFT_BCH:
  4492. if (chip->page_shift > 9)
  4493. chip->options |= NAND_SUBPAGE_READ;
  4494. break;
  4495. default:
  4496. break;
  4497. }
  4498. /* Fill in remaining MTD driver data */
  4499. mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
  4500. mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
  4501. MTD_CAP_NANDFLASH;
  4502. mtd->_erase = nand_erase;
  4503. mtd->_panic_write = panic_nand_write;
  4504. mtd->_read_oob = nand_read_oob;
  4505. mtd->_write_oob = nand_write_oob;
  4506. mtd->_sync = nand_sync;
  4507. mtd->_lock = NULL;
  4508. mtd->_unlock = NULL;
  4509. mtd->_block_isreserved = nand_block_isreserved;
  4510. mtd->_block_isbad = nand_block_isbad;
  4511. mtd->_block_markbad = nand_block_markbad;
  4512. mtd->writebufsize = mtd->writesize;
  4513. /* propagate ecc info to mtd_info */
  4514. mtd->ecclayout = ecc->layout;
  4515. mtd->ecc_strength = ecc->strength;
  4516. mtd->ecc_step_size = ecc->size;
  4517. /*
  4518. * Initialize bitflip_threshold to its default prior scan_bbt() call.
  4519. * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
  4520. * properly set.
  4521. */
  4522. if (!mtd->bitflip_threshold)
  4523. mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
  4524. return 0;
  4525. }
  4526. EXPORT_SYMBOL(nand_scan_tail);
  4527. /**
  4528. * nand_scan - [NAND Interface] Scan for the NAND device
  4529. * @mtd: MTD device structure
  4530. * @maxchips: number of chips to scan for
  4531. *
  4532. * This fills out all the uninitialized function pointers with the defaults.
  4533. * The flash ID is read and the mtd/chip structures are filled with the
  4534. * appropriate values.
  4535. */
  4536. int nand_scan(struct mtd_info *mtd, int maxchips)
  4537. {
  4538. int ret;
  4539. ret = nand_scan_ident(mtd, maxchips, NULL);
  4540. if (!ret)
  4541. ret = nand_scan_tail(mtd);
  4542. return ret;
  4543. }
  4544. EXPORT_SYMBOL(nand_scan);
  4545. MODULE_LICENSE("GPL");
  4546. MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
  4547. MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
  4548. MODULE_DESCRIPTION("Generic NAND flash driver code");