cpu.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * cpu.h
  4. *
  5. * AM33xx specific header file
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #ifndef _AM33XX_CPU_H
  10. #define _AM33XX_CPU_H
  11. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  12. #include <asm/types.h>
  13. #include <linux/bitops.h>
  14. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  15. #include <asm/arch/hardware.h>
  16. #define CL_BIT(x) (0 << x)
  17. /* Timer register bits */
  18. #define TCLR_ST BIT(0) /* Start=1 Stop=0 */
  19. #define TCLR_AR BIT(1) /* Auto reload */
  20. #define TCLR_PRE BIT(5) /* Pre-scaler enable */
  21. #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
  22. #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
  23. #define TCLR_CE BIT(6) /* compare mode enable */
  24. #define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
  25. #define TCLR_TCM BIT(8) /* edge detection of input pin*/
  26. #define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
  27. #define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
  28. #define TCLR_CAPTMODE BIT(13) /* capture mode */
  29. #define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
  30. #define TCFG_RESET BIT(0) /* software reset */
  31. #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
  32. #define TCFG_IDLEMOD_SHIFT (2) /* power management */
  33. /* cpu-id for AM43XX AM33XX and TI81XX family */
  34. #define AM437X 0xB98C
  35. #define AM335X 0xB944
  36. #define TI81XX 0xB81E
  37. #define DEVICE_ID (CTRL_BASE + 0x0600)
  38. #define DEVICE_ID_MASK 0x1FFF
  39. #define PACKAGE_TYPE_SHIFT 16
  40. #define PACKAGE_TYPE_MASK (3 << 16)
  41. /* Package Type */
  42. #define PACKAGE_TYPE_UNDEFINED 0x0
  43. #define PACKAGE_TYPE_ZCZ 0x1
  44. #define PACKAGE_TYPE_ZCE 0x2
  45. #define PACKAGE_TYPE_RESERVED 0x3
  46. /* MPU max frequencies */
  47. #define AM335X_ZCZ_300 0x1FEF
  48. #define AM335X_ZCZ_600 0x1FAF
  49. #define AM335X_ZCZ_720 0x1F2F
  50. #define AM335X_ZCZ_800 0x1E2F
  51. #define AM335X_ZCZ_1000 0x1C2F
  52. #define AM335X_ZCE_300 0x1FDF
  53. #define AM335X_ZCE_600 0x1F9F
  54. /* This gives the status of the boot mode pins on the evm */
  55. #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
  56. | BIT(3) | BIT(4))
  57. #define PRM_RSTCTRL_RESET 0x01
  58. #define PRM_RSTST_WARM_RESET_MASK 0x232
  59. /* EMIF Control register bits */
  60. #define EMIF_CTRL_DEVOFF BIT(0)
  61. #ifndef __KERNEL_STRICT_NAMES
  62. #ifndef __ASSEMBLY__
  63. #include <asm/ti-common/omap_wdt.h>
  64. #ifndef CONFIG_AM43XX
  65. /* Encapsulating core pll registers */
  66. struct cm_wkuppll {
  67. unsigned int wkclkstctrl; /* offset 0x00 */
  68. unsigned int wkctrlclkctrl; /* offset 0x04 */
  69. unsigned int wkgpio0clkctrl; /* offset 0x08 */
  70. unsigned int wkl4wkclkctrl; /* offset 0x0c */
  71. unsigned int timer0clkctrl; /* offset 0x10 */
  72. unsigned int resv2[3];
  73. unsigned int idlestdpllmpu; /* offset 0x20 */
  74. unsigned int sscdeltamstepdllmpu; /* off 0x24 */
  75. unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
  76. unsigned int clkseldpllmpu; /* offset 0x2c */
  77. unsigned int resv4[1];
  78. unsigned int idlestdpllddr; /* offset 0x34 */
  79. unsigned int resv5[2];
  80. unsigned int clkseldpllddr; /* offset 0x40 */
  81. unsigned int resv6[4];
  82. unsigned int clkseldplldisp; /* offset 0x54 */
  83. unsigned int resv7[1];
  84. unsigned int idlestdpllcore; /* offset 0x5c */
  85. unsigned int resv8[2];
  86. unsigned int clkseldpllcore; /* offset 0x68 */
  87. unsigned int resv9[1];
  88. unsigned int idlestdpllper; /* offset 0x70 */
  89. unsigned int resv10[2];
  90. unsigned int clkdcoldodpllper; /* offset 0x7c */
  91. unsigned int divm4dpllcore; /* offset 0x80 */
  92. unsigned int divm5dpllcore; /* offset 0x84 */
  93. unsigned int clkmoddpllmpu; /* offset 0x88 */
  94. unsigned int clkmoddpllper; /* offset 0x8c */
  95. unsigned int clkmoddpllcore; /* offset 0x90 */
  96. unsigned int clkmoddpllddr; /* offset 0x94 */
  97. unsigned int clkmoddplldisp; /* offset 0x98 */
  98. unsigned int clkseldpllper; /* offset 0x9c */
  99. unsigned int divm2dpllddr; /* offset 0xA0 */
  100. unsigned int divm2dplldisp; /* offset 0xA4 */
  101. unsigned int divm2dpllmpu; /* offset 0xA8 */
  102. unsigned int divm2dpllper; /* offset 0xAC */
  103. unsigned int resv11[1];
  104. unsigned int wkup_uart0ctrl; /* offset 0xB4 */
  105. unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
  106. unsigned int wkup_adctscctrl; /* offset 0xBC */
  107. unsigned int resv12;
  108. unsigned int timer1clkctrl; /* offset 0xC4 */
  109. unsigned int resv13[4];
  110. unsigned int divm6dpllcore; /* offset 0xD8 */
  111. };
  112. /**
  113. * Encapsulating peripheral functional clocks
  114. * pll registers
  115. */
  116. struct cm_perpll {
  117. unsigned int l4lsclkstctrl; /* offset 0x00 */
  118. unsigned int l3sclkstctrl; /* offset 0x04 */
  119. unsigned int l4fwclkstctrl; /* offset 0x08 */
  120. unsigned int l3clkstctrl; /* offset 0x0c */
  121. unsigned int resv1;
  122. unsigned int cpgmac0clkctrl; /* offset 0x14 */
  123. unsigned int lcdclkctrl; /* offset 0x18 */
  124. unsigned int usb0clkctrl; /* offset 0x1C */
  125. unsigned int resv2;
  126. unsigned int tptc0clkctrl; /* offset 0x24 */
  127. unsigned int emifclkctrl; /* offset 0x28 */
  128. unsigned int ocmcramclkctrl; /* offset 0x2c */
  129. unsigned int gpmcclkctrl; /* offset 0x30 */
  130. unsigned int mcasp0clkctrl; /* offset 0x34 */
  131. unsigned int uart5clkctrl; /* offset 0x38 */
  132. unsigned int mmc0clkctrl; /* offset 0x3C */
  133. unsigned int elmclkctrl; /* offset 0x40 */
  134. unsigned int i2c2clkctrl; /* offset 0x44 */
  135. unsigned int i2c1clkctrl; /* offset 0x48 */
  136. unsigned int spi0clkctrl; /* offset 0x4C */
  137. unsigned int spi1clkctrl; /* offset 0x50 */
  138. unsigned int resv3[3];
  139. unsigned int l4lsclkctrl; /* offset 0x60 */
  140. unsigned int l4fwclkctrl; /* offset 0x64 */
  141. unsigned int mcasp1clkctrl; /* offset 0x68 */
  142. unsigned int uart1clkctrl; /* offset 0x6C */
  143. unsigned int uart2clkctrl; /* offset 0x70 */
  144. unsigned int uart3clkctrl; /* offset 0x74 */
  145. unsigned int uart4clkctrl; /* offset 0x78 */
  146. unsigned int timer7clkctrl; /* offset 0x7C */
  147. unsigned int timer2clkctrl; /* offset 0x80 */
  148. unsigned int timer3clkctrl; /* offset 0x84 */
  149. unsigned int timer4clkctrl; /* offset 0x88 */
  150. unsigned int resv4[8];
  151. unsigned int gpio1clkctrl; /* offset 0xAC */
  152. unsigned int gpio2clkctrl; /* offset 0xB0 */
  153. unsigned int gpio3clkctrl; /* offset 0xB4 */
  154. unsigned int resv5;
  155. unsigned int tpccclkctrl; /* offset 0xBC */
  156. unsigned int dcan0clkctrl; /* offset 0xC0 */
  157. unsigned int dcan1clkctrl; /* offset 0xC4 */
  158. unsigned int resv6;
  159. unsigned int epwmss1clkctrl; /* offset 0xCC */
  160. unsigned int emiffwclkctrl; /* offset 0xD0 */
  161. unsigned int epwmss0clkctrl; /* offset 0xD4 */
  162. unsigned int epwmss2clkctrl; /* offset 0xD8 */
  163. unsigned int l3instrclkctrl; /* offset 0xDC */
  164. unsigned int l3clkctrl; /* Offset 0xE0 */
  165. unsigned int resv8[2];
  166. unsigned int timer5clkctrl; /* offset 0xEC */
  167. unsigned int timer6clkctrl; /* offset 0xF0 */
  168. unsigned int mmc1clkctrl; /* offset 0xF4 */
  169. unsigned int mmc2clkctrl; /* offset 0xF8 */
  170. unsigned int resv9[8];
  171. unsigned int l4hsclkstctrl; /* offset 0x11C */
  172. unsigned int l4hsclkctrl; /* offset 0x120 */
  173. unsigned int resv10[8];
  174. unsigned int cpswclkstctrl; /* offset 0x144 */
  175. unsigned int lcdcclkstctrl; /* offset 0x148 */
  176. };
  177. /* Encapsulating Display pll registers */
  178. struct cm_dpll {
  179. unsigned int resv1;
  180. unsigned int clktimer7clk; /* offset 0x04 */
  181. unsigned int clktimer2clk; /* offset 0x08 */
  182. unsigned int clktimer3clk; /* offset 0x0C */
  183. unsigned int clktimer4clk; /* offset 0x10 */
  184. unsigned int resv2;
  185. unsigned int clktimer5clk; /* offset 0x18 */
  186. unsigned int clktimer6clk; /* offset 0x1C */
  187. unsigned int resv3[2];
  188. unsigned int clktimer1clk; /* offset 0x28 */
  189. unsigned int resv4[2];
  190. unsigned int clklcdcpixelclk; /* offset 0x34 */
  191. };
  192. struct prm_device_inst {
  193. unsigned int prm_rstctrl;
  194. unsigned int prm_rsttime;
  195. unsigned int prm_rstst;
  196. };
  197. #else
  198. /* Encapsulating core pll registers */
  199. struct cm_wkuppll {
  200. unsigned int resv0[136];
  201. unsigned int wkl4wkclkctrl; /* offset 0x220 */
  202. unsigned int resv1[7];
  203. unsigned int usbphy0clkctrl; /* offset 0x240 */
  204. unsigned int resv112;
  205. unsigned int usbphy1clkctrl; /* offset 0x248 */
  206. unsigned int resv113[45];
  207. unsigned int wkclkstctrl; /* offset 0x300 */
  208. unsigned int resv2[15];
  209. unsigned int wkup_i2c0ctrl; /* offset 0x340 */
  210. unsigned int resv3;
  211. unsigned int wkup_uart0ctrl; /* offset 0x348 */
  212. unsigned int resv4[5];
  213. unsigned int wkctrlclkctrl; /* offset 0x360 */
  214. unsigned int resv5;
  215. unsigned int wkgpio0clkctrl; /* offset 0x368 */
  216. unsigned int resv6[109];
  217. unsigned int clkmoddpllcore; /* offset 0x520 */
  218. unsigned int idlestdpllcore; /* offset 0x524 */
  219. unsigned int resv61;
  220. unsigned int clkseldpllcore; /* offset 0x52C */
  221. unsigned int resv7[2];
  222. unsigned int divm4dpllcore; /* offset 0x538 */
  223. unsigned int divm5dpllcore; /* offset 0x53C */
  224. unsigned int divm6dpllcore; /* offset 0x540 */
  225. unsigned int resv8[7];
  226. unsigned int clkmoddpllmpu; /* offset 0x560 */
  227. unsigned int idlestdpllmpu; /* offset 0x564 */
  228. unsigned int resv9;
  229. unsigned int clkseldpllmpu; /* offset 0x56c */
  230. unsigned int divm2dpllmpu; /* offset 0x570 */
  231. unsigned int resv10[11];
  232. unsigned int clkmoddpllddr; /* offset 0x5A0 */
  233. unsigned int idlestdpllddr; /* offset 0x5A4 */
  234. unsigned int resv11;
  235. unsigned int clkseldpllddr; /* offset 0x5AC */
  236. unsigned int divm2dpllddr; /* offset 0x5B0 */
  237. unsigned int resv12[11];
  238. unsigned int clkmoddpllper; /* offset 0x5E0 */
  239. unsigned int idlestdpllper; /* offset 0x5E4 */
  240. unsigned int resv13;
  241. unsigned int clkseldpllper; /* offset 0x5EC */
  242. unsigned int divm2dpllper; /* offset 0x5F0 */
  243. unsigned int resv14[8];
  244. unsigned int clkdcoldodpllper; /* offset 0x614 */
  245. unsigned int resv15[2];
  246. unsigned int clkmoddplldisp; /* offset 0x620 */
  247. unsigned int resv16[2];
  248. unsigned int clkseldplldisp; /* offset 0x62C */
  249. unsigned int divm2dplldisp; /* offset 0x630 */
  250. };
  251. /*
  252. * Encapsulating peripheral functional clocks
  253. * pll registers
  254. */
  255. struct cm_perpll {
  256. unsigned int l3clkstctrl; /* offset 0x00 */
  257. unsigned int resv0[7];
  258. unsigned int l3clkctrl; /* Offset 0x20 */
  259. unsigned int resv112[7];
  260. unsigned int l3instrclkctrl; /* offset 0x40 */
  261. unsigned int resv2[3];
  262. unsigned int ocmcramclkctrl; /* offset 0x50 */
  263. unsigned int resv3[9];
  264. unsigned int tpccclkctrl; /* offset 0x78 */
  265. unsigned int resv4;
  266. unsigned int tptc0clkctrl; /* offset 0x80 */
  267. unsigned int resv5[7];
  268. unsigned int l4hsclkctrl; /* offset 0x0A0 */
  269. unsigned int resv6;
  270. unsigned int l4fwclkctrl; /* offset 0x0A8 */
  271. unsigned int resv7[85];
  272. unsigned int l3sclkstctrl; /* offset 0x200 */
  273. unsigned int resv8[7];
  274. unsigned int gpmcclkctrl; /* offset 0x220 */
  275. unsigned int resv9[5];
  276. unsigned int mcasp0clkctrl; /* offset 0x238 */
  277. unsigned int resv10;
  278. unsigned int mcasp1clkctrl; /* offset 0x240 */
  279. unsigned int resv11;
  280. unsigned int mmc2clkctrl; /* offset 0x248 */
  281. unsigned int resv12[3];
  282. unsigned int qspiclkctrl; /* offset 0x258 */
  283. unsigned int resv121;
  284. unsigned int usb0clkctrl; /* offset 0x260 */
  285. unsigned int resv122;
  286. unsigned int usb1clkctrl; /* offset 0x268 */
  287. unsigned int resv13[101];
  288. unsigned int l4lsclkstctrl; /* offset 0x400 */
  289. unsigned int resv14[7];
  290. unsigned int l4lsclkctrl; /* offset 0x420 */
  291. unsigned int resv15;
  292. unsigned int dcan0clkctrl; /* offset 0x428 */
  293. unsigned int resv16;
  294. unsigned int dcan1clkctrl; /* offset 0x430 */
  295. unsigned int resv17[13];
  296. unsigned int elmclkctrl; /* offset 0x468 */
  297. unsigned int resv18[3];
  298. unsigned int gpio1clkctrl; /* offset 0x478 */
  299. unsigned int resv19;
  300. unsigned int gpio2clkctrl; /* offset 0x480 */
  301. unsigned int resv20;
  302. unsigned int gpio3clkctrl; /* offset 0x488 */
  303. unsigned int resv41;
  304. unsigned int gpio4clkctrl; /* offset 0x490 */
  305. unsigned int resv42;
  306. unsigned int gpio5clkctrl; /* offset 0x498 */
  307. unsigned int resv21[3];
  308. unsigned int i2c1clkctrl; /* offset 0x4A8 */
  309. unsigned int resv22;
  310. unsigned int i2c2clkctrl; /* offset 0x4B0 */
  311. unsigned int resv23[3];
  312. unsigned int mmc0clkctrl; /* offset 0x4C0 */
  313. unsigned int resv24;
  314. unsigned int mmc1clkctrl; /* offset 0x4C8 */
  315. unsigned int resv25[13];
  316. unsigned int spi0clkctrl; /* offset 0x500 */
  317. unsigned int resv26;
  318. unsigned int spi1clkctrl; /* offset 0x508 */
  319. unsigned int resv27[9];
  320. unsigned int timer2clkctrl; /* offset 0x530 */
  321. unsigned int resv28;
  322. unsigned int timer3clkctrl; /* offset 0x538 */
  323. unsigned int resv29;
  324. unsigned int timer4clkctrl; /* offset 0x540 */
  325. unsigned int resv30[5];
  326. unsigned int timer7clkctrl; /* offset 0x558 */
  327. unsigned int resv31[9];
  328. unsigned int uart1clkctrl; /* offset 0x580 */
  329. unsigned int resv32;
  330. unsigned int uart2clkctrl; /* offset 0x588 */
  331. unsigned int resv33;
  332. unsigned int uart3clkctrl; /* offset 0x590 */
  333. unsigned int resv34;
  334. unsigned int uart4clkctrl; /* offset 0x598 */
  335. unsigned int resv35;
  336. unsigned int uart5clkctrl; /* offset 0x5A0 */
  337. unsigned int resv36[5];
  338. unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
  339. unsigned int resv361;
  340. unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
  341. unsigned int resv3611[79];
  342. unsigned int emifclkstctrl; /* offset 0x700 */
  343. unsigned int resv362[7];
  344. unsigned int emifclkctrl; /* offset 0x720 */
  345. unsigned int resv37[3];
  346. unsigned int emiffwclkctrl; /* offset 0x730 */
  347. unsigned int resv371;
  348. unsigned int otfaemifclkctrl; /* offset 0x738 */
  349. unsigned int resv38[57];
  350. unsigned int lcdclkctrl; /* offset 0x820 */
  351. unsigned int resv39[183];
  352. unsigned int cpswclkstctrl; /* offset 0xB00 */
  353. unsigned int resv40[7];
  354. unsigned int cpgmac0clkctrl; /* offset 0xB20 */
  355. };
  356. struct cm_device_inst {
  357. unsigned int cm_clkout1_ctrl;
  358. unsigned int cm_dll_ctrl;
  359. };
  360. struct prm_device_inst {
  361. unsigned int rstctrl;
  362. unsigned int rstst;
  363. unsigned int rsttime;
  364. unsigned int sram_count;
  365. unsigned int ldo_sram_core_set; /* offset 0x10 */
  366. unsigned int ldo_sram_core_ctr;
  367. unsigned int ldo_sram_mpu_setu;
  368. unsigned int ldo_sram_mpu_ctrl;
  369. unsigned int io_count; /* offset 0x20 */
  370. unsigned int io_pmctrl;
  371. unsigned int vc_val_bypass;
  372. unsigned int resv1;
  373. unsigned int emif_ctrl; /* offset 0x30 */
  374. };
  375. struct cm_dpll {
  376. unsigned int resv1;
  377. unsigned int clktimer2clk; /* offset 0x04 */
  378. unsigned int resv2[11];
  379. unsigned int clkselmacclk; /* offset 0x34 */
  380. };
  381. #endif /* CONFIG_AM43XX */
  382. /* Control Module RTC registers */
  383. struct cm_rtc {
  384. unsigned int rtcclkctrl; /* offset 0x0 */
  385. unsigned int clkstctrl; /* offset 0x4 */
  386. };
  387. /* Timer 32 bit registers */
  388. struct gptimer {
  389. unsigned int tidr; /* offset 0x00 */
  390. unsigned char res1[12];
  391. unsigned int tiocp_cfg; /* offset 0x10 */
  392. unsigned char res2[12];
  393. unsigned int tier; /* offset 0x20 */
  394. unsigned int tistatr; /* offset 0x24 */
  395. unsigned int tistat; /* offset 0x28 */
  396. unsigned int tisr; /* offset 0x2c */
  397. unsigned int tcicr; /* offset 0x30 */
  398. unsigned int twer; /* offset 0x34 */
  399. unsigned int tclr; /* offset 0x38 */
  400. unsigned int tcrr; /* offset 0x3c */
  401. unsigned int tldr; /* offset 0x40 */
  402. unsigned int ttgr; /* offset 0x44 */
  403. unsigned int twpc; /* offset 0x48 */
  404. unsigned int tmar; /* offset 0x4c */
  405. unsigned int tcar1; /* offset 0x50 */
  406. unsigned int tscir; /* offset 0x54 */
  407. unsigned int tcar2; /* offset 0x58 */
  408. };
  409. /* UART Registers */
  410. struct uart_sys {
  411. unsigned int resv1[21];
  412. unsigned int uartsyscfg; /* offset 0x54 */
  413. unsigned int uartsyssts; /* offset 0x58 */
  414. };
  415. /* VTP Registers */
  416. struct vtp_reg {
  417. unsigned int vtp0ctrlreg;
  418. };
  419. /* Control Status Register */
  420. struct ctrl_stat {
  421. unsigned int resv1[16];
  422. unsigned int statusreg; /* ofset 0x40 */
  423. unsigned int resv2[51];
  424. unsigned int secure_emif_sdram_config; /* offset 0x0110 */
  425. unsigned int resv3[319];
  426. unsigned int dev_attr;
  427. };
  428. /* AM33XX GPIO registers */
  429. #define OMAP_GPIO_REVISION 0x0000
  430. #define OMAP_GPIO_SYSCONFIG 0x0010
  431. #define OMAP_GPIO_SYSSTATUS 0x0114
  432. #define OMAP_GPIO_IRQSTATUS1 0x002c
  433. #define OMAP_GPIO_IRQSTATUS2 0x0030
  434. #define OMAP_GPIO_IRQSTATUS_SET_0 0x0034
  435. #define OMAP_GPIO_IRQSTATUS_SET_1 0x0038
  436. #define OMAP_GPIO_CTRL 0x0130
  437. #define OMAP_GPIO_OE 0x0134
  438. #define OMAP_GPIO_DATAIN 0x0138
  439. #define OMAP_GPIO_DATAOUT 0x013c
  440. #define OMAP_GPIO_LEVELDETECT0 0x0140
  441. #define OMAP_GPIO_LEVELDETECT1 0x0144
  442. #define OMAP_GPIO_RISINGDETECT 0x0148
  443. #define OMAP_GPIO_FALLINGDETECT 0x014c
  444. #define OMAP_GPIO_DEBOUNCE_EN 0x0150
  445. #define OMAP_GPIO_DEBOUNCE_VAL 0x0154
  446. #define OMAP_GPIO_CLEARDATAOUT 0x0190
  447. #define OMAP_GPIO_SETDATAOUT 0x0194
  448. /* Control Device Register */
  449. /* Control Device Register */
  450. #define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
  451. #define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
  452. #define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
  453. struct ctrl_dev {
  454. unsigned int deviceid; /* offset 0x00 */
  455. unsigned int resv1[7];
  456. unsigned int usb_ctrl0; /* offset 0x20 */
  457. unsigned int resv2;
  458. unsigned int usb_ctrl1; /* offset 0x28 */
  459. unsigned int resv3;
  460. unsigned int macid0l; /* offset 0x30 */
  461. unsigned int macid0h; /* offset 0x34 */
  462. unsigned int macid1l; /* offset 0x38 */
  463. unsigned int macid1h; /* offset 0x3c */
  464. unsigned int resv4[4];
  465. unsigned int miisel; /* offset 0x50 */
  466. unsigned int resv5[7];
  467. unsigned int mreqprio_0; /* offset 0x70 */
  468. unsigned int mreqprio_1; /* offset 0x74 */
  469. unsigned int resv6[97];
  470. unsigned int efuse_sma; /* offset 0x1FC */
  471. };
  472. /* Bandwidth Limiter Portion of the L3Fast Configuration Register */
  473. #define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
  474. #define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
  475. #define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
  476. struct l3f_cfg_bwlimiter {
  477. u32 padding0[2];
  478. u32 modena_init0_bw_fractional;
  479. u32 modena_init0_bw_integer;
  480. u32 modena_init0_watermark_0;
  481. };
  482. /* gmii_sel register defines */
  483. #define GMII1_SEL_MII 0x0
  484. #define GMII1_SEL_RMII 0x1
  485. #define GMII1_SEL_RGMII 0x2
  486. #define GMII2_SEL_MII 0x0
  487. #define GMII2_SEL_RMII 0x4
  488. #define GMII2_SEL_RGMII 0x8
  489. #define RGMII1_IDMODE BIT(4)
  490. #define RGMII2_IDMODE BIT(5)
  491. #define RMII1_IO_CLK_EN BIT(6)
  492. #define RMII2_IO_CLK_EN BIT(7)
  493. #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
  494. #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
  495. #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
  496. #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
  497. #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
  498. /* PWMSS */
  499. struct pwmss_regs {
  500. unsigned int idver;
  501. unsigned int sysconfig;
  502. unsigned int clkconfig;
  503. unsigned int clkstatus;
  504. };
  505. #define ECAP_CLK_EN BIT(0)
  506. #define ECAP_CLK_STOP_REQ BIT(1)
  507. #define EPWM_CLK_EN BIT(8)
  508. #define EPWM_CLK_STOP_REQ BIT(9)
  509. struct pwmss_ecap_regs {
  510. unsigned int tsctr;
  511. unsigned int ctrphs;
  512. unsigned int cap1;
  513. unsigned int cap2;
  514. unsigned int cap3;
  515. unsigned int cap4;
  516. unsigned int resv1[4];
  517. unsigned short ecctl1;
  518. unsigned short ecctl2;
  519. };
  520. struct pwmss_epwm_regs {
  521. unsigned short tbctl;
  522. unsigned short tbsts;
  523. unsigned short tbphshr;
  524. unsigned short tbphs;
  525. unsigned short tbcnt;
  526. unsigned short tbprd;
  527. unsigned short res1;
  528. unsigned short cmpctl;
  529. unsigned short cmpahr;
  530. unsigned short cmpa;
  531. unsigned short cmpb;
  532. unsigned short aqctla;
  533. unsigned short aqctlb;
  534. unsigned short aqsfrc;
  535. unsigned short aqcsfrc;
  536. unsigned short dbctl;
  537. unsigned short dbred;
  538. unsigned short dbfed;
  539. unsigned short tzsel;
  540. unsigned short tzctl;
  541. unsigned short tzflg;
  542. unsigned short tzclr;
  543. unsigned short tzfrc;
  544. unsigned short etsel;
  545. unsigned short etps;
  546. unsigned short etflg;
  547. unsigned short etclr;
  548. unsigned short etfrc;
  549. unsigned short pcctl;
  550. unsigned int res2[66];
  551. unsigned short hrcnfg;
  552. };
  553. /* Capture Control register 2 */
  554. #define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
  555. #define ECTRL2_MDSL_ECAP BIT(9)
  556. #define ECTRL2_CTRSTP_FREERUN BIT(4)
  557. #define ECTRL2_PLSL_LOW BIT(10)
  558. #define ECTRL2_SYNC_EN BIT(5)
  559. #endif /* __ASSEMBLY__ */
  560. #endif /* __KERNEL_STRICT_NAMES */
  561. #endif /* _AM33XX_CPU_H */