fsp_vpd.h 5.0 KB

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  1. /* SPDX-License-Identifier: Intel */
  2. /*
  3. * Copyright (C) 2015, Intel Corporation
  4. * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
  5. */
  6. #ifndef __FSP_VPD_H__
  7. #define __FSP_VPD_H__
  8. #include <stddef.h>
  9. struct __packed memory_upd {
  10. u64 signature; /* Offset 0x0020 */
  11. u8 revision; /* Offset 0x0028 */
  12. u8 unused2[7]; /* Offset 0x0029 */
  13. u16 mrc_init_tseg_size; /* Offset 0x0030 */
  14. u16 mrc_init_mmio_size; /* Offset 0x0032 */
  15. u8 mrc_init_spd_addr1; /* Offset 0x0034 */
  16. u8 mrc_init_spd_addr2; /* Offset 0x0035 */
  17. u8 mem_ch0_config; /* Offset 0x0036 */
  18. u8 mem_ch1_config; /* Offset 0x0037 */
  19. u32 memory_spd_ptr; /* Offset 0x0038 */
  20. u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */
  21. u8 aperture_size; /* Offset 0x003d */
  22. u8 gtt_size; /* Offset 0x003e */
  23. u8 legacy_seg_decode; /* Offset 0x003f */
  24. u8 enable_dvfs; /* Offset 0x0040 */
  25. u8 memory_type; /* Offset 0x0041 */
  26. u8 enable_ca_mirror; /* Offset 0x0042 */
  27. u8 reserved[189]; /* Offset 0x0043 */
  28. };
  29. struct gpio_family {
  30. u32 confg;
  31. u32 confg_changes;
  32. u32 misc;
  33. u32 mmio_addr;
  34. wchar_t *name;
  35. };
  36. struct gpio_pad {
  37. u32 confg0;
  38. u32 confg0_changes;
  39. u32 confg1;
  40. u32 confg1_changes;
  41. u32 community;
  42. u32 mmio_addr;
  43. wchar_t *name;
  44. u32 misc;
  45. };
  46. struct __packed silicon_upd {
  47. u64 signature; /* Offset 0x0100 */
  48. u8 revision; /* Offset 0x0108 */
  49. u8 unused3[7]; /* Offset 0x0109 */
  50. u8 sdcard_mode; /* Offset 0x0110 */
  51. u8 enable_hsuart0; /* Offset 0x0111 */
  52. u8 enable_hsuart1; /* Offset 0x0112 */
  53. u8 enable_azalia; /* Offset 0x0113 */
  54. struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */
  55. u8 enable_sata; /* Offset 0x0118 */
  56. u8 enable_xhci; /* Offset 0x0119 */
  57. u8 lpe_mode; /* Offset 0x011a */
  58. u8 enable_dma0; /* Offset 0x011b */
  59. u8 enable_dma1; /* Offset 0x011c */
  60. u8 enable_i2c0; /* Offset 0x011d */
  61. u8 enable_i2c1; /* Offset 0x011e */
  62. u8 enable_i2c2; /* Offset 0x011f */
  63. u8 enable_i2c3; /* Offset 0x0120 */
  64. u8 enable_i2c4; /* Offset 0x0121 */
  65. u8 enable_i2c5; /* Offset 0x0122 */
  66. u8 enable_i2c6; /* Offset 0x0123 */
  67. u32 graphics_config_ptr; /* Offset 0x0124 */
  68. struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */
  69. struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */
  70. u8 disable_punit_pwr_config; /* Offset 0x0130 */
  71. u8 chv_svid_config; /* Offset 0x0131 */
  72. u8 disable_dptf; /* Offset 0x0132 */
  73. u8 emmc_mode; /* Offset 0x0133 */
  74. u8 usb3_clk_ssc; /* Offset 0x0134 */
  75. u8 disp_clk_ssc; /* Offset 0x0135 */
  76. u8 sata_clk_ssc; /* Offset 0x0136 */
  77. u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */
  78. u8 usb2_port0_txi_set; /* Offset 0x0138 */
  79. u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */
  80. u8 usb2_port0_tx_pe_half; /* Offset 0x013a */
  81. u8 usb2_port1_pe_txi_set; /* Offset 0x013b */
  82. u8 usb2_port1_txi_set; /* Offset 0x013c */
  83. u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */
  84. u8 usb2_port1_tx_pe_half; /* Offset 0x013e */
  85. u8 usb2_port2_pe_txi_set; /* Offset 0x013f */
  86. u8 usb2_port2_txi_set; /* Offset 0x0140 */
  87. u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */
  88. u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */
  89. u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */
  90. u8 usb2_port3_txi_set; /* Offset 0x0144 */
  91. u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */
  92. u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */
  93. u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */
  94. u8 usb2_port4_txi_set; /* Offset 0x0148 */
  95. u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */
  96. u8 usb2_port4_tx_pe_half; /* Offset 0x014a */
  97. u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */
  98. u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */
  99. u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */
  100. u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */
  101. u8 sata_speed; /* Offset 0x014f */
  102. u8 usb_ssic_port; /* Offset 0x0150 */
  103. u8 usb_hsic_port; /* Offset 0x0151 */
  104. u8 pcie_rootport_speed; /* Offset 0x0152 */
  105. u8 enable_ssic; /* Offset 0x0153 */
  106. u32 logo_ptr; /* Offset 0x0154 */
  107. u32 logo_size; /* Offset 0x0158 */
  108. u8 rtc_lock; /* Offset 0x015c */
  109. u8 pmic_i2c_bus; /* Offset 0x015d */
  110. u8 enable_isp; /* Offset 0x015e */
  111. u8 isp_pci_dev_config; /* Offset 0x015f */
  112. u8 turbo_mode; /* Offset 0x0160 */
  113. u8 pnp_settings; /* Offset 0x0161 */
  114. u8 sd_detect_chk; /* Offset 0x0162 */
  115. u8 reserved[411]; /* Offset 0x0163 */
  116. };
  117. #define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */
  118. #define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */
  119. struct __packed upd_region {
  120. u64 signature; /* Offset 0x0000 */
  121. u8 revision; /* Offset 0x0008 */
  122. u8 unused0[7]; /* Offset 0x0009 */
  123. u32 memory_upd_offset; /* Offset 0x0010 */
  124. u32 silicon_upd_offset; /* Offset 0x0014 */
  125. u64 unused1; /* Offset 0x0018 */
  126. struct memory_upd memory_upd; /* Offset 0x0020 */
  127. struct silicon_upd silicon_upd; /* Offset 0x0100 */
  128. u16 terminator; /* Offset 0x02fe */
  129. };
  130. #define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */
  131. struct __packed vpd_region {
  132. u64 sign; /* Offset 0x0000 */
  133. u32 img_rev; /* Offset 0x0008 */
  134. u32 upd_offset; /* Offset 0x000c */
  135. };
  136. #endif /* __FSP_VPD_H__ */