mp.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2010 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <asm/processor.h>
  8. #include <asm/mmu.h>
  9. #include <ioports.h>
  10. #include <lmb.h>
  11. #include <asm/io.h>
  12. #include <asm/mp.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. int cpu_reset(u32 nr)
  15. {
  16. /* dummy function so common/cmd_mp.c will build
  17. * should be implemented in the future, when cpu_release()
  18. * is supported. Be aware there may be a similiar bug
  19. * as exists on MPC85xx w/its PIC having a timing window
  20. * associated to resetting the core */
  21. return 1;
  22. }
  23. int cpu_status(u32 nr)
  24. {
  25. /* dummy function so common/cmd_mp.c will build */
  26. return 0;
  27. }
  28. int cpu_disable(u32 nr)
  29. {
  30. volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
  31. volatile ccsr_gur_t *gur = &immap->im_gur;
  32. switch (nr) {
  33. case 0:
  34. setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
  35. break;
  36. case 1:
  37. setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
  38. break;
  39. default:
  40. printf("Invalid cpu number for disable %d\n", nr);
  41. return 1;
  42. }
  43. return 0;
  44. }
  45. int is_core_disabled(int nr) {
  46. immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
  47. ccsr_gur_t *gur = &immap->im_gur;
  48. u32 devdisr = in_be32(&gur->devdisr);
  49. switch (nr) {
  50. case 0:
  51. return (devdisr & MPC86xx_DEVDISR_CPU0);
  52. case 1:
  53. return (devdisr & MPC86xx_DEVDISR_CPU1);
  54. default:
  55. printf("Invalid cpu number for disable %d\n", nr);
  56. }
  57. return 0;
  58. }
  59. int cpu_release(u32 nr, int argc, char *const argv[])
  60. {
  61. /* dummy function so common/cmd_mp.c will build
  62. * should be implemented in the future */
  63. return 1;
  64. }
  65. u32 determine_mp_bootpg(unsigned int *pagesize)
  66. {
  67. if (pagesize)
  68. *pagesize = 4096;
  69. /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
  70. if ((u64)gd->ram_size > 0xfffff000)
  71. return (0xfff00000);
  72. return (gd->ram_size - (1024 * 1024));
  73. }
  74. void cpu_mp_lmb_reserve(struct lmb *lmb)
  75. {
  76. u32 bootpg = determine_mp_bootpg(NULL);
  77. /* tell u-boot we stole a page */
  78. lmb_reserve(lmb, bootpg, 4096);
  79. }
  80. /*
  81. * Copy the code for other cpus to execute into an
  82. * aligned location accessible via BPTR
  83. */
  84. void setup_mp(void)
  85. {
  86. extern ulong __secondary_start_page;
  87. ulong fixup = (ulong)&__secondary_start_page;
  88. u32 bootpg = determine_mp_bootpg(NULL);
  89. u32 bootpg_va;
  90. if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
  91. /* We're not covered by the DDR mapping, set up BAT */
  92. write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
  93. BATU_VS | BATU_VP,
  94. bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
  95. bootpg_va = CONFIG_SYS_SCRATCH_VA;
  96. } else {
  97. bootpg_va = bootpg;
  98. }
  99. memcpy((void *)bootpg_va, (void *)fixup, 4096);
  100. flush_cache(bootpg_va, 4096);
  101. /* remove the temporary BAT mapping */
  102. if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
  103. write_bat(DBAT7, 0, 0);
  104. /* If the physical location of bootpg is not at fff00000, set BPTR */
  105. if (bootpg != 0xfff00000)
  106. out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
  107. (bootpg >> 12));
  108. }