interrupts.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * (C) Copyright 2002 (440 port)
  7. * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  8. *
  9. * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
  10. * Xianghua Xiao (X.Xiao@motorola.com)
  11. *
  12. * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
  13. * Jeff Brown
  14. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  15. */
  16. #include <common.h>
  17. #include <irq_func.h>
  18. #include <mpc86xx.h>
  19. #include <command.h>
  20. #include <time.h>
  21. #include <asm/processor.h>
  22. #ifdef CONFIG_POST
  23. #include <post.h>
  24. #endif
  25. void interrupt_init_cpu(unsigned *decrementer_count)
  26. {
  27. volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  28. volatile ccsr_pic_t *pic = &immr->im_pic;
  29. #ifdef CONFIG_POST
  30. /*
  31. * The POST word is stored in the PIC's TFRR register which gets
  32. * cleared when the PIC is reset. Save it off so we can restore it
  33. * later.
  34. */
  35. ulong post_word = post_word_load();
  36. #endif
  37. pic->gcr = MPC86xx_PICGCR_RST;
  38. while (pic->gcr & MPC86xx_PICGCR_RST)
  39. ;
  40. pic->gcr = MPC86xx_PICGCR_MODE;
  41. *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  42. debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
  43. (get_tbclk() / 1000000),
  44. *decrementer_count);
  45. #ifdef CONFIG_INTERRUPTS
  46. pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
  47. debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
  48. pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
  49. debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
  50. pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
  51. debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
  52. #if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
  53. pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
  54. debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
  55. #endif
  56. #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
  57. pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
  58. debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
  59. #endif
  60. pic->ctpr = 0; /* 40080 clear current task priority register */
  61. #endif
  62. #ifdef CONFIG_POST
  63. post_word_store(post_word);
  64. #endif
  65. }
  66. /*
  67. * timer_interrupt - gets called when the decrementer overflows,
  68. * with interrupts disabled.
  69. * Trivial implementation - no need to be really accurate.
  70. */
  71. void timer_interrupt_cpu(struct pt_regs *regs)
  72. {
  73. /* nothing to do here */
  74. }
  75. /*
  76. * Install and free a interrupt handler. Not implemented yet.
  77. */
  78. void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  79. {
  80. }
  81. void irq_free_handler(int vec)
  82. {
  83. }
  84. /*
  85. * irqinfo - print information about PCI devices,not implemented.
  86. */
  87. int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  88. {
  89. return 0;
  90. }
  91. /*
  92. * Handle external interrupts
  93. */
  94. void external_interrupt(struct pt_regs *regs)
  95. {
  96. puts("external_interrupt(oops!)\n");
  97. }