cpu.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
  4. * Jeff Brown
  5. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <time.h>
  10. #include <vsprintf.h>
  11. #include <watchdog.h>
  12. #include <command.h>
  13. #include <asm/cache.h>
  14. #include <asm/mmu.h>
  15. #include <mpc86xx.h>
  16. #include <asm/fsl_law.h>
  17. #include <asm/ppc.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /*
  20. * Default board reset function
  21. */
  22. static void
  23. __board_reset(void)
  24. {
  25. /* Do nothing */
  26. }
  27. void board_reset(void) __attribute__((weak, alias("__board_reset")));
  28. int
  29. checkcpu(void)
  30. {
  31. sys_info_t sysinfo;
  32. uint pvr, svr;
  33. uint major, minor;
  34. char buf1[32], buf2[32];
  35. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  36. volatile ccsr_gur_t *gur = &immap->im_gur;
  37. struct cpu_type *cpu;
  38. uint msscr0 = mfspr(MSSCR0);
  39. svr = get_svr();
  40. major = SVR_MAJ(svr);
  41. minor = SVR_MIN(svr);
  42. if (cpu_numcores() > 1) {
  43. #ifndef CONFIG_MP
  44. puts("Unicore software on multiprocessor system!!\n"
  45. "To enable mutlticore build define CONFIG_MP\n");
  46. #endif
  47. }
  48. puts("CPU: ");
  49. cpu = gd->arch.cpu;
  50. puts(cpu->name);
  51. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  52. puts("Core: ");
  53. pvr = get_pvr();
  54. major = PVR_E600_MAJ(pvr);
  55. minor = PVR_E600_MIN(pvr);
  56. printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
  57. if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
  58. puts("\n Core1Translation Enabled");
  59. debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
  60. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  61. get_sys_info(&sysinfo);
  62. puts("Clock Configuration:\n");
  63. printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
  64. printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  65. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  66. strmhz(buf1, sysinfo.freq_systembus / 2),
  67. strmhz(buf2, sysinfo.freq_systembus));
  68. if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  69. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  70. } else {
  71. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  72. sysinfo.freq_localbus);
  73. }
  74. puts("L1: D-cache 32 KiB enabled\n");
  75. puts(" I-cache 32 KiB enabled\n");
  76. puts("L2: ");
  77. if (get_l2cr() & 0x80000000) {
  78. #if defined(CONFIG_ARCH_MPC8610)
  79. puts("256");
  80. #elif defined(CONFIG_ARCH_MPC8641)
  81. puts("512");
  82. #endif
  83. puts(" KiB enabled\n");
  84. } else {
  85. puts("Disabled\n");
  86. }
  87. return 0;
  88. }
  89. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  90. {
  91. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  92. volatile ccsr_gur_t *gur = &immap->im_gur;
  93. /* Attempt board-specific reset */
  94. board_reset();
  95. /* Next try asserting HRESET_REQ */
  96. out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
  97. while (1)
  98. ;
  99. return 1;
  100. }
  101. /*
  102. * Get timebase clock frequency
  103. */
  104. unsigned long
  105. get_tbclk(void)
  106. {
  107. sys_info_t sys_info;
  108. get_sys_info(&sys_info);
  109. return (sys_info.freq_systembus + 3L) / 4L;
  110. }
  111. #if defined(CONFIG_WATCHDOG)
  112. void
  113. watchdog_reset(void)
  114. {
  115. #if defined(CONFIG_ARCH_MPC8610)
  116. /*
  117. * This actually feed the hard enabled watchdog.
  118. */
  119. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  120. volatile ccsr_wdt_t *wdt = &immap->im_wdt;
  121. volatile ccsr_gur_t *gur = &immap->im_gur;
  122. u32 tmp = gur->pordevsr;
  123. if (tmp & 0x4000) {
  124. wdt->swsrr = 0x556c;
  125. wdt->swsrr = 0xaa39;
  126. }
  127. #endif
  128. }
  129. #endif /* CONFIG_WATCHDOG */
  130. /*
  131. * Print out the state of various machine registers.
  132. * Currently prints out LAWs, BR0/OR0, and BATs
  133. */
  134. void print_reginfo(void)
  135. {
  136. print_bats();
  137. print_laws();
  138. print_lbc_regs();
  139. }
  140. /*
  141. * Set the DDR BATs to reflect the actual size of DDR.
  142. *
  143. * dram_size is the actual size of DDR, in bytes
  144. *
  145. * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
  146. * are using a single BAT to cover DDR.
  147. *
  148. * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
  149. * is not defined) then we might have a situation where U-Boot will attempt
  150. * to relocated itself outside of the region mapped by DBAT0.
  151. * This will cause a machine check.
  152. *
  153. * Currently we are limited to power of two sized DDR since we only use a
  154. * single bat. If a non-power of two size is used that is less than
  155. * CONFIG_MAX_MEM_MAPPED u-boot will crash.
  156. *
  157. */
  158. void setup_ddr_bat(phys_addr_t dram_size)
  159. {
  160. unsigned long batu, bl;
  161. bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
  162. if (BATU_SIZE(bl) != dram_size) {
  163. u64 sz = (u64)dram_size - BATU_SIZE(bl);
  164. print_size(sz, " left unmapped\n");
  165. }
  166. batu = bl | BATU_VS | BATU_VP;
  167. write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
  168. write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
  169. }