pci.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004 Freescale Semiconductor.
  4. * Copyright (C) 2003 Motorola Inc.
  5. * Xianghua Xiao (x.xiao@motorola.com)
  6. */
  7. /*
  8. * PCI Configuration space access support for MPC85xx PCI Bridge
  9. */
  10. #include <common.h>
  11. #include <asm/cpm_85xx.h>
  12. #include <pci.h>
  13. #if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
  14. #ifndef CONFIG_SYS_PCI1_MEM_BUS
  15. #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
  16. #endif
  17. #ifndef CONFIG_SYS_PCI1_IO_BUS
  18. #define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
  19. #endif
  20. #ifndef CONFIG_SYS_PCI2_MEM_BUS
  21. #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
  22. #endif
  23. #ifndef CONFIG_SYS_PCI2_IO_BUS
  24. #define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
  25. #endif
  26. static struct pci_controller *pci_hose;
  27. void
  28. pci_mpc85xx_init(struct pci_controller *board_hose)
  29. {
  30. u16 reg16;
  31. u32 dev;
  32. volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
  33. #ifdef CONFIG_MPC85XX_PCI2
  34. volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
  35. #endif
  36. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  37. struct pci_controller * hose;
  38. pci_hose = board_hose;
  39. hose = &pci_hose[0];
  40. hose->first_busno = 0;
  41. hose->last_busno = 0xff;
  42. pci_setup_indirect(hose,
  43. (CONFIG_SYS_IMMR+0x8000),
  44. (CONFIG_SYS_IMMR+0x8004));
  45. /*
  46. * Hose scan.
  47. */
  48. dev = PCI_BDF(hose->first_busno, 0, 0);
  49. pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  50. reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  51. pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  52. /*
  53. * Clear non-reserved bits in status register.
  54. */
  55. pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  56. if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
  57. /* PCI-X init */
  58. if (CONFIG_SYS_CLK_FREQ < 66000000)
  59. printf("PCI-X will only work at 66 MHz\n");
  60. reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  61. | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  62. pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
  63. }
  64. pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
  65. pcix->potear1 = 0x00000000;
  66. pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
  67. pcix->powbear1 = 0x00000000;
  68. pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
  69. POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
  70. pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
  71. pcix->potear2 = 0x00000000;
  72. pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
  73. pcix->powbear2 = 0x00000000;
  74. pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
  75. POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
  76. pcix->pitar1 = 0x00000000;
  77. pcix->piwbar1 = 0x00000000;
  78. pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  79. PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
  80. pcix->powar3 = 0;
  81. pcix->powar4 = 0;
  82. pcix->piwar2 = 0;
  83. pcix->piwar3 = 0;
  84. pci_set_region(hose->regions + 0,
  85. CONFIG_SYS_PCI1_MEM_BUS,
  86. CONFIG_SYS_PCI1_MEM_PHYS,
  87. CONFIG_SYS_PCI1_MEM_SIZE,
  88. PCI_REGION_MEM);
  89. pci_set_region(hose->regions + 1,
  90. CONFIG_SYS_PCI1_IO_BUS,
  91. CONFIG_SYS_PCI1_IO_PHYS,
  92. CONFIG_SYS_PCI1_IO_SIZE,
  93. PCI_REGION_IO);
  94. hose->region_count = 2;
  95. pci_register_hose(hose);
  96. #if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
  97. /*
  98. * This is a SW workaround for an apparent HW problem
  99. * in the PCI controller on the MPC85555/41 CDS boards.
  100. * The first config cycle must be to a valid, known
  101. * device on the PCI bus in order to trick the PCI
  102. * controller state machine into a known valid state.
  103. * Without this, the first config cycle has the chance
  104. * of hanging the controller permanently, just leaving
  105. * it in a semi-working state, or leaving it working.
  106. *
  107. * Pick on the Tundra, Device 17, to get it right.
  108. */
  109. {
  110. u8 header_type;
  111. pci_hose_read_config_byte(hose,
  112. PCI_BDF(0,BRIDGE_ID,0),
  113. PCI_HEADER_TYPE,
  114. &header_type);
  115. }
  116. #endif
  117. hose->last_busno = pci_hose_scan(hose);
  118. #ifdef CONFIG_MPC85XX_PCI2
  119. hose = &pci_hose[1];
  120. hose->first_busno = pci_hose[0].last_busno + 1;
  121. hose->last_busno = 0xff;
  122. pci_setup_indirect(hose,
  123. (CONFIG_SYS_IMMR+0x9000),
  124. (CONFIG_SYS_IMMR+0x9004));
  125. dev = PCI_BDF(hose->first_busno, 0, 0);
  126. pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  127. reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  128. pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  129. /*
  130. * Clear non-reserved bits in status register.
  131. */
  132. pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  133. pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
  134. pcix2->potear1 = 0x00000000;
  135. pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
  136. pcix2->powbear1 = 0x00000000;
  137. pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
  138. POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
  139. pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
  140. pcix2->potear2 = 0x00000000;
  141. pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
  142. pcix2->powbear2 = 0x00000000;
  143. pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
  144. POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
  145. pcix2->pitar1 = 0x00000000;
  146. pcix2->piwbar1 = 0x00000000;
  147. pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  148. PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
  149. pcix2->powar3 = 0;
  150. pcix2->powar4 = 0;
  151. pcix2->piwar2 = 0;
  152. pcix2->piwar3 = 0;
  153. pci_set_region(hose->regions + 0,
  154. CONFIG_SYS_PCI2_MEM_BUS,
  155. CONFIG_SYS_PCI2_MEM_PHYS,
  156. CONFIG_SYS_PCI2_MEM_SIZE,
  157. PCI_REGION_MEM);
  158. pci_set_region(hose->regions + 1,
  159. CONFIG_SYS_PCI2_IO_BUS,
  160. CONFIG_SYS_PCI2_IO_PHYS,
  161. CONFIG_SYS_PCI2_IO_SIZE,
  162. PCI_REGION_IO);
  163. hose->region_count = 2;
  164. /*
  165. * Hose scan.
  166. */
  167. pci_register_hose(hose);
  168. hose->last_busno = pci_hose_scan(hose);
  169. #endif
  170. }
  171. #endif /* !CONFIG_FSL_PCI_INIT */