p2041_serdes.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/fsl_serdes.h>
  7. #include <asm/processor.h>
  8. #include <asm/io.h>
  9. #include "fsl_corenet_serdes.h"
  10. static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
  11. [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
  12. NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  13. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
  14. [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
  15. NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  16. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
  17. [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
  18. PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
  19. SATA2, NONE, NONE, NONE, NONE, },
  20. [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
  21. PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1,
  22. XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, },
  23. [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
  24. PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
  25. PCIE3, NONE, NONE, NONE, NONE, },
  26. [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
  27. SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
  28. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
  29. [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
  30. PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
  31. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
  32. NONE, NONE, NONE, },
  33. [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
  34. SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
  35. NONE, NONE, NONE, },
  36. [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
  37. SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  38. XAUI_FM1, NONE, NONE, NONE, NONE, },
  39. [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
  40. PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
  41. NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
  42. [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
  43. SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
  44. NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
  45. [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
  46. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
  47. SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
  48. };
  49. enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
  50. {
  51. enum srds_prtcl prtcl;
  52. u32 svr = get_svr();
  53. u32 ver = SVR_SOC_VER(svr);
  54. if (!serdes_lane_enabled(lane))
  55. return NONE;
  56. prtcl = serdes_cfg_tbl[cfg][lane];
  57. /* P2040[e] does not support XAUI */
  58. if (ver == SVR_P2040 && prtcl == XAUI_FM1)
  59. prtcl = NONE;
  60. return prtcl;
  61. }
  62. int is_serdes_prtcl_valid(u32 prtcl)
  63. {
  64. int i;
  65. u32 svr = get_svr();
  66. u32 ver = SVR_SOC_VER(svr);
  67. if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
  68. return 0;
  69. /* P2040[e] does not support XAUI */
  70. if (ver == SVR_P2040 && prtcl == XAUI_FM1)
  71. return 0;
  72. for (i = 0; i < SRDS_MAX_LANES; i++) {
  73. if (serdes_cfg_tbl[prtcl][i] != NONE)
  74. return 1;
  75. }
  76. return 0;
  77. }