mpc8544_serdes.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010 Freescale Semiconductor, Inc.
  4. */
  5. #include <config.h>
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/immap_85xx.h>
  9. #include <asm/fsl_serdes.h>
  10. #define SRDS1_MAX_LANES 8
  11. #define SRDS2_MAX_LANES 4
  12. static u32 serdes1_prtcl_map, serdes2_prtcl_map;
  13. static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  14. [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  15. [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  16. [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  17. [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  18. [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  19. [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  20. };
  21. static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
  22. [0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  23. [0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  24. [0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  25. [0x6] = {PCIE3, NONE, NONE, NONE},
  26. [0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
  27. };
  28. int is_serdes_configured(enum srds_prtcl device)
  29. {
  30. int ret;
  31. if (!(serdes1_prtcl_map & (1 << NONE)))
  32. fsl_serdes_init();
  33. ret = (1 << device) & serdes1_prtcl_map;
  34. if (ret)
  35. return ret;
  36. if (!(serdes2_prtcl_map & (1 << NONE)))
  37. fsl_serdes_init();
  38. return (1 << device) & serdes2_prtcl_map;
  39. }
  40. void fsl_serdes_init(void)
  41. {
  42. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  43. u32 pordevsr = in_be32(&gur->pordevsr);
  44. u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  45. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  46. int lane;
  47. if (serdes1_prtcl_map & (1 << NONE) &&
  48. serdes2_prtcl_map & (1 << NONE))
  49. return;
  50. debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  51. if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  52. printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  53. return;
  54. }
  55. for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  56. enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  57. serdes1_prtcl_map |= (1 << lane_prtcl);
  58. }
  59. /* Set the first bit to indicate serdes has been initialized */
  60. serdes1_prtcl_map |= (1 << NONE);
  61. if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
  62. printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  63. return;
  64. }
  65. for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
  66. enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
  67. serdes2_prtcl_map |= (1 << lane_prtcl);
  68. }
  69. if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
  70. serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
  71. if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
  72. serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
  73. /* Set the first bit to indicate serdes has been initialized */
  74. serdes2_prtcl_map |= (1 << NONE);
  75. }