mpc8536_serdes.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008,2010 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. */
  6. #include <config.h>
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/immap_85xx.h>
  10. #include <asm/fsl_serdes.h>
  11. /* PORDEVSR register */
  12. #define GUTS_PORDEVSR_OFFS 0xc
  13. #define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000
  14. #define GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT 27
  15. /* SerDes CR0 register */
  16. #define FSL_SRDSCR0_OFFS 0x0
  17. #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
  18. #define FSL_SRDSCR0_TXEQA_SGMII 0x00004000
  19. #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
  20. #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
  21. #define FSL_SRDSCR0_TXEQE_SGMII 0x00000400
  22. #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
  23. /* SerDes CR1 register */
  24. #define FSL_SRDSCR1_OFFS 0x4
  25. #define FSL_SRDSCR1_LANEA_MASK 0x80200000
  26. #define FSL_SRDSCR1_LANEA_OFF 0x80200000
  27. #define FSL_SRDSCR1_LANEE_MASK 0x08020000
  28. #define FSL_SRDSCR1_LANEE_OFF 0x08020000
  29. /* SerDes CR2 register */
  30. #define FSL_SRDSCR2_OFFS 0x8
  31. #define FSL_SRDSCR2_EICA_MASK 0x00001f00
  32. #define FSL_SRDSCR2_EICA_SGMII 0x00000400
  33. #define FSL_SRDSCR2_EICA_SATA 0x00001400
  34. #define FSL_SRDSCR2_EICE_MASK 0x0000001f
  35. #define FSL_SRDSCR2_EICE_SGMII 0x00000004
  36. #define FSL_SRDSCR2_EICE_SATA 0x00000014
  37. /* SerDes CR3 register */
  38. #define FSL_SRDSCR3_OFFS 0xc
  39. #define FSL_SRDSCR3_LANEA_MASK 0x3f000700
  40. #define FSL_SRDSCR3_LANEA_SGMII 0x00000000
  41. #define FSL_SRDSCR3_LANEA_SATA 0x15000500
  42. #define FSL_SRDSCR3_LANEE_MASK 0x003f0007
  43. #define FSL_SRDSCR3_LANEE_SGMII 0x00000000
  44. #define FSL_SRDSCR3_LANEE_SATA 0x00150005
  45. #define SRDS1_MAX_LANES 8
  46. #define SRDS2_MAX_LANES 2
  47. static u32 serdes1_prtcl_map, serdes2_prtcl_map;
  48. static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  49. [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  50. [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
  51. [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  52. [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
  53. };
  54. static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
  55. [0x1] = {SATA1, SATA2},
  56. [0x3] = {SATA1, NONE},
  57. [0x4] = {SGMII_TSEC1, SGMII_TSEC3},
  58. [0x6] = {SGMII_TSEC1, NONE},
  59. };
  60. int is_serdes_configured(enum srds_prtcl device)
  61. {
  62. int ret;
  63. if (!(serdes1_prtcl_map & (1 << NONE)))
  64. fsl_serdes_init();
  65. ret = (1 << device) & serdes1_prtcl_map;
  66. if (ret)
  67. return ret;
  68. if (!(serdes2_prtcl_map & (1 << NONE)))
  69. fsl_serdes_init();
  70. return (1 << device) & serdes2_prtcl_map;
  71. }
  72. void fsl_serdes_init(void)
  73. {
  74. void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  75. void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
  76. u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
  77. u32 srds1_io_sel, srds2_io_sel;
  78. u32 tmp;
  79. int lane;
  80. if (serdes1_prtcl_map & (1 << NONE) &&
  81. serdes2_prtcl_map & (1 << NONE))
  82. return;
  83. srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  84. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  85. /* parse the SRDS2_IO_SEL of PORDEVSR */
  86. srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
  87. >> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
  88. debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel);
  89. debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel);
  90. switch (srds2_io_sel) {
  91. case 1: /* Lane A - SATA1, Lane E - SATA2 */
  92. /* CR 0 */
  93. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  94. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  95. tmp |= FSL_SRDSCR0_TXEQA_SATA;
  96. tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
  97. tmp |= FSL_SRDSCR0_TXEQE_SATA;
  98. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  99. /* CR 1 */
  100. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  101. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  102. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  103. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  104. /* CR 2 */
  105. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  106. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  107. tmp |= FSL_SRDSCR2_EICA_SATA;
  108. tmp &= ~FSL_SRDSCR2_EICE_MASK;
  109. tmp |= FSL_SRDSCR2_EICE_SATA;
  110. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  111. /* CR 3 */
  112. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  113. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  114. tmp |= FSL_SRDSCR3_LANEA_SATA;
  115. tmp &= ~FSL_SRDSCR3_LANEE_MASK;
  116. tmp |= FSL_SRDSCR3_LANEE_SATA;
  117. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  118. break;
  119. case 3: /* Lane A - SATA1, Lane E - disabled */
  120. /* CR 0 */
  121. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  122. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  123. tmp |= FSL_SRDSCR0_TXEQA_SATA;
  124. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  125. /* CR 1 */
  126. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  127. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  128. tmp |= FSL_SRDSCR1_LANEE_OFF;
  129. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  130. /* CR 2 */
  131. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  132. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  133. tmp |= FSL_SRDSCR2_EICA_SATA;
  134. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  135. /* CR 3 */
  136. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  137. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  138. tmp |= FSL_SRDSCR3_LANEA_SATA;
  139. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  140. break;
  141. case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */
  142. /* CR 0 */
  143. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  144. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  145. tmp |= FSL_SRDSCR0_TXEQA_SGMII;
  146. tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
  147. tmp |= FSL_SRDSCR0_TXEQE_SGMII;
  148. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  149. /* CR 1 */
  150. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  151. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  152. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  153. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  154. /* CR 2 */
  155. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  156. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  157. tmp |= FSL_SRDSCR2_EICA_SGMII;
  158. tmp &= ~FSL_SRDSCR2_EICE_MASK;
  159. tmp |= FSL_SRDSCR2_EICE_SGMII;
  160. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  161. /* CR 3 */
  162. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  163. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  164. tmp |= FSL_SRDSCR3_LANEA_SGMII;
  165. tmp &= ~FSL_SRDSCR3_LANEE_MASK;
  166. tmp |= FSL_SRDSCR3_LANEE_SGMII;
  167. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  168. break;
  169. case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */
  170. /* CR 0 */
  171. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  172. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  173. tmp |= FSL_SRDSCR0_TXEQA_SGMII;
  174. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  175. /* CR 1 */
  176. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  177. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  178. tmp |= FSL_SRDSCR1_LANEE_OFF;
  179. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  180. /* CR 2 */
  181. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  182. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  183. tmp |= FSL_SRDSCR2_EICA_SGMII;
  184. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  185. /* CR 3 */
  186. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  187. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  188. tmp |= FSL_SRDSCR3_LANEA_SGMII;
  189. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  190. break;
  191. case 7: /* Lane A - disabled, Lane E - disabled */
  192. /* CR 1 */
  193. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  194. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  195. tmp |= FSL_SRDSCR1_LANEA_OFF;
  196. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  197. tmp |= FSL_SRDSCR1_LANEE_OFF;
  198. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  199. break;
  200. default:
  201. break;
  202. }
  203. if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  204. printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
  205. return;
  206. }
  207. for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  208. enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane];
  209. serdes1_prtcl_map |= (1 << lane_prtcl);
  210. }
  211. /* Set the first bit to indicate serdes has been initialized */
  212. serdes1_prtcl_map |= (1 << NONE);
  213. if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
  214. printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
  215. return;
  216. }
  217. for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
  218. enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
  219. serdes2_prtcl_map |= (1 << lane_prtcl);
  220. }
  221. /* Set the first bit to indicate serdes has been initialized */
  222. serdes2_prtcl_map |= (1 << NONE);
  223. }