mp.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <env.h>
  8. #include <asm/processor.h>
  9. #include <env.h>
  10. #include <ioports.h>
  11. #include <lmb.h>
  12. #include <asm/io.h>
  13. #include <asm/mmu.h>
  14. #include <asm/fsl_law.h>
  15. #include <fsl_ddr_sdram.h>
  16. #include "mp.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. u32 fsl_ddr_get_intl3r(void);
  19. extern u32 __spin_table[];
  20. u32 get_my_id()
  21. {
  22. return mfspr(SPRN_PIR);
  23. }
  24. /*
  25. * Determine if U-Boot should keep secondary cores in reset, or let them out
  26. * of reset and hold them in a spinloop
  27. */
  28. int hold_cores_in_reset(int verbose)
  29. {
  30. /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
  31. if (env_get_yesno("mp_holdoff") == 1) {
  32. if (verbose) {
  33. puts("Secondary cores are being held in reset.\n");
  34. puts("See 'mp_holdoff' environment variable\n");
  35. }
  36. return 1;
  37. }
  38. return 0;
  39. }
  40. int cpu_reset(u32 nr)
  41. {
  42. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  43. out_be32(&pic->pir, 1 << nr);
  44. /* the dummy read works around an errata on early 85xx MP PICs */
  45. (void)in_be32(&pic->pir);
  46. out_be32(&pic->pir, 0x0);
  47. return 0;
  48. }
  49. int cpu_status(u32 nr)
  50. {
  51. u32 *table, id = get_my_id();
  52. if (hold_cores_in_reset(1))
  53. return 0;
  54. if (nr == id) {
  55. table = (u32 *)&__spin_table;
  56. printf("table base @ 0x%p\n", table);
  57. } else if (is_core_disabled(nr)) {
  58. puts("Disabled\n");
  59. } else {
  60. table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
  61. printf("Running on cpu %d\n", id);
  62. printf("\n");
  63. printf("table @ 0x%p\n", table);
  64. printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
  65. printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
  66. printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
  67. }
  68. return 0;
  69. }
  70. #ifdef CONFIG_FSL_CORENET
  71. int cpu_disable(u32 nr)
  72. {
  73. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  74. setbits_be32(&gur->coredisrl, 1 << nr);
  75. return 0;
  76. }
  77. int is_core_disabled(int nr) {
  78. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  79. u32 coredisrl = in_be32(&gur->coredisrl);
  80. return (coredisrl & (1 << nr));
  81. }
  82. #else
  83. int cpu_disable(u32 nr)
  84. {
  85. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  86. switch (nr) {
  87. case 0:
  88. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
  89. break;
  90. case 1:
  91. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
  92. break;
  93. default:
  94. printf("Invalid cpu number for disable %d\n", nr);
  95. return 1;
  96. }
  97. return 0;
  98. }
  99. int is_core_disabled(int nr) {
  100. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  101. u32 devdisr = in_be32(&gur->devdisr);
  102. switch (nr) {
  103. case 0:
  104. return (devdisr & MPC85xx_DEVDISR_CPU0);
  105. case 1:
  106. return (devdisr & MPC85xx_DEVDISR_CPU1);
  107. default:
  108. printf("Invalid cpu number for disable %d\n", nr);
  109. }
  110. return 0;
  111. }
  112. #endif
  113. static u8 boot_entry_map[4] = {
  114. 0,
  115. BOOT_ENTRY_PIR,
  116. BOOT_ENTRY_R3_LOWER,
  117. };
  118. int cpu_release(u32 nr, int argc, char *const argv[])
  119. {
  120. u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
  121. u64 boot_addr;
  122. if (hold_cores_in_reset(1))
  123. return 0;
  124. if (nr == get_my_id()) {
  125. printf("Invalid to release the boot core.\n\n");
  126. return 1;
  127. }
  128. if (argc != 4) {
  129. printf("Invalid number of arguments to release.\n\n");
  130. return 1;
  131. }
  132. boot_addr = simple_strtoull(argv[0], NULL, 16);
  133. /* handle pir, r3 */
  134. for (i = 1; i < 3; i++) {
  135. if (argv[i][0] != '-') {
  136. u8 entry = boot_entry_map[i];
  137. val = simple_strtoul(argv[i], NULL, 16);
  138. table[entry] = val;
  139. }
  140. }
  141. table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
  142. /* ensure all table updates complete before final address write */
  143. eieio();
  144. table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
  145. return 0;
  146. }
  147. u32 determine_mp_bootpg(unsigned int *pagesize)
  148. {
  149. u32 bootpg;
  150. #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
  151. u32 svr = get_svr();
  152. u32 granule_size, check;
  153. struct law_entry e;
  154. #endif
  155. /* use last 4K of mapped memory */
  156. bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
  157. CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
  158. CONFIG_SYS_SDRAM_BASE - 4096;
  159. if (pagesize)
  160. *pagesize = 4096;
  161. #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
  162. /*
  163. * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
  164. * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
  165. * the way boot page chosen in u-boot avoids hitting this erratum. So only
  166. * thw workaround for 3-way interleaving is needed.
  167. *
  168. * To make sure boot page translation works with 3-Way DDR interleaving
  169. * enforce a check for the following constrains
  170. * 8K granule size requires BRSIZE=8K and
  171. * bootpg >> log2(BRSIZE) %3 == 1
  172. * 4K and 1K granule size requires BRSIZE=4K and
  173. * bootpg >> log2(BRSIZE) %3 == 0
  174. */
  175. if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
  176. e = find_law(bootpg);
  177. switch (e.trgt_id) {
  178. case LAW_TRGT_IF_DDR_INTLV_123:
  179. granule_size = fsl_ddr_get_intl3r() & 0x1f;
  180. if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
  181. if (pagesize)
  182. *pagesize = 8192;
  183. bootpg &= 0xffffe000; /* align to 8KB */
  184. check = bootpg >> 13;
  185. while ((check % 3) != 1)
  186. check--;
  187. bootpg = check << 13;
  188. debug("Boot page (8K) at 0x%08x\n", bootpg);
  189. break;
  190. } else {
  191. bootpg &= 0xfffff000; /* align to 4KB */
  192. check = bootpg >> 12;
  193. while ((check % 3) != 0)
  194. check--;
  195. bootpg = check << 12;
  196. debug("Boot page (4K) at 0x%08x\n", bootpg);
  197. }
  198. break;
  199. default:
  200. break;
  201. }
  202. }
  203. #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
  204. return bootpg;
  205. }
  206. phys_addr_t get_spin_phys_addr(void)
  207. {
  208. return virt_to_phys(&__spin_table);
  209. }
  210. #ifdef CONFIG_FSL_CORENET
  211. static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
  212. {
  213. u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
  214. u32 *table = (u32 *)&__spin_table;
  215. volatile ccsr_gur_t *gur;
  216. volatile ccsr_local_t *ccm;
  217. volatile ccsr_rcpm_t *rcpm;
  218. volatile ccsr_pic_t *pic;
  219. int timeout = 10;
  220. u32 mask = cpu_mask();
  221. struct law_entry e;
  222. gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  223. ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
  224. rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  225. pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  226. whoami = in_be32(&pic->whoami);
  227. cpu_up_mask = 1 << whoami;
  228. out_be32(&ccm->bstrl, bootpg);
  229. e = find_law(bootpg);
  230. /* pagesize is only 4K or 8K */
  231. if (pagesize == 8192)
  232. brsize = LAW_SIZE_8K;
  233. out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
  234. debug("BRSIZE is 0x%x\n", brsize);
  235. /* readback to sync write */
  236. in_be32(&ccm->bstrar);
  237. /* disable time base at the platform */
  238. out_be32(&rcpm->ctbenrl, cpu_up_mask);
  239. out_be32(&gur->brrl, mask);
  240. /* wait for everyone */
  241. while (timeout) {
  242. unsigned int i, cpu, nr_cpus = cpu_numcores();
  243. for_each_cpu(i, cpu, nr_cpus, mask) {
  244. if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
  245. cpu_up_mask |= (1 << cpu);
  246. }
  247. if ((cpu_up_mask & mask) == mask)
  248. break;
  249. udelay(100);
  250. timeout--;
  251. }
  252. if (timeout == 0)
  253. printf("CPU up timeout. CPU up mask is %x should be %x\n",
  254. cpu_up_mask, mask);
  255. /* enable time base at the platform */
  256. out_be32(&rcpm->ctbenrl, 0);
  257. /* readback to sync write */
  258. in_be32(&rcpm->ctbenrl);
  259. mtspr(SPRN_TBWU, 0);
  260. mtspr(SPRN_TBWL, 0);
  261. out_be32(&rcpm->ctbenrl, mask);
  262. #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
  263. /*
  264. * Disabling Boot Page Translation allows the memory region 0xfffff000
  265. * to 0xffffffff to be used normally. Leaving Boot Page Translation
  266. * enabled remaps 0xfffff000 to SDRAM which makes that memory region
  267. * unusable for normal operation but it does allow OSes to easily
  268. * reset a processor core to put it back into U-Boot's spinloop.
  269. */
  270. clrbits_be32(&ccm->bstrar, LAW_EN);
  271. #endif
  272. }
  273. #else
  274. static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
  275. {
  276. u32 up, cpu_up_mask, whoami;
  277. u32 *table = (u32 *)&__spin_table;
  278. volatile u32 bpcr;
  279. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  280. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  281. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  282. u32 devdisr;
  283. int timeout = 10;
  284. whoami = in_be32(&pic->whoami);
  285. out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
  286. /* disable time base at the platform */
  287. devdisr = in_be32(&gur->devdisr);
  288. if (whoami)
  289. devdisr |= MPC85xx_DEVDISR_TB0;
  290. else
  291. devdisr |= MPC85xx_DEVDISR_TB1;
  292. out_be32(&gur->devdisr, devdisr);
  293. /* release the hounds */
  294. up = ((1 << cpu_numcores()) - 1);
  295. bpcr = in_be32(&ecm->eebpcr);
  296. bpcr |= (up << 24);
  297. out_be32(&ecm->eebpcr, bpcr);
  298. asm("sync; isync; msync");
  299. cpu_up_mask = 1 << whoami;
  300. /* wait for everyone */
  301. while (timeout) {
  302. int i;
  303. for (i = 0; i < cpu_numcores(); i++) {
  304. if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
  305. cpu_up_mask |= (1 << i);
  306. };
  307. if ((cpu_up_mask & up) == up)
  308. break;
  309. udelay(100);
  310. timeout--;
  311. }
  312. if (timeout == 0)
  313. printf("CPU up timeout. CPU up mask is %x should be %x\n",
  314. cpu_up_mask, up);
  315. /* enable time base at the platform */
  316. if (whoami)
  317. devdisr |= MPC85xx_DEVDISR_TB1;
  318. else
  319. devdisr |= MPC85xx_DEVDISR_TB0;
  320. out_be32(&gur->devdisr, devdisr);
  321. /* readback to sync write */
  322. in_be32(&gur->devdisr);
  323. mtspr(SPRN_TBWU, 0);
  324. mtspr(SPRN_TBWL, 0);
  325. devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
  326. out_be32(&gur->devdisr, devdisr);
  327. #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
  328. /*
  329. * Disabling Boot Page Translation allows the memory region 0xfffff000
  330. * to 0xffffffff to be used normally. Leaving Boot Page Translation
  331. * enabled remaps 0xfffff000 to SDRAM which makes that memory region
  332. * unusable for normal operation but it does allow OSes to easily
  333. * reset a processor core to put it back into U-Boot's spinloop.
  334. */
  335. clrbits_be32(&ecm->bptr, 0x80000000);
  336. #endif
  337. }
  338. #endif
  339. void cpu_mp_lmb_reserve(struct lmb *lmb)
  340. {
  341. u32 bootpg = determine_mp_bootpg(NULL);
  342. lmb_reserve(lmb, bootpg, 4096);
  343. }
  344. void setup_mp(void)
  345. {
  346. extern u32 __secondary_start_page;
  347. extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
  348. int i;
  349. ulong fixup = (u32)&__secondary_start_page;
  350. u32 bootpg, bootpg_map, pagesize;
  351. bootpg = determine_mp_bootpg(&pagesize);
  352. /*
  353. * pagesize is only 4K or 8K
  354. * we only use the last 4K of boot page
  355. * bootpg_map saves the address for the boot page
  356. * 8K is used for the workaround of 3-way DDR interleaving
  357. */
  358. bootpg_map = bootpg;
  359. if (pagesize == 8192)
  360. bootpg += 4096; /* use 2nd half */
  361. /* Some OSes expect secondary cores to be held in reset */
  362. if (hold_cores_in_reset(0))
  363. return;
  364. /*
  365. * Store the bootpg's cache-able half address for use by secondary
  366. * CPU cores to continue to boot
  367. */
  368. __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
  369. /* Store spin table's physical address for use by secondary cores */
  370. __spin_table_addr = (u32)get_spin_phys_addr();
  371. /* flush bootpg it before copying invalidate any staled cacheline */
  372. flush_cache(bootpg, 4096);
  373. /* look for the tlb covering the reset page, there better be one */
  374. i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
  375. /* we found a match */
  376. if (i != -1) {
  377. /* map reset page to bootpg so we can copy code there */
  378. disable_tlb(i);
  379. set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
  380. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  381. 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
  382. memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
  383. plat_mp_up(bootpg_map, pagesize);
  384. } else {
  385. puts("WARNING: No reset page TLB. "
  386. "Skipping secondary core setup\n");
  387. }
  388. }