interrupts.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * (C) Copyright 2002 (440 port)
  7. * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  8. *
  9. * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
  10. * Xianghua Xiao (X.Xiao@motorola.com)
  11. */
  12. #include <common.h>
  13. #include <irq_func.h>
  14. #include <time.h>
  15. #include <watchdog.h>
  16. #include <command.h>
  17. #include <asm/processor.h>
  18. #include <asm/io.h>
  19. #ifdef CONFIG_POST
  20. #include <post.h>
  21. #endif
  22. void interrupt_init_cpu(unsigned *decrementer_count)
  23. {
  24. ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
  25. #ifdef CONFIG_POST
  26. /*
  27. * The POST word is stored in the PIC's TFRR register which gets
  28. * cleared when the PIC is reset. Save it off so we can restore it
  29. * later.
  30. */
  31. ulong post_word = post_word_load();
  32. #endif
  33. out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
  34. while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
  35. ;
  36. out_be32(&pic->gcr, MPC85xx_PICGCR_M);
  37. in_be32(&pic->gcr);
  38. *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  39. /* PIE is same as DIE, dec interrupt enable */
  40. mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
  41. #ifdef CONFIG_INTERRUPTS
  42. pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
  43. debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
  44. pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
  45. debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
  46. pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
  47. debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
  48. #ifdef CONFIG_PCI1
  49. pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
  50. debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
  51. #endif
  52. #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
  53. pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
  54. debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
  55. #endif
  56. #ifdef CONFIG_PCIE1
  57. pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
  58. debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
  59. #endif
  60. #ifdef CONFIG_PCIE3
  61. pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
  62. debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
  63. #endif
  64. pic->ctpr=0; /* 40080 clear current task priority register */
  65. #endif
  66. #ifdef CONFIG_POST
  67. post_word_store(post_word);
  68. #endif
  69. }
  70. /* Install and free a interrupt handler. Not implemented yet. */
  71. void
  72. irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  73. {
  74. return;
  75. }
  76. void
  77. irq_free_handler(int vec)
  78. {
  79. return;
  80. }
  81. void timer_interrupt_cpu(struct pt_regs *regs)
  82. {
  83. /* PIS is same as DIS, dec interrupt status */
  84. mtspr(SPRN_TSR, TSR_PIS);
  85. }
  86. #if defined(CONFIG_CMD_IRQ)
  87. /* irqinfo - print information about PCI devices,not implemented. */
  88. int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  89. {
  90. return 0;
  91. }
  92. #endif