cpu_init_early.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc
  4. */
  5. #include <common.h>
  6. #include <asm/processor.h>
  7. #include <asm/mmu.h>
  8. #include <asm/fsl_law.h>
  9. #include <asm/io.h>
  10. DECLARE_GLOBAL_DATA_PTR;
  11. #ifdef CONFIG_A003399_NOR_WORKAROUND
  12. void setup_ifc(void)
  13. {
  14. struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  15. u32 _mas0, _mas1, _mas2, _mas3, _mas7;
  16. phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
  17. /*
  18. * Adjust the TLB we were running out of to match the phys addr of the
  19. * chip select we are adjusting and will return to.
  20. */
  21. flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
  22. _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
  23. _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
  24. MAS1_TSIZE(BOOKE_PAGESZ_4M);
  25. _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
  26. _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
  27. _mas7 = FSL_BOOKE_MAS7(flash_phys);
  28. mtspr(MAS0, _mas0);
  29. mtspr(MAS1, _mas1);
  30. mtspr(MAS2, _mas2);
  31. mtspr(MAS3, _mas3);
  32. mtspr(MAS7, _mas7);
  33. asm volatile("isync;msync;tlbwe;isync");
  34. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
  35. /*
  36. * TLB entry for debuggging in AS1
  37. * Create temporary TLB entry in AS0 to handle debug exception
  38. * As on debug exception MSR is cleared i.e. Address space is changed
  39. * to 0. A TLB entry (in AS0) is required to handle debug exception generated
  40. * in AS1.
  41. *
  42. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  43. * bacause flash's physical address is going to change as
  44. * CONFIG_SYS_FLASH_BASE_PHYS.
  45. */
  46. _mas0 = MAS0_TLBSEL(1) |
  47. MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
  48. _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
  49. MAS1_TSIZE(BOOKE_PAGESZ_4M);
  50. _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
  51. _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
  52. _mas7 = FSL_BOOKE_MAS7(flash_phys);
  53. mtspr(MAS0, _mas0);
  54. mtspr(MAS1, _mas1);
  55. mtspr(MAS2, _mas2);
  56. mtspr(MAS3, _mas3);
  57. mtspr(MAS7, _mas7);
  58. asm volatile("isync;msync;tlbwe;isync");
  59. #endif
  60. /* Change flash's physical address */
  61. ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
  62. ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
  63. ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
  64. return ;
  65. }
  66. #endif
  67. /* We run cpu_init_early_f in AS = 1 */
  68. void cpu_init_early_f(void *fdt)
  69. {
  70. u32 mas0, mas1, mas2, mas3, mas7;
  71. #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  72. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  73. #endif
  74. #ifdef CONFIG_A003399_NOR_WORKAROUND
  75. ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  76. u32 *dst, *src;
  77. void (*setup_ifc_sram)(void);
  78. int i;
  79. #endif
  80. /* Pointer is writable since we allocated a register for it */
  81. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  82. /* gd area was zeroed during startup */
  83. #ifdef CONFIG_ARCH_QEMU_E500
  84. /*
  85. * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
  86. * so we need to populate it before it accesses it.
  87. */
  88. gd->fdt_blob = fdt;
  89. #endif
  90. mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
  91. mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
  92. mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
  93. mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
  94. mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
  95. write_tlb(mas0, mas1, mas2, mas3, mas7);
  96. /*
  97. * Work Around for IFC Erratum A-003549. This issue is P1010
  98. * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
  99. * Hence specifically selecting CS3.
  100. */
  101. #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  102. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
  103. #endif
  104. init_laws();
  105. /*
  106. * Work Around for IFC Erratum A003399, issue will hit only when execution
  107. * from NOR Flash
  108. */
  109. #ifdef CONFIG_A003399_NOR_WORKAROUND
  110. #define SRAM_BASE_ADDR (0x00000000)
  111. /* TLB for SRAM */
  112. mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
  113. mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
  114. MAS1_TSIZE(BOOKE_PAGESZ_1M);
  115. mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
  116. mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
  117. mas7 = FSL_BOOKE_MAS7(0);
  118. write_tlb(mas0, mas1, mas2, mas3, mas7);
  119. out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
  120. out_be32(&l2cache->l2errdis,
  121. (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
  122. out_be32(&l2cache->l2ctl,
  123. (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
  124. /*
  125. * Copy the code in setup_ifc to L2SRAM. Do a word copy
  126. * because NOR Flash on P1010 does not support byte
  127. * access (Erratum IFC-A002769)
  128. */
  129. setup_ifc_sram = (void *)SRAM_BASE_ADDR;
  130. dst = (u32 *) SRAM_BASE_ADDR;
  131. src = (u32 *) setup_ifc;
  132. for (i = 0; i < 1024; i++) {
  133. /* cppcheck-suppress nullPointer */
  134. *dst++ = *src++;
  135. }
  136. /* cppcheck-suppress nullPointer */
  137. setup_ifc_sram();
  138. /* CLEANUP */
  139. clrbits_be32(&l2cache->l2ctl,
  140. (MPC85xx_L2CTL_L2E |
  141. MPC85xx_L2CTL_L2SRAM_ENTIRE));
  142. out_be32(&l2cache->l2srbar0, 0x0);
  143. #endif
  144. invalidate_tlb(1);
  145. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
  146. !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
  147. !defined(CONFIG_NAND_SPL)
  148. disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
  149. #endif
  150. init_tlbs();
  151. }