cpu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  4. * (C) Copyright 2002, 2003 Motorola Inc.
  5. * Xianghua Xiao (X.Xiao@motorola.com)
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <init.h>
  14. #include <irq_func.h>
  15. #include <time.h>
  16. #include <vsprintf.h>
  17. #include <watchdog.h>
  18. #include <command.h>
  19. #include <fsl_esdhc.h>
  20. #include <asm/cache.h>
  21. #include <asm/io.h>
  22. #include <asm/mmu.h>
  23. #include <fsl_ifc.h>
  24. #include <asm/fsl_law.h>
  25. #include <asm/fsl_lbc.h>
  26. #include <post.h>
  27. #include <asm/processor.h>
  28. #include <fsl_ddr_sdram.h>
  29. #include <asm/ppc.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. /*
  32. * Default board reset function
  33. */
  34. static void
  35. __board_reset(void)
  36. {
  37. /* Do nothing */
  38. }
  39. void board_reset(void) __attribute__((weak, alias("__board_reset")));
  40. int checkcpu (void)
  41. {
  42. sys_info_t sysinfo;
  43. uint pvr, svr;
  44. uint ver;
  45. uint major, minor;
  46. struct cpu_type *cpu;
  47. char buf1[32], buf2[32];
  48. #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
  49. ccsr_gur_t __iomem *gur =
  50. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  51. #endif
  52. /*
  53. * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
  54. * mode. Previous platform use ddr ratio to do the same. This
  55. * information is only for display here.
  56. */
  57. #ifdef CONFIG_FSL_CORENET
  58. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  59. u32 ddr_sync = 0; /* only async mode is supported */
  60. #else
  61. u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
  62. >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
  63. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  64. #else /* CONFIG_FSL_CORENET */
  65. #ifdef CONFIG_DDR_CLK_FREQ
  66. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  67. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  68. #else
  69. u32 ddr_ratio = 0;
  70. #endif /* CONFIG_DDR_CLK_FREQ */
  71. #endif /* CONFIG_FSL_CORENET */
  72. unsigned int i, core, nr_cores = cpu_numcores();
  73. u32 mask = cpu_mask();
  74. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  75. unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
  76. u32 dsp_mask = cpu_dsp_mask();
  77. #endif
  78. svr = get_svr();
  79. major = SVR_MAJ(svr);
  80. minor = SVR_MIN(svr);
  81. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  82. if (SVR_SOC_VER(svr) == SVR_T4080) {
  83. ccsr_rcpm_t *rcpm =
  84. (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  85. setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
  86. FSL_CORENET_DEVDISR2_DTSEC1_9);
  87. setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
  88. setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
  89. /* It needs SW to disable core4~7 as HW design sake on T4080 */
  90. for (i = 4; i < 8; i++)
  91. cpu_disable(i);
  92. /* request core4~7 into PH20 state, prior to entering PCL10
  93. * state, all cores in cluster should be placed in PH20 state.
  94. */
  95. setbits_be32(&rcpm->pcph20setr, 0xf0);
  96. /* put the 2nd cluster into PCL10 state */
  97. setbits_be32(&rcpm->clpcl10setr, 1 << 1);
  98. }
  99. #endif
  100. if (cpu_numcores() > 1) {
  101. #ifndef CONFIG_MP
  102. puts("Unicore software on multiprocessor system!!\n"
  103. "To enable mutlticore build define CONFIG_MP\n");
  104. #endif
  105. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  106. printf("CPU%d: ", pic->whoami);
  107. } else {
  108. puts("CPU: ");
  109. }
  110. cpu = gd->arch.cpu;
  111. puts(cpu->name);
  112. if (IS_E_PROCESSOR(svr))
  113. puts("E");
  114. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  115. pvr = get_pvr();
  116. ver = PVR_VER(pvr);
  117. major = PVR_MAJ(pvr);
  118. minor = PVR_MIN(pvr);
  119. printf("Core: ");
  120. switch(ver) {
  121. case PVR_VER_E500_V1:
  122. case PVR_VER_E500_V2:
  123. puts("e500");
  124. break;
  125. case PVR_VER_E500MC:
  126. puts("e500mc");
  127. break;
  128. case PVR_VER_E5500:
  129. puts("e5500");
  130. break;
  131. case PVR_VER_E6500:
  132. puts("e6500");
  133. break;
  134. default:
  135. puts("Unknown");
  136. break;
  137. }
  138. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  139. if (nr_cores > CONFIG_MAX_CPUS) {
  140. panic("\nUnexpected number of cores: %d, max is %d\n",
  141. nr_cores, CONFIG_MAX_CPUS);
  142. }
  143. get_sys_info(&sysinfo);
  144. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  145. if (sysinfo.diff_sysclk == 1)
  146. puts("Single Source Clock Configuration\n");
  147. #endif
  148. puts("Clock Configuration:");
  149. for_each_cpu(i, core, nr_cores, mask) {
  150. if (!(i & 3))
  151. printf ("\n ");
  152. printf("CPU%d:%-4s MHz, ", core,
  153. strmhz(buf1, sysinfo.freq_processor[core]));
  154. }
  155. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  156. for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
  157. if (!(j & 3))
  158. printf("\n ");
  159. printf("DSP CPU%d:%-4s MHz, ", j,
  160. strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
  161. }
  162. #endif
  163. printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
  164. printf("\n");
  165. #ifdef CONFIG_FSL_CORENET
  166. if (ddr_sync == 1) {
  167. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  168. "(Synchronous), ",
  169. strmhz(buf1, sysinfo.freq_ddrbus/2),
  170. strmhz(buf2, sysinfo.freq_ddrbus));
  171. } else {
  172. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  173. "(Asynchronous), ",
  174. strmhz(buf1, sysinfo.freq_ddrbus/2),
  175. strmhz(buf2, sysinfo.freq_ddrbus));
  176. }
  177. #else
  178. switch (ddr_ratio) {
  179. case 0x0:
  180. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  181. strmhz(buf1, sysinfo.freq_ddrbus/2),
  182. strmhz(buf2, sysinfo.freq_ddrbus));
  183. break;
  184. case 0x7:
  185. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  186. "(Synchronous), ",
  187. strmhz(buf1, sysinfo.freq_ddrbus/2),
  188. strmhz(buf2, sysinfo.freq_ddrbus));
  189. break;
  190. default:
  191. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  192. "(Asynchronous), ",
  193. strmhz(buf1, sysinfo.freq_ddrbus/2),
  194. strmhz(buf2, sysinfo.freq_ddrbus));
  195. break;
  196. }
  197. #endif
  198. #if defined(CONFIG_FSL_LBC)
  199. if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  200. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  201. } else {
  202. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  203. sysinfo.freq_localbus);
  204. }
  205. #endif
  206. #if defined(CONFIG_FSL_IFC)
  207. printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  208. #endif
  209. #ifdef CONFIG_CPM2
  210. printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  211. #endif
  212. #ifdef CONFIG_QE
  213. printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
  214. #endif
  215. #if defined(CONFIG_SYS_CPRI)
  216. printf(" ");
  217. printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
  218. #endif
  219. #if defined(CONFIG_SYS_MAPLE)
  220. printf("\n ");
  221. printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
  222. printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
  223. printf("MAPLE-eTVPE:%-4s MHz\n",
  224. strmhz(buf1, sysinfo.freq_maple_etvpe));
  225. #endif
  226. #ifdef CONFIG_SYS_DPAA_FMAN
  227. for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
  228. printf(" FMAN%d: %s MHz\n", i + 1,
  229. strmhz(buf1, sysinfo.freq_fman[i]));
  230. }
  231. #endif
  232. #ifdef CONFIG_SYS_DPAA_QBMAN
  233. printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
  234. #endif
  235. #ifdef CONFIG_SYS_DPAA_PME
  236. printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
  237. #endif
  238. puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
  239. #ifdef CONFIG_FSL_CORENET
  240. /* Display the RCW, so that no one gets confused as to what RCW
  241. * we're actually using for this boot.
  242. */
  243. puts("Reset Configuration Word (RCW):");
  244. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  245. u32 rcw = in_be32(&gur->rcwsr[i]);
  246. if ((i % 4) == 0)
  247. printf("\n %08x:", i * 4);
  248. printf(" %08x", rcw);
  249. }
  250. puts("\n");
  251. #endif
  252. return 0;
  253. }
  254. /* ------------------------------------------------------------------------- */
  255. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  256. {
  257. /* Everything after the first generation of PQ3 parts has RSTCR */
  258. #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
  259. defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
  260. unsigned long val, msr;
  261. /*
  262. * Initiate hard reset in debug control register DBCR0
  263. * Make sure MSR[DE] = 1. This only resets the core.
  264. */
  265. msr = mfmsr ();
  266. msr |= MSR_DE;
  267. mtmsr (msr);
  268. val = mfspr(DBCR0);
  269. val |= 0x70000000;
  270. mtspr(DBCR0,val);
  271. #else
  272. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  273. /* Attempt board-specific reset */
  274. board_reset();
  275. /* Next try asserting HRESET_REQ */
  276. out_be32(&gur->rstcr, 0x2);
  277. udelay(100);
  278. #endif
  279. return 1;
  280. }
  281. /*
  282. * Get timebase clock frequency
  283. */
  284. #ifndef CONFIG_SYS_FSL_TBCLK_DIV
  285. #define CONFIG_SYS_FSL_TBCLK_DIV 8
  286. #endif
  287. __weak unsigned long get_tbclk(void)
  288. {
  289. unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
  290. return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
  291. }
  292. #if defined(CONFIG_WATCHDOG)
  293. #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
  294. void
  295. init_85xx_watchdog(void)
  296. {
  297. mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
  298. TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
  299. }
  300. void
  301. reset_85xx_watchdog(void)
  302. {
  303. /*
  304. * Clear TSR(WIS) bit by writing 1
  305. */
  306. mtspr(SPRN_TSR, TSR_WIS);
  307. }
  308. void
  309. watchdog_reset(void)
  310. {
  311. int re_enable = disable_interrupts();
  312. reset_85xx_watchdog();
  313. if (re_enable)
  314. enable_interrupts();
  315. }
  316. #endif /* CONFIG_WATCHDOG */
  317. /*
  318. * Initializes on-chip MMC controllers.
  319. * to override, implement board_mmc_init()
  320. */
  321. int cpu_mmc_init(bd_t *bis)
  322. {
  323. #ifdef CONFIG_FSL_ESDHC
  324. return fsl_esdhc_mmc_init(bis);
  325. #else
  326. return 0;
  327. #endif
  328. }
  329. /*
  330. * Print out the state of various machine registers.
  331. * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
  332. * parameters for IFC and TLBs
  333. */
  334. void print_reginfo(void)
  335. {
  336. print_tlbcam();
  337. print_laws();
  338. #if defined(CONFIG_FSL_LBC)
  339. print_lbc_regs();
  340. #endif
  341. #ifdef CONFIG_FSL_IFC
  342. print_ifc_regs();
  343. #endif
  344. }
  345. /* Common ddr init for non-corenet fsl 85xx platforms */
  346. #ifndef CONFIG_FSL_CORENET
  347. #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
  348. !defined(CONFIG_SYS_INIT_L2_ADDR)
  349. int dram_init(void)
  350. {
  351. #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
  352. defined(CONFIG_ARCH_QEMU_E500)
  353. gd->ram_size = fsl_ddr_sdram_size();
  354. #else
  355. gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  356. #endif
  357. return 0;
  358. }
  359. #else /* CONFIG_SYS_RAMBOOT */
  360. int dram_init(void)
  361. {
  362. phys_size_t dram_size = 0;
  363. #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
  364. {
  365. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  366. unsigned int x = 10;
  367. unsigned int i;
  368. /*
  369. * Work around to stabilize DDR DLL
  370. */
  371. out_be32(&gur->ddrdllcr, 0x81000000);
  372. asm("sync;isync;msync");
  373. udelay(200);
  374. while (in_be32(&gur->ddrdllcr) != 0x81000100) {
  375. setbits_be32(&gur->devdisr, 0x00010000);
  376. for (i = 0; i < x; i++)
  377. ;
  378. clrbits_be32(&gur->devdisr, 0x00010000);
  379. x++;
  380. }
  381. }
  382. #endif
  383. #if defined(CONFIG_SPD_EEPROM) || \
  384. defined(CONFIG_DDR_SPD) || \
  385. defined(CONFIG_SYS_DDR_RAW_TIMING)
  386. dram_size = fsl_ddr_sdram();
  387. #else
  388. dram_size = fixed_sdram();
  389. #endif
  390. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  391. dram_size *= 0x100000;
  392. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  393. /*
  394. * Initialize and enable DDR ECC.
  395. */
  396. ddr_enable_ecc(dram_size);
  397. #endif
  398. #if defined(CONFIG_FSL_LBC)
  399. /* Some boards also have sdram on the lbc */
  400. lbc_sdram_init();
  401. #endif
  402. debug("DDR: ");
  403. gd->ram_size = dram_size;
  404. return 0;
  405. }
  406. #endif /* CONFIG_SYS_RAMBOOT */
  407. #endif
  408. #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
  409. /* Board-specific functions defined in each board's ddr.c */
  410. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  411. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  412. void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
  413. phys_addr_t *rpn);
  414. unsigned int
  415. setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  416. void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  417. static void dump_spd_ddr_reg(void)
  418. {
  419. int i, j, k, m;
  420. u8 *p_8;
  421. u32 *p_32;
  422. struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
  423. generic_spd_eeprom_t
  424. spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
  425. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
  426. fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
  427. puts("SPD data of all dimms (zero value is omitted)...\n");
  428. puts("Byte (hex) ");
  429. k = 1;
  430. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  431. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
  432. printf("Dimm%d ", k++);
  433. }
  434. puts("\n");
  435. for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
  436. m = 0;
  437. printf("%3d (0x%02x) ", k, k);
  438. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  439. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  440. p_8 = (u8 *) &spd[i][j];
  441. if (p_8[k]) {
  442. printf("0x%02x ", p_8[k]);
  443. m++;
  444. } else
  445. puts(" ");
  446. }
  447. }
  448. if (m)
  449. puts("\n");
  450. else
  451. puts("\r");
  452. }
  453. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  454. switch (i) {
  455. case 0:
  456. ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  457. break;
  458. #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  459. case 1:
  460. ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  461. break;
  462. #endif
  463. #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  464. case 2:
  465. ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  466. break;
  467. #endif
  468. #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  469. case 3:
  470. ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  471. break;
  472. #endif
  473. default:
  474. printf("%s unexpected controller number = %u\n",
  475. __func__, i);
  476. return;
  477. }
  478. }
  479. printf("DDR registers dump for all controllers "
  480. "(zero value is omitted)...\n");
  481. puts("Offset (hex) ");
  482. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
  483. printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
  484. puts("\n");
  485. for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
  486. m = 0;
  487. printf("%6d (0x%04x)", k * 4, k * 4);
  488. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  489. p_32 = (u32 *) ddr[i];
  490. if (p_32[k]) {
  491. printf(" 0x%08x", p_32[k]);
  492. m++;
  493. } else
  494. puts(" ");
  495. }
  496. if (m)
  497. puts("\n");
  498. else
  499. puts("\r");
  500. }
  501. puts("\n");
  502. }
  503. /* invalid the TLBs for DDR and setup new ones to cover p_addr */
  504. static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
  505. {
  506. u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  507. unsigned long epn;
  508. u32 tsize, valid, ptr;
  509. int ddr_esel;
  510. clear_ddr_tlbs_phys(p_addr, size>>20);
  511. /* Setup new tlb to cover the physical address */
  512. setup_ddr_tlbs_phys(p_addr, size>>20);
  513. ptr = vstart;
  514. ddr_esel = find_tlb_idx((void *)ptr, 1);
  515. if (ddr_esel != -1) {
  516. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
  517. } else {
  518. printf("TLB error in function %s\n", __func__);
  519. return -1;
  520. }
  521. return 0;
  522. }
  523. /*
  524. * slide the testing window up to test another area
  525. * for 32_bit system, the maximum testable memory is limited to
  526. * CONFIG_MAX_MEM_MAPPED
  527. */
  528. int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  529. {
  530. phys_addr_t test_cap, p_addr;
  531. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  532. #if !defined(CONFIG_PHYS_64BIT) || \
  533. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  534. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  535. test_cap = p_size;
  536. #else
  537. test_cap = gd->ram_size;
  538. #endif
  539. p_addr = (*vstart) + (*size) + (*phys_offset);
  540. if (p_addr < test_cap - 1) {
  541. p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
  542. if (reset_tlb(p_addr, p_size, phys_offset) == -1)
  543. return -1;
  544. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  545. *size = (u32) p_size;
  546. printf("Testing 0x%08llx - 0x%08llx\n",
  547. (u64)(*vstart) + (*phys_offset),
  548. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  549. } else
  550. return 1;
  551. return 0;
  552. }
  553. /* initialization for testing area */
  554. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  555. {
  556. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  557. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  558. *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
  559. *phys_offset = 0;
  560. #if !defined(CONFIG_PHYS_64BIT) || \
  561. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  562. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  563. if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  564. puts("Cannot test more than ");
  565. print_size(CONFIG_MAX_MEM_MAPPED,
  566. " without proper 36BIT support.\n");
  567. }
  568. #endif
  569. printf("Testing 0x%08llx - 0x%08llx\n",
  570. (u64)(*vstart) + (*phys_offset),
  571. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  572. return 0;
  573. }
  574. /* invalid TLBs for DDR and remap as normal after testing */
  575. int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  576. {
  577. unsigned long epn;
  578. u32 tsize, valid, ptr;
  579. phys_addr_t rpn = 0;
  580. int ddr_esel;
  581. /* disable the TLBs for this testing */
  582. ptr = *vstart;
  583. while (ptr < (*vstart) + (*size)) {
  584. ddr_esel = find_tlb_idx((void *)ptr, 1);
  585. if (ddr_esel != -1) {
  586. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
  587. disable_tlb(ddr_esel);
  588. }
  589. ptr += TSIZE_TO_BYTES(tsize);
  590. }
  591. puts("Remap DDR ");
  592. setup_ddr_tlbs(gd->ram_size>>20);
  593. puts("\n");
  594. return 0;
  595. }
  596. void arch_memory_failure_handle(void)
  597. {
  598. dump_spd_ddr_reg();
  599. }
  600. #endif