speed.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  7. */
  8. #ifndef CONFIG_CLK_MPC83XX
  9. #include <common.h>
  10. #include <clock_legacy.h>
  11. #include <mpc83xx.h>
  12. #include <command.h>
  13. #include <vsprintf.h>
  14. #include <asm/processor.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* ----------------------------------------------------------------- */
  17. typedef enum {
  18. _unk,
  19. _off,
  20. _byp,
  21. _x8,
  22. _x4,
  23. _x2,
  24. _x1,
  25. _1x,
  26. _1_5x,
  27. _2x,
  28. _2_5x,
  29. _3x
  30. } mult_t;
  31. typedef struct {
  32. mult_t core_csb_ratio;
  33. mult_t vco_divider;
  34. } corecnf_t;
  35. static corecnf_t corecnf_tab[] = {
  36. {_byp, _byp}, /* 0x00 */
  37. {_byp, _byp}, /* 0x01 */
  38. {_byp, _byp}, /* 0x02 */
  39. {_byp, _byp}, /* 0x03 */
  40. {_byp, _byp}, /* 0x04 */
  41. {_byp, _byp}, /* 0x05 */
  42. {_byp, _byp}, /* 0x06 */
  43. {_byp, _byp}, /* 0x07 */
  44. {_1x, _x2}, /* 0x08 */
  45. {_1x, _x4}, /* 0x09 */
  46. {_1x, _x8}, /* 0x0A */
  47. {_1x, _x8}, /* 0x0B */
  48. {_1_5x, _x2}, /* 0x0C */
  49. {_1_5x, _x4}, /* 0x0D */
  50. {_1_5x, _x8}, /* 0x0E */
  51. {_1_5x, _x8}, /* 0x0F */
  52. {_2x, _x2}, /* 0x10 */
  53. {_2x, _x4}, /* 0x11 */
  54. {_2x, _x8}, /* 0x12 */
  55. {_2x, _x8}, /* 0x13 */
  56. {_2_5x, _x2}, /* 0x14 */
  57. {_2_5x, _x4}, /* 0x15 */
  58. {_2_5x, _x8}, /* 0x16 */
  59. {_2_5x, _x8}, /* 0x17 */
  60. {_3x, _x2}, /* 0x18 */
  61. {_3x, _x4}, /* 0x19 */
  62. {_3x, _x8}, /* 0x1A */
  63. {_3x, _x8}, /* 0x1B */
  64. };
  65. /* ----------------------------------------------------------------- */
  66. /*
  67. *
  68. */
  69. int get_clocks(void)
  70. {
  71. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  72. u32 pci_sync_in;
  73. u8 spmf;
  74. u8 clkin_div;
  75. u32 sccr;
  76. u32 corecnf_tab_index;
  77. u8 corepll;
  78. u32 lcrr;
  79. u32 csb_clk;
  80. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  81. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
  82. u32 tsec1_clk;
  83. u32 tsec2_clk;
  84. u32 usbdr_clk;
  85. #elif defined(CONFIG_ARCH_MPC8309)
  86. u32 usbdr_clk;
  87. #endif
  88. #ifdef CONFIG_ARCH_MPC834X
  89. u32 usbmph_clk;
  90. #endif
  91. u32 core_clk;
  92. u32 i2c1_clk;
  93. #if !defined(CONFIG_ARCH_MPC832X)
  94. u32 i2c2_clk;
  95. #endif
  96. #if defined(CONFIG_ARCH_MPC8315)
  97. u32 tdm_clk;
  98. #endif
  99. #if defined(CONFIG_FSL_ESDHC)
  100. u32 sdhc_clk;
  101. #endif
  102. #if !defined(CONFIG_ARCH_MPC8309)
  103. u32 enc_clk;
  104. #endif
  105. u32 lbiu_clk;
  106. u32 lclk_clk;
  107. u32 mem_clk;
  108. #if defined(CONFIG_ARCH_MPC8360)
  109. u32 mem_sec_clk;
  110. #endif
  111. #if defined(CONFIG_QE)
  112. u32 qepmf;
  113. u32 qepdf;
  114. u32 qe_clk;
  115. u32 brg_clk;
  116. #endif
  117. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  118. defined(CONFIG_ARCH_MPC837X)
  119. u32 pciexp1_clk;
  120. u32 pciexp2_clk;
  121. #endif
  122. #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
  123. u32 sata_clk;
  124. #endif
  125. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  126. return -1;
  127. clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
  128. if (im->reset.rcwh & HRCWH_PCI_HOST) {
  129. #if defined(CONFIG_SYS_CLK_FREQ)
  130. pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
  131. #else
  132. pci_sync_in = 0xDEADBEEF;
  133. #endif
  134. } else {
  135. #if defined(CONFIG_83XX_PCICLK)
  136. pci_sync_in = CONFIG_83XX_PCICLK;
  137. #else
  138. pci_sync_in = 0xDEADBEEF;
  139. #endif
  140. }
  141. spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  142. csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
  143. sccr = im->clk.sccr;
  144. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  145. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
  146. switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
  147. case 0:
  148. tsec1_clk = 0;
  149. break;
  150. case 1:
  151. tsec1_clk = csb_clk;
  152. break;
  153. case 2:
  154. tsec1_clk = csb_clk / 2;
  155. break;
  156. case 3:
  157. tsec1_clk = csb_clk / 3;
  158. break;
  159. default:
  160. /* unknown SCCR_TSEC1CM value */
  161. return -2;
  162. }
  163. #endif
  164. #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
  165. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
  166. switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
  167. case 0:
  168. usbdr_clk = 0;
  169. break;
  170. case 1:
  171. usbdr_clk = csb_clk;
  172. break;
  173. case 2:
  174. usbdr_clk = csb_clk / 2;
  175. break;
  176. case 3:
  177. usbdr_clk = csb_clk / 3;
  178. break;
  179. default:
  180. /* unknown SCCR_USBDRCM value */
  181. return -3;
  182. }
  183. #endif
  184. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
  185. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
  186. switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
  187. case 0:
  188. tsec2_clk = 0;
  189. break;
  190. case 1:
  191. tsec2_clk = csb_clk;
  192. break;
  193. case 2:
  194. tsec2_clk = csb_clk / 2;
  195. break;
  196. case 3:
  197. tsec2_clk = csb_clk / 3;
  198. break;
  199. default:
  200. /* unknown SCCR_TSEC2CM value */
  201. return -4;
  202. }
  203. #elif defined(CONFIG_ARCH_MPC8313)
  204. tsec2_clk = tsec1_clk;
  205. if (!(sccr & SCCR_TSEC1ON))
  206. tsec1_clk = 0;
  207. if (!(sccr & SCCR_TSEC2ON))
  208. tsec2_clk = 0;
  209. #endif
  210. #if defined(CONFIG_ARCH_MPC834X)
  211. switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
  212. case 0:
  213. usbmph_clk = 0;
  214. break;
  215. case 1:
  216. usbmph_clk = csb_clk;
  217. break;
  218. case 2:
  219. usbmph_clk = csb_clk / 2;
  220. break;
  221. case 3:
  222. usbmph_clk = csb_clk / 3;
  223. break;
  224. default:
  225. /* unknown SCCR_USBMPHCM value */
  226. return -5;
  227. }
  228. if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
  229. /* if USB MPH clock is not disabled and
  230. * USB DR clock is not disabled then
  231. * USB MPH & USB DR must have the same rate
  232. */
  233. return -6;
  234. }
  235. #endif
  236. #if !defined(CONFIG_ARCH_MPC8309)
  237. switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
  238. case 0:
  239. enc_clk = 0;
  240. break;
  241. case 1:
  242. enc_clk = csb_clk;
  243. break;
  244. case 2:
  245. enc_clk = csb_clk / 2;
  246. break;
  247. case 3:
  248. enc_clk = csb_clk / 3;
  249. break;
  250. default:
  251. /* unknown SCCR_ENCCM value */
  252. return -7;
  253. }
  254. #endif
  255. #if defined(CONFIG_FSL_ESDHC)
  256. switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
  257. case 0:
  258. sdhc_clk = 0;
  259. break;
  260. case 1:
  261. sdhc_clk = csb_clk;
  262. break;
  263. case 2:
  264. sdhc_clk = csb_clk / 2;
  265. break;
  266. case 3:
  267. sdhc_clk = csb_clk / 3;
  268. break;
  269. default:
  270. /* unknown SCCR_SDHCCM value */
  271. return -8;
  272. }
  273. #endif
  274. #if defined(CONFIG_ARCH_MPC8315)
  275. switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
  276. case 0:
  277. tdm_clk = 0;
  278. break;
  279. case 1:
  280. tdm_clk = csb_clk;
  281. break;
  282. case 2:
  283. tdm_clk = csb_clk / 2;
  284. break;
  285. case 3:
  286. tdm_clk = csb_clk / 3;
  287. break;
  288. default:
  289. /* unknown SCCR_TDMCM value */
  290. return -8;
  291. }
  292. #endif
  293. #if defined(CONFIG_ARCH_MPC834X)
  294. i2c1_clk = tsec2_clk;
  295. #elif defined(CONFIG_ARCH_MPC8360)
  296. i2c1_clk = csb_clk;
  297. #elif defined(CONFIG_ARCH_MPC832X)
  298. i2c1_clk = enc_clk;
  299. #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  300. i2c1_clk = enc_clk;
  301. #elif defined(CONFIG_FSL_ESDHC)
  302. i2c1_clk = sdhc_clk;
  303. #elif defined(CONFIG_ARCH_MPC837X)
  304. i2c1_clk = enc_clk;
  305. #elif defined(CONFIG_ARCH_MPC8309)
  306. i2c1_clk = csb_clk;
  307. #endif
  308. #if !defined(CONFIG_ARCH_MPC832X)
  309. i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
  310. #endif
  311. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  312. defined(CONFIG_ARCH_MPC837X)
  313. switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
  314. case 0:
  315. pciexp1_clk = 0;
  316. break;
  317. case 1:
  318. pciexp1_clk = csb_clk;
  319. break;
  320. case 2:
  321. pciexp1_clk = csb_clk / 2;
  322. break;
  323. case 3:
  324. pciexp1_clk = csb_clk / 3;
  325. break;
  326. default:
  327. /* unknown SCCR_PCIEXP1CM value */
  328. return -9;
  329. }
  330. switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
  331. case 0:
  332. pciexp2_clk = 0;
  333. break;
  334. case 1:
  335. pciexp2_clk = csb_clk;
  336. break;
  337. case 2:
  338. pciexp2_clk = csb_clk / 2;
  339. break;
  340. case 3:
  341. pciexp2_clk = csb_clk / 3;
  342. break;
  343. default:
  344. /* unknown SCCR_PCIEXP2CM value */
  345. return -10;
  346. }
  347. #endif
  348. #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
  349. switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
  350. case 0:
  351. sata_clk = 0;
  352. break;
  353. case 1:
  354. sata_clk = csb_clk;
  355. break;
  356. case 2:
  357. sata_clk = csb_clk / 2;
  358. break;
  359. case 3:
  360. sata_clk = csb_clk / 3;
  361. break;
  362. default:
  363. /* unknown SCCR_SATA1CM value */
  364. return -11;
  365. }
  366. #endif
  367. lbiu_clk = csb_clk *
  368. (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
  369. lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
  370. switch (lcrr) {
  371. case 2:
  372. case 4:
  373. case 8:
  374. lclk_clk = lbiu_clk / lcrr;
  375. break;
  376. default:
  377. /* unknown lcrr */
  378. return -12;
  379. }
  380. mem_clk = csb_clk *
  381. (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
  382. corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
  383. #if defined(CONFIG_ARCH_MPC8360)
  384. mem_sec_clk = csb_clk * (1 +
  385. ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
  386. #endif
  387. corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
  388. if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
  389. /* corecnf_tab_index is too high, possibly wrong value */
  390. return -11;
  391. }
  392. switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
  393. case _byp:
  394. case _x1:
  395. case _1x:
  396. core_clk = csb_clk;
  397. break;
  398. case _1_5x:
  399. core_clk = (3 * csb_clk) / 2;
  400. break;
  401. case _2x:
  402. core_clk = 2 * csb_clk;
  403. break;
  404. case _2_5x:
  405. core_clk = (5 * csb_clk) / 2;
  406. break;
  407. case _3x:
  408. core_clk = 3 * csb_clk;
  409. break;
  410. default:
  411. /* unknown core to csb ratio */
  412. return -13;
  413. }
  414. #if defined(CONFIG_QE)
  415. qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
  416. qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
  417. qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
  418. brg_clk = qe_clk / 2;
  419. #endif
  420. gd->arch.csb_clk = csb_clk;
  421. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  422. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
  423. gd->arch.tsec1_clk = tsec1_clk;
  424. gd->arch.tsec2_clk = tsec2_clk;
  425. gd->arch.usbdr_clk = usbdr_clk;
  426. #elif defined(CONFIG_ARCH_MPC8309)
  427. gd->arch.usbdr_clk = usbdr_clk;
  428. #endif
  429. #if defined(CONFIG_ARCH_MPC834X)
  430. gd->arch.usbmph_clk = usbmph_clk;
  431. #endif
  432. #if defined(CONFIG_ARCH_MPC8315)
  433. gd->arch.tdm_clk = tdm_clk;
  434. #endif
  435. #if defined(CONFIG_FSL_ESDHC)
  436. gd->arch.sdhc_clk = sdhc_clk;
  437. #endif
  438. gd->arch.core_clk = core_clk;
  439. gd->arch.i2c1_clk = i2c1_clk;
  440. #if !defined(CONFIG_ARCH_MPC832X)
  441. gd->arch.i2c2_clk = i2c2_clk;
  442. #endif
  443. #if !defined(CONFIG_ARCH_MPC8309)
  444. gd->arch.enc_clk = enc_clk;
  445. #endif
  446. gd->arch.lbiu_clk = lbiu_clk;
  447. gd->arch.lclk_clk = lclk_clk;
  448. gd->mem_clk = mem_clk;
  449. #if defined(CONFIG_ARCH_MPC8360)
  450. gd->arch.mem_sec_clk = mem_sec_clk;
  451. #endif
  452. #if defined(CONFIG_QE)
  453. gd->arch.qe_clk = qe_clk;
  454. gd->arch.brg_clk = brg_clk;
  455. #endif
  456. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  457. defined(CONFIG_ARCH_MPC837X)
  458. gd->arch.pciexp1_clk = pciexp1_clk;
  459. gd->arch.pciexp2_clk = pciexp2_clk;
  460. #endif
  461. #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
  462. gd->arch.sata_clk = sata_clk;
  463. #endif
  464. gd->pci_clk = pci_sync_in;
  465. gd->cpu_clk = gd->arch.core_clk;
  466. gd->bus_clk = gd->arch.csb_clk;
  467. return 0;
  468. }
  469. /********************************************
  470. * get_bus_freq
  471. * return system bus freq in Hz
  472. *********************************************/
  473. ulong get_bus_freq(ulong dummy)
  474. {
  475. return gd->arch.csb_clk;
  476. }
  477. /********************************************
  478. * get_ddr_freq
  479. * return ddr bus freq in Hz
  480. *********************************************/
  481. ulong get_ddr_freq(ulong dummy)
  482. {
  483. return gd->mem_clk;
  484. }
  485. int get_serial_clock(void)
  486. {
  487. return get_bus_freq(0);
  488. }
  489. static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
  490. char *const argv[])
  491. {
  492. char buf[32];
  493. printf("Clock configuration:\n");
  494. printf(" Core: %-4s MHz\n",
  495. strmhz(buf, gd->arch.core_clk));
  496. printf(" Coherent System Bus: %-4s MHz\n",
  497. strmhz(buf, gd->arch.csb_clk));
  498. #if defined(CONFIG_QE)
  499. printf(" QE: %-4s MHz\n",
  500. strmhz(buf, gd->arch.qe_clk));
  501. printf(" BRG: %-4s MHz\n",
  502. strmhz(buf, gd->arch.brg_clk));
  503. #endif
  504. printf(" Local Bus Controller:%-4s MHz\n",
  505. strmhz(buf, gd->arch.lbiu_clk));
  506. printf(" Local Bus: %-4s MHz\n",
  507. strmhz(buf, gd->arch.lclk_clk));
  508. printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
  509. #if defined(CONFIG_ARCH_MPC8360)
  510. printf(" DDR Secondary: %-4s MHz\n",
  511. strmhz(buf, gd->arch.mem_sec_clk));
  512. #endif
  513. #if !defined(CONFIG_ARCH_MPC8309)
  514. printf(" SEC: %-4s MHz\n",
  515. strmhz(buf, gd->arch.enc_clk));
  516. #endif
  517. printf(" I2C1: %-4s MHz\n",
  518. strmhz(buf, gd->arch.i2c1_clk));
  519. #if !defined(CONFIG_ARCH_MPC832X)
  520. printf(" I2C2: %-4s MHz\n",
  521. strmhz(buf, gd->arch.i2c2_clk));
  522. #endif
  523. #if defined(CONFIG_ARCH_MPC8315)
  524. printf(" TDM: %-4s MHz\n",
  525. strmhz(buf, gd->arch.tdm_clk));
  526. #endif
  527. #if defined(CONFIG_FSL_ESDHC)
  528. printf(" SDHC: %-4s MHz\n",
  529. strmhz(buf, gd->arch.sdhc_clk));
  530. #endif
  531. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  532. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
  533. printf(" TSEC1: %-4s MHz\n",
  534. strmhz(buf, gd->arch.tsec1_clk));
  535. printf(" TSEC2: %-4s MHz\n",
  536. strmhz(buf, gd->arch.tsec2_clk));
  537. printf(" USB DR: %-4s MHz\n",
  538. strmhz(buf, gd->arch.usbdr_clk));
  539. #elif defined(CONFIG_ARCH_MPC8309)
  540. printf(" USB DR: %-4s MHz\n",
  541. strmhz(buf, gd->arch.usbdr_clk));
  542. #endif
  543. #if defined(CONFIG_ARCH_MPC834X)
  544. printf(" USB MPH: %-4s MHz\n",
  545. strmhz(buf, gd->arch.usbmph_clk));
  546. #endif
  547. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  548. defined(CONFIG_ARCH_MPC837X)
  549. printf(" PCIEXP1: %-4s MHz\n",
  550. strmhz(buf, gd->arch.pciexp1_clk));
  551. printf(" PCIEXP2: %-4s MHz\n",
  552. strmhz(buf, gd->arch.pciexp2_clk));
  553. #endif
  554. #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
  555. printf(" SATA: %-4s MHz\n",
  556. strmhz(buf, gd->arch.sata_clk));
  557. #endif
  558. return 0;
  559. }
  560. U_BOOT_CMD(clocks, 1, 0, do_clocks,
  561. "print clock configuration",
  562. " clocks"
  563. );
  564. #endif