clk.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Marek Vasut <marex@denx.de>
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <command.h>
  8. #include <hang.h>
  9. #include <asm/io.h>
  10. #include <asm/addrspace.h>
  11. #include <asm/types.h>
  12. #include <mach/ar71xx_regs.h>
  13. #include <mach/ath79.h>
  14. #include <wait_bit.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /*
  17. * The math for calculating PLL:
  18. * NFRAC * 2^8
  19. * NINT + -------------
  20. * XTAL [MHz] 2^(18 - 1)
  21. * PLL [MHz] = ------------ * ----------------------
  22. * REFDIV 2^OUTDIV
  23. *
  24. * Unfortunatelly, there is no way to reliably compute the variables.
  25. * The vendor U-Boot port contains macros for various combinations of
  26. * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
  27. * in those numbers.
  28. */
  29. struct ar934x_pll_config {
  30. u8 range;
  31. u8 refdiv;
  32. u8 outdiv;
  33. /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
  34. u8 nint[2];
  35. };
  36. struct ar934x_clock_config {
  37. u16 cpu_freq;
  38. u16 ddr_freq;
  39. u16 ahb_freq;
  40. struct ar934x_pll_config cpu_pll;
  41. struct ar934x_pll_config ddr_pll;
  42. };
  43. static const struct ar934x_clock_config ar934x_clock_config[] = {
  44. { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
  45. { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
  46. { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
  47. { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
  48. { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
  49. { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
  50. { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
  51. { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
  52. { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
  53. { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
  54. { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
  55. { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
  56. { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
  57. { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
  58. { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
  59. { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
  60. { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
  61. { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
  62. { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
  63. { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
  64. { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
  65. { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
  66. { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
  67. { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
  68. { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
  69. { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
  70. { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
  71. { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
  72. };
  73. static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
  74. {
  75. u32 reg;
  76. do {
  77. writel(0x10810f00, pll_reg_base + 0x4);
  78. writel(srif_val, pll_reg_base + 0x0);
  79. writel(0xd0810f00, pll_reg_base + 0x4);
  80. writel(0x03000000, pll_reg_base + 0x8);
  81. writel(0xd0800f00, pll_reg_base + 0x4);
  82. clrbits_be32(pll_reg_base + 0x8, BIT(30));
  83. udelay(5);
  84. setbits_be32(pll_reg_base + 0x8, BIT(30));
  85. udelay(5);
  86. wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
  87. clrbits_be32(pll_reg_base + 0x8, BIT(30));
  88. udelay(5);
  89. /* Check if CPU SRIF PLL locked. */
  90. reg = readl(pll_reg_base + 0x8);
  91. reg = (reg & 0x7ffff8) >> 3;
  92. } while (reg >= 0x40000);
  93. }
  94. void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
  95. {
  96. void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
  97. AR934X_SRIF_SIZE, MAP_NOCACHE);
  98. void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
  99. AR71XX_PLL_SIZE, MAP_NOCACHE);
  100. const struct ar934x_pll_config *pll_cfg;
  101. int i, pll_nint, pll_refdiv, xtal_40 = 0;
  102. u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
  103. /* Configure SRIF PLL with initial values. */
  104. writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);
  105. writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);
  106. writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);
  107. writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);
  108. writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
  109. /* Test for 40MHz XTAL */
  110. reg = ath79_get_bootstrap();
  111. if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
  112. xtal_40 = 1;
  113. cpu_srif = 0x41c00000;
  114. ddr_srif = 0x41680000;
  115. } else {
  116. xtal_40 = 0;
  117. cpu_srif = 0x29c00000;
  118. ddr_srif = 0x29680000;
  119. }
  120. /* Locate CPU/DDR PLL configuration */
  121. for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {
  122. if (cpu_mhz != ar934x_clock_config[i].cpu_freq)
  123. continue;
  124. if (ddr_mhz != ar934x_clock_config[i].ddr_freq)
  125. continue;
  126. if (ahb_mhz != ar934x_clock_config[i].ahb_freq)
  127. continue;
  128. /* Entry found */
  129. pll_cfg = &ar934x_clock_config[i].cpu_pll;
  130. pll_nint = pll_cfg->nint[xtal_40];
  131. pll_refdiv = pll_cfg->refdiv;
  132. cpu_pll =
  133. (pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) |
  134. (pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) |
  135. (pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |
  136. (pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);
  137. pll_cfg = &ar934x_clock_config[i].ddr_pll;
  138. pll_nint = pll_cfg->nint[xtal_40];
  139. pll_refdiv = pll_cfg->refdiv;
  140. ddr_pll =
  141. (pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) |
  142. (pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) |
  143. (pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |
  144. (pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);
  145. break;
  146. }
  147. /* PLL configuration not found, hang. */
  148. if (i == ARRAY_SIZE(ar934x_clock_config))
  149. hang();
  150. /* Set PLL Bypass */
  151. setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
  152. AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
  153. setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
  154. AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
  155. setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
  156. AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
  157. /* Configure CPU PLL */
  158. writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD,
  159. pll_regs + AR934X_PLL_CPU_CONFIG_REG);
  160. /* Configure DDR PLL */
  161. writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD,
  162. pll_regs + AR934X_PLL_DDR_CONFIG_REG);
  163. /* Configure PLL routing */
  164. writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS |
  165. AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS |
  166. AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS |
  167. (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |
  168. (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |
  169. (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |
  170. AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL |
  171. AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL |
  172. AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL,
  173. pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
  174. /* Configure SRIF PLLs, which is completely undocumented :-) */
  175. ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif);
  176. ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif);
  177. /* Unset PLL Bypass */
  178. clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
  179. AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
  180. clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
  181. AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
  182. clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
  183. AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
  184. /* Enable PLL dithering */
  185. writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |
  186. (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),
  187. pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG);
  188. writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT,
  189. pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG);
  190. }
  191. static u32 ar934x_get_xtal(void)
  192. {
  193. u32 val;
  194. val = ath79_get_bootstrap();
  195. if (val & AR934X_BOOTSTRAP_REF_CLK_40)
  196. return 40000000;
  197. else
  198. return 25000000;
  199. }
  200. int get_serial_clock(void)
  201. {
  202. return ar934x_get_xtal();
  203. }
  204. static u32 ar934x_cpupll_to_hz(const u32 regval)
  205. {
  206. const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  207. AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
  208. const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  209. AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
  210. const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
  211. AR934X_PLL_CPU_CONFIG_NINT_MASK;
  212. const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  213. AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
  214. const u32 xtal = ar934x_get_xtal();
  215. return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
  216. }
  217. static u32 ar934x_ddrpll_to_hz(const u32 regval)
  218. {
  219. const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  220. AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
  221. const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  222. AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
  223. const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
  224. AR934X_PLL_DDR_CONFIG_NINT_MASK;
  225. const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  226. AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
  227. const u32 xtal = ar934x_get_xtal();
  228. return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
  229. }
  230. static void ar934x_update_clock(void)
  231. {
  232. void __iomem *regs;
  233. u32 ctrl, cpu, cpupll, ddr, ddrpll;
  234. u32 cpudiv, ddrdiv, busdiv;
  235. u32 cpuclk, ddrclk, busclk;
  236. regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
  237. MAP_NOCACHE);
  238. cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
  239. ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
  240. ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
  241. cpupll = ar934x_cpupll_to_hz(cpu);
  242. ddrpll = ar934x_ddrpll_to_hz(ddr);
  243. if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  244. cpuclk = ar934x_get_xtal();
  245. else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  246. cpuclk = cpupll;
  247. else
  248. cpuclk = ddrpll;
  249. if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  250. ddrclk = ar934x_get_xtal();
  251. else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
  252. ddrclk = ddrpll;
  253. else
  254. ddrclk = cpupll;
  255. if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  256. busclk = ar934x_get_xtal();
  257. else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  258. busclk = ddrpll;
  259. else
  260. busclk = cpupll;
  261. cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  262. AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  263. ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  264. AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  265. busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  266. AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  267. gd->cpu_clk = cpuclk / (cpudiv + 1);
  268. gd->mem_clk = ddrclk / (ddrdiv + 1);
  269. gd->bus_clk = busclk / (busdiv + 1);
  270. }
  271. ulong get_bus_freq(ulong dummy)
  272. {
  273. ar934x_update_clock();
  274. return gd->bus_clk;
  275. }
  276. ulong get_ddr_freq(ulong dummy)
  277. {
  278. ar934x_update_clock();
  279. return gd->mem_clk;
  280. }
  281. int do_ar934x_showclk(struct cmd_tbl *cmdtp, int flag, int argc,
  282. char *const argv[])
  283. {
  284. ar934x_update_clock();
  285. printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
  286. printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
  287. printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
  288. return 0;
  289. }
  290. U_BOOT_CMD(
  291. clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk,
  292. "display clocks",
  293. ""
  294. );