slicetimer.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  4. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <irq_func.h>
  9. #include <asm/timer.h>
  10. #include <asm/immap.h>
  11. #include <asm/io.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. static ulong timestamp;
  14. #if defined(CONFIG_SLTTMR)
  15. #ifndef CONFIG_SYS_UDELAY_BASE
  16. # error "uDelay base not defined!"
  17. #endif
  18. #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
  19. # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
  20. #endif
  21. extern void dtimer_intr_setup(void);
  22. void __udelay(unsigned long usec)
  23. {
  24. slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
  25. u32 now, freq;
  26. /* 1 us period */
  27. freq = CONFIG_SYS_TIMER_PRESCALER;
  28. /* Disable */
  29. out_be32(&timerp->cr, 0);
  30. out_be32(&timerp->tcnt, usec * freq);
  31. out_be32(&timerp->cr, SLT_CR_TEN);
  32. now = in_be32(&timerp->cnt);
  33. while (now != 0)
  34. now = in_be32(&timerp->cnt);
  35. setbits_be32(&timerp->sr, SLT_SR_ST);
  36. out_be32(&timerp->cr, 0);
  37. }
  38. void dtimer_interrupt(void *not_used)
  39. {
  40. slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
  41. /* check for timer interrupt asserted */
  42. if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
  43. setbits_be32(&timerp->sr, SLT_SR_ST);
  44. timestamp++;
  45. return;
  46. }
  47. }
  48. int timer_init(void)
  49. {
  50. slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
  51. timestamp = 0;
  52. /* disable timer */
  53. out_be32(&timerp->cr, 0);
  54. out_be32(&timerp->tcnt, 0);
  55. /* clear status */
  56. out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
  57. /* initialize and enable timer interrupt */
  58. irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
  59. /* Interrupt every ms */
  60. out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
  61. dtimer_intr_setup();
  62. /* set a period of 1us, set timer mode to restart and
  63. enable timer and interrupt */
  64. out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
  65. return 0;
  66. }
  67. ulong get_timer(ulong base)
  68. {
  69. return (timestamp - base);
  70. }
  71. #endif /* CONFIG_SLTTMR */