pci.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  4. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  5. */
  6. /*
  7. * PCI Configuration space access support
  8. */
  9. #include <common.h>
  10. #include <pci.h>
  11. #include <asm/io.h>
  12. #include <asm/immap.h>
  13. #if defined(CONFIG_PCI)
  14. /* System RAM mapped over PCI */
  15. #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
  16. #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  17. #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  18. #define cfg_read(val, addr, type, op) *val = op((type)(addr));
  19. #define cfg_write(val, addr, type, op) op((type *)(addr), (val));
  20. #define PCI_OP(rw, size, type, op, mask) \
  21. int pci_##rw##_cfg_##size(struct pci_controller *hose, \
  22. pci_dev_t dev, int offset, type val) \
  23. { \
  24. u32 addr = 0; \
  25. u16 cfg_type = 0; \
  26. addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
  27. out_be32(hose->cfg_addr, addr); \
  28. cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
  29. out_be32(hose->cfg_addr, addr & 0x7fffffff); \
  30. return 0; \
  31. }
  32. PCI_OP(read, byte, u8 *, in_8, 3)
  33. PCI_OP(read, word, u16 *, in_le16, 2)
  34. PCI_OP(read, dword, u32 *, in_le32, 0)
  35. PCI_OP(write, byte, u8, out_8, 3)
  36. PCI_OP(write, word, u16, out_le16, 2)
  37. PCI_OP(write, dword, u32, out_le32, 0)
  38. void pci_mcf5445x_init(struct pci_controller *hose)
  39. {
  40. pci_t *pci = (pci_t *)MMAP_PCI;
  41. pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
  42. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  43. u32 barEn = 0;
  44. out_be32(&pciarb->acr, 0x001f001f);
  45. /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
  46. PCIREQ2, PCIGNT2 */
  47. out_be16(&gpio->par_pci,
  48. GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
  49. GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
  50. GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
  51. GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
  52. /* Assert reset bit */
  53. setbits_be32(&pci->gscr, PCI_GSCR_PR);
  54. setbits_be32(&pci->tcr1, PCI_TCR1_P);
  55. /* Initiator windows */
  56. out_be32(&pci->iw0btar,
  57. CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
  58. out_be32(&pci->iw1btar,
  59. CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
  60. out_be32(&pci->iw2btar,
  61. CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
  62. out_be32(&pci->iwcr,
  63. PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
  64. PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
  65. out_be32(&pci->icr, 0);
  66. /* Enable bus master and mem access */
  67. out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
  68. /* Cache line size and master latency */
  69. out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
  70. out_be32(&pci->cr2, 0);
  71. #ifdef CONFIG_SYS_PCI_BAR0
  72. out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
  73. out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
  74. barEn |= PCI_TCR2_B0E;
  75. #endif
  76. #ifdef CONFIG_SYS_PCI_BAR1
  77. out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
  78. out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
  79. barEn |= PCI_TCR2_B1E;
  80. #endif
  81. #ifdef CONFIG_SYS_PCI_BAR2
  82. out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
  83. out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
  84. barEn |= PCI_TCR2_B2E;
  85. #endif
  86. #ifdef CONFIG_SYS_PCI_BAR3
  87. out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
  88. out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
  89. barEn |= PCI_TCR2_B3E;
  90. #endif
  91. #ifdef CONFIG_SYS_PCI_BAR4
  92. out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
  93. out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
  94. barEn |= PCI_TCR2_B4E;
  95. #endif
  96. #ifdef CONFIG_SYS_PCI_BAR5
  97. out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
  98. out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
  99. barEn |= PCI_TCR2_B5E;
  100. #endif
  101. out_be32(&pci->tcr2, barEn);
  102. /* Deassert reset bit */
  103. clrbits_be32(&pci->gscr, PCI_GSCR_PR);
  104. udelay(1000);
  105. /* Enable PCI bus master support */
  106. hose->first_busno = 0;
  107. hose->last_busno = 0xff;
  108. pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
  109. CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
  110. pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
  111. CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
  112. pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
  113. CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
  114. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  115. hose->region_count = 3;
  116. hose->cfg_addr = &(pci->car);
  117. hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
  118. pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
  119. pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
  120. pci_write_cfg_dword);
  121. /* Hose scan */
  122. pci_register_hose(hose);
  123. hose->last_busno = pci_hose_scan(hose);
  124. }
  125. #endif /* CONFIG_PCI */