speed.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. */
  10. #include <common.h>
  11. #include <clock_legacy.h>
  12. #include <asm/processor.h>
  13. #include <asm/immap.h>
  14. #include <asm/io.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* PLL min/max specifications */
  17. #define MAX_FVCO 500000 /* KHz */
  18. #define MAX_FSYS 80000 /* KHz */
  19. #define MIN_FSYS 58333 /* KHz */
  20. #ifdef CONFIG_MCF5301x
  21. #define FREF 20000 /* KHz */
  22. #define MAX_MFD 63 /* Multiplier */
  23. #define MIN_MFD 0 /* Multiplier */
  24. #define USBDIV 8
  25. /* Low Power Divider specifications */
  26. #define MIN_LPD (0) /* Divider (not encoded) */
  27. #define MAX_LPD (15) /* Divider (not encoded) */
  28. #define DEFAULT_LPD (0) /* Divider (not encoded) */
  29. #endif
  30. #ifdef CONFIG_MCF532x
  31. #define FREF 16000 /* KHz */
  32. #define MAX_MFD 135 /* Multiplier */
  33. #define MIN_MFD 88 /* Multiplier */
  34. /* Low Power Divider specifications */
  35. #define MIN_LPD (1 << 0) /* Divider (not encoded) */
  36. #define MAX_LPD (1 << 15) /* Divider (not encoded) */
  37. #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
  38. #endif
  39. #define BUSDIV 6 /* Divider */
  40. /* Get the value of the current system clock */
  41. int get_sys_clock(void)
  42. {
  43. ccm_t *ccm = (ccm_t *)(MMAP_CCM);
  44. pll_t *pll = (pll_t *)(MMAP_PLL);
  45. int divider;
  46. /* Test to see if device is in LIMP mode */
  47. if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
  48. divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
  49. #ifdef CONFIG_MCF5301x
  50. return (FREF / (3 * (1 << divider)));
  51. #endif
  52. #ifdef CONFIG_MCF532x
  53. return (FREF / (2 << divider));
  54. #endif
  55. } else {
  56. #ifdef CONFIG_MCF5301x
  57. u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
  58. u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
  59. u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
  60. return (((FREF * pfdr) / refdiv) / busdiv);
  61. #endif
  62. #ifdef CONFIG_MCF532x
  63. return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
  64. #endif
  65. }
  66. }
  67. /*
  68. * Initialize the Low Power Divider circuit
  69. *
  70. * Parameters:
  71. * div Desired system frequency divider
  72. *
  73. * Return Value:
  74. * The resulting output system frequency
  75. */
  76. int clock_limp(int div)
  77. {
  78. ccm_t *ccm = (ccm_t *)(MMAP_CCM);
  79. u32 temp;
  80. /* Check bounds of divider */
  81. if (div < MIN_LPD)
  82. div = MIN_LPD;
  83. if (div > MAX_LPD)
  84. div = MAX_LPD;
  85. /* Save of the current value of the SSIDIV so we don't overwrite the value */
  86. temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
  87. /* Apply the divider to the system clock */
  88. out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
  89. setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
  90. return (FREF / (3 * (1 << div)));
  91. }
  92. /* Exit low power LIMP mode */
  93. int clock_exit_limp(void)
  94. {
  95. ccm_t *ccm = (ccm_t *)(MMAP_CCM);
  96. int fout;
  97. /* Exit LIMP mode */
  98. clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
  99. /* Wait for PLL to lock */
  100. while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
  101. ;
  102. fout = get_sys_clock();
  103. return fout;
  104. }
  105. /* Initialize the PLL
  106. *
  107. * Parameters:
  108. * fref PLL reference clock frequency in KHz
  109. * fsys Desired PLL output frequency in KHz
  110. * flags Operating parameters
  111. *
  112. * Return Value:
  113. * The resulting output system frequency
  114. */
  115. int clock_pll(int fsys, int flags)
  116. {
  117. #ifdef CONFIG_MCF532x
  118. u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
  119. #endif
  120. sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
  121. pll_t *pll = (pll_t *)(MMAP_PLL);
  122. int fref, temp, fout, mfd;
  123. u32 i;
  124. fref = FREF;
  125. if (fsys == 0) {
  126. /* Return current PLL output */
  127. #ifdef CONFIG_MCF5301x
  128. u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
  129. mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
  130. return (fref * mfd) / busdiv;
  131. #endif
  132. #ifdef CONFIG_MCF532x
  133. mfd = in_8(&pll->pfdr);
  134. return (fref * mfd / (BUSDIV * 4));
  135. #endif
  136. }
  137. /* Check bounds of requested system clock */
  138. if (fsys > MAX_FSYS)
  139. fsys = MAX_FSYS;
  140. if (fsys < MIN_FSYS)
  141. fsys = MIN_FSYS;
  142. /*
  143. * Multiplying by 100 when calculating the temp value,
  144. * and then dividing by 100 to calculate the mfd allows
  145. * for exact values without needing to include floating
  146. * point libraries.
  147. */
  148. temp = (100 * fsys) / fref;
  149. #ifdef CONFIG_MCF5301x
  150. mfd = (BUSDIV * temp) / 100;
  151. /* Determine the output frequency for selected values */
  152. fout = ((fref * mfd) / BUSDIV);
  153. #endif
  154. #ifdef CONFIG_MCF532x
  155. mfd = (4 * BUSDIV * temp) / 100;
  156. /* Determine the output frequency for selected values */
  157. fout = ((fref * mfd) / (BUSDIV * 4));
  158. #endif
  159. /* must not tamper with SDRAMC if running from SDRAM */
  160. #if !defined(CONFIG_MONITOR_IS_IN_RAM)
  161. /*
  162. * Check to see if the SDRAM has already been initialized.
  163. * If it has then the SDRAM needs to be put into self refresh
  164. * mode before reprogramming the PLL.
  165. */
  166. if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
  167. clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
  168. /*
  169. * Initialize the PLL to generate the new system clock frequency.
  170. * The device must be put into LIMP mode to reprogram the PLL.
  171. */
  172. /* Enter LIMP mode */
  173. clock_limp(DEFAULT_LPD);
  174. #ifdef CONFIG_MCF5301x
  175. out_be32(&pll->pdr,
  176. PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
  177. PLL_PDR_OUTDIV2(BUSDIV - 1) |
  178. PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
  179. PLL_PDR_OUTDIV4(USBDIV - 1));
  180. clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
  181. setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
  182. #endif
  183. #ifdef CONFIG_MCF532x
  184. /* Reprogram PLL for desired fsys */
  185. out_8(&pll->podr,
  186. PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
  187. out_8(&pll->pfdr, mfd);
  188. #endif
  189. /* Exit LIMP mode */
  190. clock_exit_limp();
  191. /* Return the SDRAM to normal operation if it is in use. */
  192. if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
  193. setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
  194. #ifdef CONFIG_MCF532x
  195. /*
  196. * software workaround for SDRAM opeartion after exiting LIMP
  197. * mode errata
  198. */
  199. out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
  200. #endif
  201. /* wait for DQS logic to relock */
  202. for (i = 0; i < 0x200; i++) ;
  203. #endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
  204. return fout;
  205. }
  206. /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
  207. int get_clocks(void)
  208. {
  209. gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
  210. gd->cpu_clk = (gd->bus_clk * 3);
  211. #ifdef CONFIG_SYS_I2C_FSL
  212. gd->arch.i2c1_clk = gd->bus_clk;
  213. #endif
  214. return (0);
  215. }