cpu.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Josef Baumgartner <josef.baumgartner@telex.de>
  5. *
  6. * MCF5282 additionals
  7. * (C) Copyright 2005
  8. * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  9. *
  10. * MCF5275 additions
  11. * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  12. *
  13. * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  14. */
  15. #include <common.h>
  16. #include <init.h>
  17. #include <net.h>
  18. #include <vsprintf.h>
  19. #include <watchdog.h>
  20. #include <command.h>
  21. #include <asm/immap.h>
  22. #include <asm/io.h>
  23. #include <netdev.h>
  24. #include "cpu.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #ifdef CONFIG_M5208
  27. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  28. {
  29. rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  30. udelay(1000);
  31. out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  32. /* we don't return! */
  33. return 0;
  34. };
  35. #if defined(CONFIG_DISPLAY_CPUINFO)
  36. int print_cpuinfo(void)
  37. {
  38. char buf1[32], buf2[32];
  39. printf("CPU: Freescale Coldfire MCF5208\n"
  40. " CPU CLK %s MHz BUS CLK %s MHz\n",
  41. strmhz(buf1, gd->cpu_clk),
  42. strmhz(buf2, gd->bus_clk));
  43. return 0;
  44. };
  45. #endif /* CONFIG_DISPLAY_CPUINFO */
  46. #if defined(CONFIG_WATCHDOG)
  47. /* Called by macro WATCHDOG_RESET */
  48. void watchdog_reset(void)
  49. {
  50. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  51. out_be16(&wdt->sr, 0x5555);
  52. out_be16(&wdt->sr, 0xaaaa);
  53. }
  54. int watchdog_disable(void)
  55. {
  56. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  57. /* reset watchdog counter */
  58. out_be16(&wdt->sr, 0x5555);
  59. out_be16(&wdt->sr, 0xaaaa);
  60. /* disable watchdog timer */
  61. out_be16(&wdt->cr, 0);
  62. puts("WATCHDOG:disabled\n");
  63. return (0);
  64. }
  65. int watchdog_init(void)
  66. {
  67. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  68. /* disable watchdog */
  69. out_be16(&wdt->cr, 0);
  70. /* set timeout and enable watchdog */
  71. out_be16(&wdt->mr,
  72. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  73. /* reset watchdog counter */
  74. out_be16(&wdt->sr, 0x5555);
  75. out_be16(&wdt->sr, 0xaaaa);
  76. puts("WATCHDOG:enabled\n");
  77. return (0);
  78. }
  79. #endif /* #ifdef CONFIG_WATCHDOG */
  80. #endif /* #ifdef CONFIG_M5208 */
  81. #ifdef CONFIG_M5271
  82. #if defined(CONFIG_DISPLAY_CPUINFO)
  83. /*
  84. * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
  85. * determine which one we are running on, based on the Chip Identification
  86. * Register (CIR).
  87. */
  88. int print_cpuinfo(void)
  89. {
  90. char buf[32];
  91. unsigned short cir; /* Chip Identification Register */
  92. unsigned short pin; /* Part identification number */
  93. unsigned char prn; /* Part revision number */
  94. char *cpu_model;
  95. cir = mbar_readShort(MCF_CCM_CIR);
  96. pin = cir >> MCF_CCM_CIR_PIN_LEN;
  97. prn = cir & MCF_CCM_CIR_PRN_MASK;
  98. switch (pin) {
  99. case MCF_CCM_CIR_PIN_MCF5270:
  100. cpu_model = "5270";
  101. break;
  102. case MCF_CCM_CIR_PIN_MCF5271:
  103. cpu_model = "5271";
  104. break;
  105. default:
  106. cpu_model = NULL;
  107. break;
  108. }
  109. if (cpu_model)
  110. printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
  111. cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
  112. else
  113. printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
  114. " (PIN: 0x%x) rev. %hu, at %s MHz\n",
  115. pin, prn, strmhz(buf, CONFIG_SYS_CLK));
  116. return 0;
  117. }
  118. #endif /* CONFIG_DISPLAY_CPUINFO */
  119. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  120. {
  121. /* Call the board specific reset actions first. */
  122. if(board_reset) {
  123. board_reset();
  124. }
  125. mbar_writeByte(MCF_RCM_RCR,
  126. MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
  127. return 0;
  128. };
  129. #if defined(CONFIG_WATCHDOG)
  130. void watchdog_reset(void)
  131. {
  132. mbar_writeShort(MCF_WTM_WSR, 0x5555);
  133. mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
  134. }
  135. int watchdog_disable(void)
  136. {
  137. mbar_writeShort(MCF_WTM_WCR, 0);
  138. return (0);
  139. }
  140. int watchdog_init(void)
  141. {
  142. mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
  143. return (0);
  144. }
  145. #endif /* #ifdef CONFIG_WATCHDOG */
  146. #endif
  147. #ifdef CONFIG_M5272
  148. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  149. {
  150. wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  151. out_be16(&wdp->wdog_wrrr, 0);
  152. udelay(1000);
  153. /* enable watchdog, set timeout to 0 and wait */
  154. out_be16(&wdp->wdog_wrrr, 1);
  155. while (1) ;
  156. /* we don't return! */
  157. return 0;
  158. };
  159. #if defined(CONFIG_DISPLAY_CPUINFO)
  160. int print_cpuinfo(void)
  161. {
  162. sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
  163. uchar msk;
  164. char *suf;
  165. puts("CPU: ");
  166. msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
  167. switch (msk) {
  168. case 0x2:
  169. suf = "1K75N";
  170. break;
  171. case 0x4:
  172. suf = "3K75N";
  173. break;
  174. default:
  175. suf = NULL;
  176. printf("Freescale MCF5272 (Mask:%01x)\n", msk);
  177. break;
  178. }
  179. if (suf)
  180. printf("Freescale MCF5272 %s\n", suf);
  181. return 0;
  182. };
  183. #endif /* CONFIG_DISPLAY_CPUINFO */
  184. #if defined(CONFIG_WATCHDOG)
  185. /* Called by macro WATCHDOG_RESET */
  186. void watchdog_reset(void)
  187. {
  188. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  189. out_be16(&wdt->wdog_wcr, 0);
  190. }
  191. int watchdog_disable(void)
  192. {
  193. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  194. /* reset watchdog counter */
  195. out_be16(&wdt->wdog_wcr, 0);
  196. /* disable watchdog interrupt */
  197. out_be16(&wdt->wdog_wirr, 0);
  198. /* disable watchdog timer */
  199. out_be16(&wdt->wdog_wrrr, 0);
  200. puts("WATCHDOG:disabled\n");
  201. return (0);
  202. }
  203. int watchdog_init(void)
  204. {
  205. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  206. /* disable watchdog interrupt */
  207. out_be16(&wdt->wdog_wirr, 0);
  208. /* set timeout and enable watchdog */
  209. out_be16(&wdt->wdog_wrrr,
  210. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  211. /* reset watchdog counter */
  212. out_be16(&wdt->wdog_wcr, 0);
  213. puts("WATCHDOG:enabled\n");
  214. return (0);
  215. }
  216. #endif /* #ifdef CONFIG_WATCHDOG */
  217. #endif /* #ifdef CONFIG_M5272 */
  218. #ifdef CONFIG_M5275
  219. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  220. {
  221. rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  222. udelay(1000);
  223. out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  224. /* we don't return! */
  225. return 0;
  226. };
  227. #if defined(CONFIG_DISPLAY_CPUINFO)
  228. int print_cpuinfo(void)
  229. {
  230. char buf[32];
  231. printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
  232. strmhz(buf, CONFIG_SYS_CLK));
  233. return 0;
  234. };
  235. #endif /* CONFIG_DISPLAY_CPUINFO */
  236. #if defined(CONFIG_WATCHDOG)
  237. /* Called by macro WATCHDOG_RESET */
  238. void watchdog_reset(void)
  239. {
  240. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  241. out_be16(&wdt->wsr, 0x5555);
  242. out_be16(&wdt->wsr, 0xaaaa);
  243. }
  244. int watchdog_disable(void)
  245. {
  246. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  247. /* reset watchdog counter */
  248. out_be16(&wdt->wsr, 0x5555);
  249. out_be16(&wdt->wsr, 0xaaaa);
  250. /* disable watchdog timer */
  251. out_be16(&wdt->wcr, 0);
  252. puts("WATCHDOG:disabled\n");
  253. return (0);
  254. }
  255. int watchdog_init(void)
  256. {
  257. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  258. /* disable watchdog */
  259. out_be16(&wdt->wcr, 0);
  260. /* set timeout and enable watchdog */
  261. out_be16(&wdt->wmr,
  262. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  263. /* reset watchdog counter */
  264. out_be16(&wdt->wsr, 0x5555);
  265. out_be16(&wdt->wsr, 0xaaaa);
  266. puts("WATCHDOG:enabled\n");
  267. return (0);
  268. }
  269. #endif /* #ifdef CONFIG_WATCHDOG */
  270. #endif /* #ifdef CONFIG_M5275 */
  271. #ifdef CONFIG_M5282
  272. #if defined(CONFIG_DISPLAY_CPUINFO)
  273. int print_cpuinfo(void)
  274. {
  275. unsigned char resetsource = MCFRESET_RSR;
  276. printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
  277. MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
  278. printf("Reset:%s%s%s%s%s%s%s\n",
  279. (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
  280. (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
  281. (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
  282. (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
  283. (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
  284. (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
  285. (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
  286. return 0;
  287. }
  288. #endif /* CONFIG_DISPLAY_CPUINFO */
  289. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  290. {
  291. MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
  292. return 0;
  293. };
  294. #endif
  295. #ifdef CONFIG_M5249
  296. #if defined(CONFIG_DISPLAY_CPUINFO)
  297. int print_cpuinfo(void)
  298. {
  299. char buf[32];
  300. printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
  301. strmhz(buf, CONFIG_SYS_CLK));
  302. return 0;
  303. }
  304. #endif /* CONFIG_DISPLAY_CPUINFO */
  305. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  306. {
  307. /* enable watchdog, set timeout to 0 and wait */
  308. mbar_writeByte(MCFSIM_SYPCR, 0xc0);
  309. while (1) ;
  310. /* we don't return! */
  311. return 0;
  312. };
  313. #endif
  314. #ifdef CONFIG_M5253
  315. #if defined(CONFIG_DISPLAY_CPUINFO)
  316. int print_cpuinfo(void)
  317. {
  318. char buf[32];
  319. unsigned char resetsource = mbar_readLong(SIM_RSR);
  320. printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
  321. strmhz(buf, CONFIG_SYS_CLK));
  322. if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
  323. printf("Reset:%s%s\n",
  324. (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
  325. : "",
  326. (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
  327. "");
  328. }
  329. return 0;
  330. }
  331. #endif /* CONFIG_DISPLAY_CPUINFO */
  332. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  333. {
  334. /* enable watchdog, set timeout to 0 and wait */
  335. mbar_writeByte(SIM_SYPCR, 0xc0);
  336. while (1) ;
  337. /* we don't return! */
  338. return 0;
  339. };
  340. #endif
  341. #if defined(CONFIG_MCFFEC)
  342. /* Default initializations for MCFFEC controllers. To override,
  343. * create a board-specific function called:
  344. * int board_eth_init(bd_t *bis)
  345. */
  346. int cpu_eth_init(bd_t *bis)
  347. {
  348. return mcffec_initialize(bis);
  349. }
  350. #endif