mp.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <asm/arch/hardware.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/io.h>
  11. #define LOCK 0
  12. #define SPLIT 1
  13. #define HALT 0
  14. #define RELEASE 1
  15. #define ZYNQMP_BOOTADDR_HIGH_MASK 0xFFFFFFFF
  16. #define ZYNQMP_R5_HIVEC_ADDR 0xFFFF0000
  17. #define ZYNQMP_R5_LOVEC_ADDR 0x0
  18. #define ZYNQMP_RPU_CFG_CPU_HALT_MASK 0x01
  19. #define ZYNQMP_RPU_CFG_HIVEC_MASK 0x04
  20. #define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08
  21. #define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40
  22. #define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10
  23. #define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04
  24. #define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK 0x01
  25. #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02
  26. #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
  27. #define ZYNQMP_TCM_START_ADDRESS 0xFFE00000
  28. #define ZYNQMP_TCM_BOTH_SIZE 0x40000
  29. #define ZYNQMP_CORE_APU0 0
  30. #define ZYNQMP_CORE_APU3 3
  31. #define ZYNQMP_MAX_CORES 6
  32. int is_core_valid(unsigned int core)
  33. {
  34. if (core < ZYNQMP_MAX_CORES)
  35. return 1;
  36. return 0;
  37. }
  38. int cpu_reset(u32 nr)
  39. {
  40. puts("Feature is not implemented.\n");
  41. return 0;
  42. }
  43. static void set_r5_halt_mode(u8 halt, u8 mode)
  44. {
  45. u32 tmp;
  46. tmp = readl(&rpu_base->rpu0_cfg);
  47. if (halt == HALT)
  48. tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  49. else
  50. tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  51. writel(tmp, &rpu_base->rpu0_cfg);
  52. if (mode == LOCK) {
  53. tmp = readl(&rpu_base->rpu1_cfg);
  54. if (halt == HALT)
  55. tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  56. else
  57. tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  58. writel(tmp, &rpu_base->rpu1_cfg);
  59. }
  60. }
  61. static void set_r5_tcm_mode(u8 mode)
  62. {
  63. u32 tmp;
  64. tmp = readl(&rpu_base->rpu_glbl_ctrl);
  65. if (mode == LOCK) {
  66. tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  67. tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  68. ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
  69. } else {
  70. tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  71. tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  72. ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK);
  73. }
  74. writel(tmp, &rpu_base->rpu_glbl_ctrl);
  75. }
  76. static void set_r5_reset(u8 mode)
  77. {
  78. u32 tmp;
  79. tmp = readl(&crlapb_base->rst_lpd_top);
  80. tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
  81. ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
  82. if (mode == LOCK)
  83. tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
  84. writel(tmp, &crlapb_base->rst_lpd_top);
  85. }
  86. static void release_r5_reset(u8 mode)
  87. {
  88. u32 tmp;
  89. tmp = readl(&crlapb_base->rst_lpd_top);
  90. tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
  91. ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
  92. if (mode == LOCK)
  93. tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
  94. writel(tmp, &crlapb_base->rst_lpd_top);
  95. }
  96. static void enable_clock_r5(void)
  97. {
  98. u32 tmp;
  99. tmp = readl(&crlapb_base->cpu_r5_ctrl);
  100. tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
  101. writel(tmp, &crlapb_base->cpu_r5_ctrl);
  102. /* Give some delay for clock
  103. * to propagate */
  104. udelay(0x500);
  105. }
  106. int cpu_disable(u32 nr)
  107. {
  108. if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
  109. u32 val = readl(&crfapb_base->rst_fpd_apu);
  110. val |= 1 << nr;
  111. writel(val, &crfapb_base->rst_fpd_apu);
  112. } else {
  113. set_r5_reset(LOCK);
  114. }
  115. return 0;
  116. }
  117. int cpu_status(u32 nr)
  118. {
  119. if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
  120. u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
  121. u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
  122. nr * 8);
  123. u32 val = readl(&crfapb_base->rst_fpd_apu);
  124. val &= 1 << nr;
  125. printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n",
  126. nr, val ? "OFF" : "ON" , addr_high, addr_low);
  127. } else {
  128. u32 val = readl(&crlapb_base->rst_lpd_top);
  129. val &= 1 << (nr - 4);
  130. printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON");
  131. }
  132. return 0;
  133. }
  134. static void set_r5_start(u8 high)
  135. {
  136. u32 tmp;
  137. tmp = readl(&rpu_base->rpu0_cfg);
  138. if (high)
  139. tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
  140. else
  141. tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
  142. writel(tmp, &rpu_base->rpu0_cfg);
  143. tmp = readl(&rpu_base->rpu1_cfg);
  144. if (high)
  145. tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
  146. else
  147. tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
  148. writel(tmp, &rpu_base->rpu1_cfg);
  149. }
  150. static void write_tcm_boot_trampoline(u32 boot_addr)
  151. {
  152. if (boot_addr) {
  153. /*
  154. * Boot trampoline is simple ASM code below.
  155. *
  156. * b over;
  157. * label:
  158. * .word 0
  159. * over: ldr r0, =label
  160. * ldr r1, [r0]
  161. * bx r1
  162. */
  163. debug("Write boot trampoline for %x\n", boot_addr);
  164. writel(0xea000000, ZYNQMP_TCM_START_ADDRESS);
  165. writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4);
  166. writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8);
  167. writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc);
  168. writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10);
  169. writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for
  170. }
  171. }
  172. void initialize_tcm(bool mode)
  173. {
  174. if (!mode) {
  175. set_r5_tcm_mode(LOCK);
  176. set_r5_halt_mode(HALT, LOCK);
  177. enable_clock_r5();
  178. release_r5_reset(LOCK);
  179. } else {
  180. set_r5_tcm_mode(SPLIT);
  181. set_r5_halt_mode(HALT, SPLIT);
  182. enable_clock_r5();
  183. release_r5_reset(SPLIT);
  184. }
  185. }
  186. int cpu_release(u32 nr, int argc, char *const argv[])
  187. {
  188. if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
  189. u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
  190. /* HIGH */
  191. writel((u32)(boot_addr >> 32),
  192. ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8);
  193. /* LOW */
  194. writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK),
  195. ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
  196. u32 val = readl(&crfapb_base->rst_fpd_apu);
  197. val &= ~(1 << nr);
  198. writel(val, &crfapb_base->rst_fpd_apu);
  199. } else {
  200. if (argc != 2) {
  201. printf("Invalid number of arguments to release.\n");
  202. printf("<addr> <mode>-Start addr lockstep or split\n");
  203. return 1;
  204. }
  205. u32 boot_addr = simple_strtoul(argv[0], NULL, 16);
  206. u32 boot_addr_uniq = 0;
  207. if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
  208. boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
  209. printf("Using TCM jump trampoline for address 0x%x\n",
  210. boot_addr);
  211. /* Save boot address for later usage */
  212. boot_addr_uniq = boot_addr;
  213. /*
  214. * R5 needs to start from LOVEC at TCM
  215. * OCM will be probably occupied by ATF
  216. */
  217. boot_addr = ZYNQMP_R5_LOVEC_ADDR;
  218. }
  219. /*
  220. * Since we don't know where the user may have loaded the image
  221. * for an R5 we have to flush all the data cache to ensure
  222. * the R5 sees it.
  223. */
  224. flush_dcache_all();
  225. if (!strncmp(argv[1], "lockstep", 8)) {
  226. printf("R5 lockstep mode\n");
  227. set_r5_reset(LOCK);
  228. set_r5_tcm_mode(LOCK);
  229. set_r5_halt_mode(HALT, LOCK);
  230. set_r5_start(boot_addr);
  231. enable_clock_r5();
  232. release_r5_reset(LOCK);
  233. dcache_disable();
  234. write_tcm_boot_trampoline(boot_addr_uniq);
  235. dcache_enable();
  236. set_r5_halt_mode(RELEASE, LOCK);
  237. } else if (!strncmp(argv[1], "split", 5)) {
  238. printf("R5 split mode\n");
  239. set_r5_reset(SPLIT);
  240. set_r5_tcm_mode(SPLIT);
  241. set_r5_halt_mode(HALT, SPLIT);
  242. set_r5_start(boot_addr);
  243. enable_clock_r5();
  244. release_r5_reset(SPLIT);
  245. dcache_disable();
  246. write_tcm_boot_trampoline(boot_addr_uniq);
  247. dcache_enable();
  248. set_r5_halt_mode(RELEASE, SPLIT);
  249. } else {
  250. printf("Unsupported mode\n");
  251. return 1;
  252. }
  253. }
  254. return 0;
  255. }