umc-sld8.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011-2014 Panasonic Corporation
  4. * Copyright (C) 2015-2016 Socionext Inc.
  5. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  6. */
  7. #include <common.h>
  8. #include <linux/errno.h>
  9. #include <linux/io.h>
  10. #include <linux/sizes.h>
  11. #include <asm/processor.h>
  12. #include "../init.h"
  13. #include "ddrphy-init.h"
  14. #include "umc-regs.h"
  15. #define DRAM_CH_NR 2
  16. enum dram_freq {
  17. DRAM_FREQ_1333M,
  18. DRAM_FREQ_1600M,
  19. DRAM_FREQ_NR,
  20. };
  21. enum dram_size {
  22. DRAM_SZ_128M,
  23. DRAM_SZ_256M,
  24. DRAM_SZ_512M,
  25. DRAM_SZ_NR,
  26. };
  27. static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
  28. static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
  29. static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
  30. static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
  31. static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
  32. {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
  33. {0x002b0617, 0x003f0617, 0x00670617},
  34. };
  35. static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
  36. static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
  37. static int umc_get_rank(int ch)
  38. {
  39. return ch; /* ch0: rank0, ch1: rank1 for this SoC */
  40. }
  41. static void umc_start_ssif(void __iomem *ssif_base)
  42. {
  43. writel(0x00000000, ssif_base + 0x0000b004);
  44. writel(0xffffffff, ssif_base + 0x0000c004);
  45. writel(0x000fffcf, ssif_base + 0x0000c008);
  46. writel(0x00000001, ssif_base + 0x0000b000);
  47. writel(0x00000001, ssif_base + 0x0000c000);
  48. writel(0x03010101, ssif_base + UMC_MDMCHSEL);
  49. writel(0x03010100, ssif_base + UMC_DMDCHSEL);
  50. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
  51. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
  52. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
  53. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
  54. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
  55. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
  56. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
  57. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
  58. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
  59. writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
  60. writel(0x00000001, ssif_base + UMC_CPURST);
  61. writel(0x00000001, ssif_base + UMC_IDSRST);
  62. writel(0x00000001, ssif_base + UMC_IXMRST);
  63. writel(0x00000001, ssif_base + UMC_MDMRST);
  64. writel(0x00000001, ssif_base + UMC_MDDRST);
  65. writel(0x00000001, ssif_base + UMC_SIORST);
  66. writel(0x00000001, ssif_base + UMC_VIORST);
  67. writel(0x00000001, ssif_base + UMC_FRCRST);
  68. writel(0x00000001, ssif_base + UMC_RGLRST);
  69. writel(0x00000001, ssif_base + UMC_AIORST);
  70. writel(0x00000001, ssif_base + UMC_DMDRST);
  71. }
  72. static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
  73. int freq, unsigned long size, bool ddr3plus)
  74. {
  75. enum dram_freq freq_e;
  76. enum dram_size size_e;
  77. switch (freq) {
  78. case 1333:
  79. freq_e = DRAM_FREQ_1333M;
  80. break;
  81. case 1600:
  82. freq_e = DRAM_FREQ_1600M;
  83. break;
  84. default:
  85. pr_err("unsupported DRAM frequency %d MHz\n", freq);
  86. return -EINVAL;
  87. }
  88. switch (size) {
  89. case 0:
  90. return 0;
  91. case SZ_128M:
  92. size_e = DRAM_SZ_128M;
  93. break;
  94. case SZ_256M:
  95. size_e = DRAM_SZ_256M;
  96. break;
  97. case SZ_512M:
  98. size_e = DRAM_SZ_512M;
  99. break;
  100. default:
  101. pr_err("unsupported DRAM size 0x%08lx\n", size);
  102. return -EINVAL;
  103. }
  104. writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
  105. dc_base + UMC_CMDCTLA);
  106. writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
  107. dc_base + UMC_CMDCTLB);
  108. writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
  109. writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
  110. writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
  111. writel(0x04060806, dc_base + UMC_WDATACTL_D0);
  112. writel(0x04a02000, dc_base + UMC_DATASET);
  113. writel(0x00000000, ca_base + 0x2300);
  114. writel(0x00400020, dc_base + UMC_DCCGCTL);
  115. writel(0x00000003, dc_base + 0x7000);
  116. writel(0x0000004f, dc_base + 0x8000);
  117. writel(0x000000c3, dc_base + 0x8004);
  118. writel(0x00000077, dc_base + 0x8008);
  119. writel(0x0000003b, dc_base + UMC_DICGCTLA);
  120. writel(0x020a0808, dc_base + UMC_DICGCTLB);
  121. writel(0x00000004, dc_base + UMC_FLOWCTLG);
  122. writel(0x80000201, ca_base + 0xc20);
  123. writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
  124. writel(0x00200000, dc_base + UMC_FLOWCTLB);
  125. writel(0x00004444, dc_base + UMC_FLOWCTLC);
  126. writel(0x200a0a00, dc_base + UMC_SPCSETB);
  127. writel(0x00000000, dc_base + UMC_SPCSETD);
  128. writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
  129. return 0;
  130. }
  131. static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
  132. int freq, unsigned long size, bool ddr3plus, int ch)
  133. {
  134. void __iomem *phy_base = dc_base + 0x00001000;
  135. int ret;
  136. writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
  137. while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
  138. cpu_relax();
  139. writel(0x00000101, dc_base + UMC_DIOCTLA);
  140. ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
  141. if (ret)
  142. return ret;
  143. ddrphy_prepare_training(phy_base, umc_get_rank(ch));
  144. ret = ddrphy_training(phy_base);
  145. if (ret)
  146. return ret;
  147. return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
  148. }
  149. int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
  150. {
  151. void __iomem *umc_base = (void __iomem *)0x5b800000;
  152. void __iomem *ca_base = umc_base + 0x00001000;
  153. void __iomem *dc_base = umc_base + 0x00400000;
  154. void __iomem *ssif_base = umc_base;
  155. int ch, ret;
  156. for (ch = 0; ch < DRAM_CH_NR; ch++) {
  157. ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
  158. bd->dram_ch[ch].size,
  159. !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
  160. if (ret) {
  161. pr_err("failed to initialize UMC ch%d\n", ch);
  162. return ret;
  163. }
  164. ca_base += 0x00001000;
  165. dc_base += 0x00200000;
  166. }
  167. umc_start_ssif(ssif_base);
  168. return 0;
  169. }