umc-pxs2.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2017 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. *
  6. * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
  7. * Copyright (C) 2015 Socionext Inc.
  8. */
  9. #include <init.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <linux/io.h>
  13. #include <linux/printk.h>
  14. #include <linux/sizes.h>
  15. #include <asm/processor.h>
  16. #include <time.h>
  17. #include "../init.h"
  18. #include "../soc-info.h"
  19. #include "ddrmphy-regs.h"
  20. #include "umc-regs.h"
  21. #define DRAM_CH_NR 3
  22. enum dram_freq {
  23. DRAM_FREQ_1866M,
  24. DRAM_FREQ_2133M,
  25. DRAM_FREQ_NR,
  26. };
  27. enum dram_size {
  28. DRAM_SZ_256M,
  29. DRAM_SZ_512M,
  30. DRAM_SZ_NR,
  31. };
  32. /* PHY */
  33. static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
  34. static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
  35. static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
  36. static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357};
  37. static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
  38. static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88};
  39. static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0};
  40. static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00};
  41. static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89};
  42. static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125};
  43. static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};
  44. /* dependent on package and board design */
  45. static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
  46. /* DDR multiPHY */
  47. static inline int ddrphy_get_rank(int dx)
  48. {
  49. return dx / 2;
  50. }
  51. static void ddrphy_fifo_reset(void __iomem *phy_base)
  52. {
  53. u32 tmp;
  54. tmp = readl(phy_base + MPHY_PGCR0);
  55. tmp &= ~MPHY_PGCR0_PHYFRST;
  56. writel(tmp, phy_base + MPHY_PGCR0);
  57. udelay(1);
  58. tmp |= MPHY_PGCR0_PHYFRST;
  59. writel(tmp, phy_base + MPHY_PGCR0);
  60. udelay(1);
  61. }
  62. static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
  63. {
  64. u32 tmp;
  65. tmp = readl(phy_base + MPHY_PGCR1);
  66. if (enable)
  67. tmp &= ~MPHY_PGCR1_INHVT;
  68. else
  69. tmp |= MPHY_PGCR1_INHVT;
  70. writel(tmp, phy_base + MPHY_PGCR1);
  71. if (!enable) {
  72. while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP))
  73. cpu_relax();
  74. }
  75. }
  76. static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
  77. {
  78. int dx;
  79. u32 lcdlr1, rdqsd;
  80. void __iomem *dx_base = phy_base + MPHY_DX_BASE;
  81. ddrphy_vt_ctrl(phy_base, 0);
  82. for (dx = 0; dx < nr_dx; dx++) {
  83. lcdlr1 = readl(dx_base + MPHY_DX_LCDLR1);
  84. rdqsd = (lcdlr1 >> 8) & 0xff;
  85. rdqsd = clamp(rdqsd + step, 0U, 0xffU);
  86. lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
  87. writel(lcdlr1, dx_base + MPHY_DX_LCDLR1);
  88. readl(dx_base + MPHY_DX_LCDLR1); /* relax */
  89. dx_base += MPHY_DX_STRIDE;
  90. }
  91. ddrphy_vt_ctrl(phy_base, 1);
  92. }
  93. static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
  94. {
  95. void __iomem *dx_base = phy_base + MPHY_DX_BASE;
  96. const int nr_dx = width / 8;
  97. int dx, rank;
  98. u32 gtr;
  99. int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
  100. for (dx = 0; dx < nr_dx; dx++) {
  101. gtr = readl(dx_base + MPHY_DX_GTR);
  102. for (rank = 0; rank < 4; rank++) {
  103. dgsl = gtr & 0x7;
  104. /* if dgsl is zero, this rank was not trained. skip. */
  105. if (dgsl) {
  106. dgsl_min = min(dgsl_min, dgsl);
  107. dgsl_max = max(dgsl_max, dgsl);
  108. }
  109. gtr >>= 3;
  110. }
  111. dx_base += MPHY_DX_STRIDE;
  112. }
  113. if (dgsl_min != dgsl_max)
  114. pr_warn("DQS Gateing System Latencies are not all leveled.\n");
  115. return dgsl_max;
  116. }
  117. static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
  118. int ch)
  119. {
  120. u32 tmp;
  121. void __iomem *zq_base, *dx_base;
  122. int zq, dx;
  123. int nr_dx;
  124. nr_dx = width / 8;
  125. writel(MPHY_PIR_ZCALBYP, phy_base + MPHY_PIR);
  126. /*
  127. * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
  128. * to avoid read error issue.
  129. */
  130. writel(0x07d81e37, phy_base + MPHY_PGCR0);
  131. writel(0x0200c4e0, phy_base + MPHY_PGCR1);
  132. tmp = ddrphy_pgcr2[freq];
  133. if (width >= 32)
  134. tmp |= MPHY_PGCR2_DUALCHN | MPHY_PGCR2_ACPDDC;
  135. writel(tmp, phy_base + MPHY_PGCR2);
  136. writel(ddrphy_ptr0[freq], phy_base + MPHY_PTR0);
  137. writel(ddrphy_ptr1[freq], phy_base + MPHY_PTR1);
  138. writel(0x00083def, phy_base + MPHY_PTR2);
  139. writel(ddrphy_ptr3[freq], phy_base + MPHY_PTR3);
  140. writel(ddrphy_ptr4[freq], phy_base + MPHY_PTR4);
  141. writel(ddrphy_acbdlr0[ch], phy_base + MPHY_ACBDLR0);
  142. writel(0x55555555, phy_base + MPHY_ACIOCR1);
  143. writel(0x00000000, phy_base + MPHY_ACIOCR2);
  144. writel(0x55555555, phy_base + MPHY_ACIOCR3);
  145. writel(0x00000000, phy_base + MPHY_ACIOCR4);
  146. writel(0x00000055, phy_base + MPHY_ACIOCR5);
  147. writel(0x00181aa4, phy_base + MPHY_DXCCR);
  148. writel(0x0024641e, phy_base + MPHY_DSGCR);
  149. writel(0x0000040b, phy_base + MPHY_DCR);
  150. writel(ddrphy_dtpr0[freq], phy_base + MPHY_DTPR0);
  151. writel(ddrphy_dtpr1[freq], phy_base + MPHY_DTPR1);
  152. writel(ddrphy_dtpr2[freq], phy_base + MPHY_DTPR2);
  153. writel(ddrphy_dtpr3[freq], phy_base + MPHY_DTPR3);
  154. writel(ddrphy_mr0[freq], phy_base + MPHY_MR0);
  155. writel(0x00000006, phy_base + MPHY_MR1);
  156. writel(ddrphy_mr2[freq], phy_base + MPHY_MR2);
  157. writel(0x00000000, phy_base + MPHY_MR3);
  158. tmp = 0;
  159. for (dx = 0; dx < nr_dx; dx++)
  160. tmp |= BIT(MPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
  161. writel(0x90003087 | tmp, phy_base + MPHY_DTCR);
  162. writel(0x00000000, phy_base + MPHY_DTAR0);
  163. writel(0x00000008, phy_base + MPHY_DTAR1);
  164. writel(0x00000010, phy_base + MPHY_DTAR2);
  165. writel(0x00000018, phy_base + MPHY_DTAR3);
  166. writel(0xdd22ee11, phy_base + MPHY_DTDR0);
  167. writel(0x7788bb44, phy_base + MPHY_DTDR1);
  168. /* impedance control settings */
  169. writel(0x04048900, phy_base + MPHY_ZQCR);
  170. zq_base = phy_base + MPHY_ZQ_BASE;
  171. for (zq = 0; zq < 4; zq++) {
  172. /*
  173. * board-dependent
  174. * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
  175. */
  176. writel(0x0007BB5D, zq_base + MPHY_ZQ_PR);
  177. zq_base += MPHY_ZQ_STRIDE;
  178. }
  179. /* DATX8 settings */
  180. dx_base = phy_base + MPHY_DX_BASE;
  181. for (dx = 0; dx < 4; dx++) {
  182. tmp = readl(dx_base + MPHY_DX_GCR0);
  183. tmp &= ~MPHY_DX_GCR0_WLRKEN_MASK;
  184. tmp |= BIT(MPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
  185. MPHY_DX_GCR0_WLRKEN_MASK;
  186. writel(tmp, dx_base + MPHY_DX_GCR0);
  187. writel(0x00000000, dx_base + MPHY_DX_GCR1);
  188. writel(0x00000000, dx_base + MPHY_DX_GCR2);
  189. writel(0x00000000, dx_base + MPHY_DX_GCR3);
  190. dx_base += MPHY_DX_STRIDE;
  191. }
  192. while (!(readl(phy_base + MPHY_PGSR0) & MPHY_PGSR0_IDONE))
  193. cpu_relax();
  194. ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
  195. }
  196. struct ddrphy_init_sequence {
  197. char *description;
  198. u32 init_flag;
  199. u32 done_flag;
  200. u32 err_flag;
  201. };
  202. static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
  203. {
  204. "Impedance Calibration",
  205. MPHY_PIR_ZCAL,
  206. MPHY_PGSR0_ZCDONE,
  207. MPHY_PGSR0_ZCERR,
  208. },
  209. { /* sentinel */ }
  210. };
  211. static const struct ddrphy_init_sequence dram_init_sequence[] = {
  212. {
  213. "DRAM Initialization",
  214. MPHY_PIR_DRAMRST | MPHY_PIR_DRAMINIT,
  215. MPHY_PGSR0_DIDONE,
  216. 0,
  217. },
  218. { /* sentinel */ }
  219. };
  220. static const struct ddrphy_init_sequence training_sequence[] = {
  221. {
  222. "Write Leveling",
  223. MPHY_PIR_WL,
  224. MPHY_PGSR0_WLDONE,
  225. MPHY_PGSR0_WLERR,
  226. },
  227. {
  228. "Read DQS Gate Training",
  229. MPHY_PIR_QSGATE,
  230. MPHY_PGSR0_QSGDONE,
  231. MPHY_PGSR0_QSGERR,
  232. },
  233. {
  234. "Write Leveling Adjustment",
  235. MPHY_PIR_WLADJ,
  236. MPHY_PGSR0_WLADONE,
  237. MPHY_PGSR0_WLAERR,
  238. },
  239. {
  240. "Read Bit Deskew",
  241. MPHY_PIR_RDDSKW,
  242. MPHY_PGSR0_RDDONE,
  243. MPHY_PGSR0_RDERR,
  244. },
  245. {
  246. "Write Bit Deskew",
  247. MPHY_PIR_WRDSKW,
  248. MPHY_PGSR0_WDDONE,
  249. MPHY_PGSR0_WDERR,
  250. },
  251. {
  252. "Read Eye Training",
  253. MPHY_PIR_RDEYE,
  254. MPHY_PGSR0_REDONE,
  255. MPHY_PGSR0_REERR,
  256. },
  257. {
  258. "Write Eye Training",
  259. MPHY_PIR_WREYE,
  260. MPHY_PGSR0_WEDONE,
  261. MPHY_PGSR0_WEERR,
  262. },
  263. { /* sentinel */ }
  264. };
  265. static int __ddrphy_training(void __iomem *phy_base,
  266. const struct ddrphy_init_sequence *seq)
  267. {
  268. const struct ddrphy_init_sequence *s;
  269. u32 pgsr0;
  270. u32 init_flag = MPHY_PIR_INIT;
  271. u32 done_flag = MPHY_PGSR0_IDONE;
  272. int timeout = 50000; /* 50 msec is long enough */
  273. unsigned long start = 0;
  274. #ifdef DEBUG
  275. start = get_timer(0);
  276. #endif
  277. for (s = seq; s->description; s++) {
  278. init_flag |= s->init_flag;
  279. done_flag |= s->done_flag;
  280. }
  281. writel(init_flag, phy_base + MPHY_PIR);
  282. do {
  283. if (--timeout < 0) {
  284. pr_err("%s: error: timeout during DDR training\n",
  285. __func__);
  286. return -ETIMEDOUT;
  287. }
  288. udelay(1);
  289. pgsr0 = readl(phy_base + MPHY_PGSR0);
  290. } while ((pgsr0 & done_flag) != done_flag);
  291. for (s = seq; s->description; s++) {
  292. if (pgsr0 & s->err_flag) {
  293. pr_err("%s: error: %s failed\n", __func__,
  294. s->description);
  295. return -EIO;
  296. }
  297. }
  298. pr_debug("DDRPHY training: elapsed time %ld msec\n", get_timer(start));
  299. return 0;
  300. }
  301. static int ddrphy_impedance_calibration(void __iomem *phy_base)
  302. {
  303. int ret;
  304. u32 tmp;
  305. ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
  306. if (ret)
  307. return ret;
  308. /*
  309. * Because of a hardware bug, IDONE flag is set when the first ZQ block
  310. * is calibrated. The flag does not guarantee the completion for all
  311. * the ZQ blocks. Wait a little more just in case.
  312. */
  313. udelay(1);
  314. /* reflect ZQ settings and enable average algorithm*/
  315. tmp = readl(phy_base + MPHY_ZQCR);
  316. tmp |= MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
  317. writel(tmp, phy_base + MPHY_ZQCR);
  318. tmp &= ~MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
  319. tmp |= MPHY_ZQCR_AVGEN;
  320. writel(tmp, phy_base + MPHY_ZQCR);
  321. return 0;
  322. }
  323. static int ddrphy_dram_init(void __iomem *phy_base)
  324. {
  325. return __ddrphy_training(phy_base, dram_init_sequence);
  326. }
  327. static int ddrphy_training(void __iomem *phy_base)
  328. {
  329. return __ddrphy_training(phy_base, training_sequence);
  330. }
  331. /* UMC */
  332. static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
  333. /*
  334. * The ch2 is a different generation UMC core.
  335. * The register spec is different, unfortunately.
  336. */
  337. static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
  338. static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
  339. static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
  340. {0x004A071D, 0x0078071D},
  341. {0x0055081E, 0x0089081E},
  342. };
  343. static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
  344. /* The ch2 is different for some reason only hardware guys know... */
  345. static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
  346. static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
  347. static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
  348. {
  349. u32 val;
  350. int latency;
  351. val = readl(dc_base + UMC_RDATACTL_D0);
  352. latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
  353. latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
  354. UMC_RDATACTL_RAD2LTY_SHIFT;
  355. /*
  356. * UMC works at the half clock rate of the PHY.
  357. * The LSB of latency is ignored
  358. */
  359. latency += phy_latency & ~1;
  360. val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
  361. if (latency > 0xf) {
  362. val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
  363. val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
  364. } else {
  365. val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
  366. }
  367. writel(val, dc_base + UMC_RDATACTL_D0);
  368. writel(val, dc_base + UMC_RDATACTL_D1);
  369. readl(dc_base + UMC_RDATACTL_D1); /* relax */
  370. }
  371. /* enable/disable auto refresh */
  372. static void umc_refresh_ctrl(void __iomem *dc_base, int enable)
  373. {
  374. u32 tmp;
  375. tmp = readl(dc_base + UMC_SPCSETB);
  376. tmp &= ~UMC_SPCSETB_AREFMD_MASK;
  377. if (enable)
  378. tmp |= UMC_SPCSETB_AREFMD_ARB;
  379. else
  380. tmp |= UMC_SPCSETB_AREFMD_REG;
  381. writel(tmp, dc_base + UMC_SPCSETB);
  382. udelay(1);
  383. }
  384. static void umc_ud_init(void __iomem *umc_base, int ch)
  385. {
  386. writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
  387. if (ch == 2)
  388. writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
  389. }
  390. static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
  391. unsigned long size, int width, int ch)
  392. {
  393. enum dram_size size_e;
  394. int latency;
  395. u32 val;
  396. switch (size) {
  397. case 0:
  398. return 0;
  399. case SZ_256M:
  400. size_e = DRAM_SZ_256M;
  401. break;
  402. case SZ_512M:
  403. size_e = DRAM_SZ_512M;
  404. break;
  405. default:
  406. pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
  407. size, ch);
  408. return -EINVAL;
  409. }
  410. writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
  411. writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
  412. dc_base + UMC_CMDCTLB);
  413. writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA);
  414. writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);
  415. val = 0x000e000e;
  416. latency = 12;
  417. /* ES2 inserted one more FF to the logic. */
  418. if (uniphier_get_soc_model() >= 2)
  419. latency += 2;
  420. if (latency > 0xf) {
  421. val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
  422. val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
  423. } else {
  424. val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
  425. }
  426. writel(val, dc_base + UMC_RDATACTL_D0);
  427. if (width >= 32)
  428. writel(val, dc_base + UMC_RDATACTL_D1);
  429. writel(0x04060A02, dc_base + UMC_WDATACTL_D0);
  430. if (width >= 32)
  431. writel(0x04060A02, dc_base + UMC_WDATACTL_D1);
  432. writel(0x04000000, dc_base + UMC_DATASET);
  433. writel(0x00400020, dc_base + UMC_DCCGCTL);
  434. writel(0x00000084, dc_base + UMC_FLOWCTLG);
  435. writel(0x00000000, dc_base + UMC_ACSSETA);
  436. writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
  437. dc_base + UMC_FLOWCTLA);
  438. writel(0x00004400, dc_base + UMC_FLOWCTLC);
  439. writel(0x200A0A00, dc_base + UMC_SPCSETB);
  440. writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
  441. writel(0x0000000D, dc_base + UMC_RESPCTL);
  442. if (ch != 2) {
  443. writel(0x00202000, dc_base + UMC_FLOWCTLB);
  444. writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);
  445. writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);
  446. writel(0x00080700, dc_base + UMC_BSICMAPSET);
  447. } else {
  448. writel(0x00200000, dc_base + UMC_FLOWCTLB);
  449. writel(0x00000000, dc_base + UMC_BSICMAPSET);
  450. }
  451. writel(0x00000000, dc_base + UMC_ERRMASKA);
  452. writel(0x00000000, dc_base + UMC_ERRMASKB);
  453. return 0;
  454. }
  455. static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
  456. unsigned long size, unsigned int width, int ch)
  457. {
  458. void __iomem *dc_base = umc_ch_base + 0x00011000;
  459. void __iomem *phy_base = umc_ch_base + 0x00030000;
  460. int ret;
  461. writel(0x00000002, dc_base + UMC_INITSET);
  462. while (readl(dc_base + UMC_INITSTAT) & BIT(2))
  463. cpu_relax();
  464. /* deassert PHY reset signals */
  465. writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
  466. dc_base + UMC_DIOCTLA);
  467. ddrphy_init(phy_base, freq, width, ch);
  468. ret = ddrphy_impedance_calibration(phy_base);
  469. if (ret)
  470. return ret;
  471. ddrphy_dram_init(phy_base);
  472. if (ret)
  473. return ret;
  474. ret = umc_dc_init(dc_base, freq, size, width, ch);
  475. if (ret)
  476. return ret;
  477. umc_ud_init(umc_ch_base, ch);
  478. ret = ddrphy_training(phy_base);
  479. if (ret)
  480. return ret;
  481. udelay(1);
  482. /* match the system latency between UMC and PHY */
  483. umc_set_system_latency(dc_base,
  484. ddrphy_get_system_latency(phy_base, width));
  485. udelay(1);
  486. /* stop auto refresh before clearing FIFO in PHY */
  487. umc_refresh_ctrl(dc_base, 0);
  488. ddrphy_fifo_reset(phy_base);
  489. umc_refresh_ctrl(dc_base, 1);
  490. udelay(10);
  491. return 0;
  492. }
  493. static void um_init(void __iomem *um_base)
  494. {
  495. writel(0x000000ff, um_base + UMC_MBUS0);
  496. writel(0x000000ff, um_base + UMC_MBUS1);
  497. writel(0x000000ff, um_base + UMC_MBUS2);
  498. writel(0x000000ff, um_base + UMC_MBUS3);
  499. }
  500. int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd)
  501. {
  502. void __iomem *um_base = (void __iomem *)0x5b600000;
  503. void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
  504. enum dram_freq freq;
  505. int ch, ret;
  506. switch (bd->dram_freq) {
  507. case 1866:
  508. freq = DRAM_FREQ_1866M;
  509. break;
  510. case 2133:
  511. freq = DRAM_FREQ_2133M;
  512. break;
  513. default:
  514. pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
  515. return -EINVAL;
  516. }
  517. for (ch = 0; ch < DRAM_CH_NR; ch++) {
  518. unsigned long size = bd->dram_ch[ch].size;
  519. unsigned int width = bd->dram_ch[ch].width;
  520. if (size) {
  521. ret = umc_ch_init(umc_ch_base, freq,
  522. size / (width / 16), width, ch);
  523. if (ret) {
  524. pr_err("failed to initialize UMC ch%d\n", ch);
  525. return ret;
  526. }
  527. }
  528. umc_ch_base += 0x00200000;
  529. }
  530. um_init(um_base);
  531. return 0;
  532. }