cmd_ddrmphy.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2017 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <stdio.h>
  9. #include <linux/io.h>
  10. #include <linux/printk.h>
  11. #include <linux/sizes.h>
  12. #include "../soc-info.h"
  13. #include "ddrmphy-regs.h"
  14. /* Select either decimal or hexadecimal */
  15. #if 1
  16. #define PRINTF_FORMAT "%2d"
  17. #else
  18. #define PRINTF_FORMAT "%02x"
  19. #endif
  20. /* field separator */
  21. #define FS " "
  22. #define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
  23. #define UNIPHIER_MAX_NR_DDRMPHY 3
  24. struct uniphier_ddrmphy_param {
  25. unsigned int soc_id;
  26. unsigned int nr_phy;
  27. struct {
  28. resource_size_t base;
  29. unsigned int nr_zq;
  30. unsigned int nr_dx;
  31. } phy[UNIPHIER_MAX_NR_DDRMPHY];
  32. };
  33. static const struct uniphier_ddrmphy_param uniphier_ddrmphy_param[] = {
  34. {
  35. .soc_id = UNIPHIER_PXS2_ID,
  36. .nr_phy = 3,
  37. .phy = {
  38. { .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
  39. { .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
  40. { .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
  41. },
  42. },
  43. {
  44. .soc_id = UNIPHIER_LD6B_ID,
  45. .nr_phy = 3,
  46. .phy = {
  47. { .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
  48. { .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
  49. { .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
  50. },
  51. },
  52. };
  53. UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrmphy_param, uniphier_ddrmphy_param)
  54. static void print_bdl(void __iomem *reg, int n)
  55. {
  56. u32 val = readl(reg);
  57. int i;
  58. for (i = 0; i < n; i++)
  59. printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
  60. }
  61. static void dump_loop(const struct uniphier_ddrmphy_param *param,
  62. void (*callback)(void __iomem *))
  63. {
  64. void __iomem *phy_base, *dx_base;
  65. int phy, dx;
  66. for (phy = 0; phy < param->nr_phy; phy++) {
  67. phy_base = ioremap(param->phy[phy].base, SZ_4K);
  68. dx_base = phy_base + MPHY_DX_BASE;
  69. for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
  70. printf("PHY%dDX%d:", phy, dx);
  71. (*callback)(dx_base);
  72. dx_base += MPHY_DX_STRIDE;
  73. printf("\n");
  74. }
  75. iounmap(phy_base);
  76. }
  77. }
  78. static void zq_dump(const struct uniphier_ddrmphy_param *param)
  79. {
  80. void __iomem *phy_base, *zq_base;
  81. u32 val;
  82. int phy, zq, i;
  83. printf("\n--- Impedance Data ---\n");
  84. printf(" ZPD ZPU OPD OPU ZDV ODV\n");
  85. for (phy = 0; phy < param->nr_phy; phy++) {
  86. phy_base = ioremap(param->phy[phy].base, SZ_4K);
  87. zq_base = phy_base + MPHY_ZQ_BASE;
  88. for (zq = 0; zq < param->phy[phy].nr_zq; zq++) {
  89. printf("PHY%dZQ%d:", phy, zq);
  90. val = readl(zq_base + MPHY_ZQ_DR);
  91. for (i = 0; i < 4; i++) {
  92. printf(FS PRINTF_FORMAT, val & 0x7f);
  93. val >>= 7;
  94. }
  95. val = readl(zq_base + MPHY_ZQ_PR);
  96. for (i = 0; i < 2; i++) {
  97. printf(FS PRINTF_FORMAT, val & 0xf);
  98. val >>= 4;
  99. }
  100. zq_base += MPHY_ZQ_STRIDE;
  101. printf("\n");
  102. }
  103. iounmap(phy_base);
  104. }
  105. }
  106. static void __wbdl_dump(void __iomem *dx_base)
  107. {
  108. print_bdl(dx_base + MPHY_DX_BDLR0, 4);
  109. print_bdl(dx_base + MPHY_DX_BDLR1, 4);
  110. print_bdl(dx_base + MPHY_DX_BDLR2, 2);
  111. printf(FS "(+" PRINTF_FORMAT ")",
  112. readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
  113. }
  114. static void wbdl_dump(const struct uniphier_ddrmphy_param *param)
  115. {
  116. printf("\n--- Write Bit Delay Line ---\n");
  117. printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
  118. dump_loop(param, &__wbdl_dump);
  119. }
  120. static void __rbdl_dump(void __iomem *dx_base)
  121. {
  122. print_bdl(dx_base + MPHY_DX_BDLR3, 4);
  123. print_bdl(dx_base + MPHY_DX_BDLR4, 4);
  124. print_bdl(dx_base + MPHY_DX_BDLR5, 1);
  125. printf(FS "(+" PRINTF_FORMAT ")",
  126. (readl(dx_base + MPHY_DX_LCDLR1) >> 8) & 0xff);
  127. printf(FS "(+" PRINTF_FORMAT ")",
  128. (readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
  129. }
  130. static void rbdl_dump(const struct uniphier_ddrmphy_param *param)
  131. {
  132. printf("\n--- Read Bit Delay Line ---\n");
  133. printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
  134. dump_loop(param, &__rbdl_dump);
  135. }
  136. static void __wld_dump(void __iomem *dx_base)
  137. {
  138. int rank;
  139. u32 lcdlr0 = readl(dx_base + MPHY_DX_LCDLR0);
  140. u32 gtr = readl(dx_base + MPHY_DX_GTR);
  141. for (rank = 0; rank < 4; rank++) {
  142. u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
  143. u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
  144. printf(FS PRINTF_FORMAT "%sT", wld,
  145. wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
  146. }
  147. }
  148. static void wld_dump(const struct uniphier_ddrmphy_param *param)
  149. {
  150. printf("\n--- Write Leveling Delay ---\n");
  151. printf(" Rank0 Rank1 Rank2 Rank3\n");
  152. dump_loop(param, &__wld_dump);
  153. }
  154. static void __dqsgd_dump(void __iomem *dx_base)
  155. {
  156. int rank;
  157. u32 lcdlr2 = readl(dx_base + MPHY_DX_LCDLR2);
  158. u32 gtr = readl(dx_base + MPHY_DX_GTR);
  159. for (rank = 0; rank < 4; rank++) {
  160. u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
  161. u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
  162. printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
  163. }
  164. }
  165. static void dqsgd_dump(const struct uniphier_ddrmphy_param *param)
  166. {
  167. printf("\n--- DQS Gating Delay ---\n");
  168. printf(" Rank0 Rank1 Rank2 Rank3\n");
  169. dump_loop(param, &__dqsgd_dump);
  170. }
  171. static void __mdl_dump(void __iomem *dx_base)
  172. {
  173. int i;
  174. u32 mdl = readl(dx_base + MPHY_DX_MDLR);
  175. for (i = 0; i < 3; i++)
  176. printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
  177. }
  178. static void mdl_dump(const struct uniphier_ddrmphy_param *param)
  179. {
  180. printf("\n--- Master Delay Line ---\n");
  181. printf(" IPRD TPRD MDLD\n");
  182. dump_loop(param, &__mdl_dump);
  183. }
  184. #define REG_DUMP(x) \
  185. { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
  186. printf("%3d: %-10s: %p : %08x\n", \
  187. ofst >> MPHY_SHIFT, #x, reg, readl(reg)); }
  188. #define DX_REG_DUMP(dx, x) \
  189. { int ofst = MPHY_DX_BASE + MPHY_DX_STRIDE * (dx) + \
  190. MPHY_DX_## x; \
  191. void __iomem *reg = phy_base + ofst; \
  192. printf("%3d: DX%d%-7s: %p : %08x\n", \
  193. ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
  194. static void reg_dump(const struct uniphier_ddrmphy_param *param)
  195. {
  196. void __iomem *phy_base;
  197. int phy, dx;
  198. printf("\n--- DDR Multi PHY registers ---\n");
  199. for (phy = 0; phy < param->nr_phy; phy++) {
  200. phy_base = ioremap(param->phy[phy].base, SZ_4K);
  201. printf("== PHY%d (base: %08x) ==\n", phy,
  202. ptr_to_uint(phy_base));
  203. printf(" No: Name : Address : Data\n");
  204. REG_DUMP(RIDR);
  205. REG_DUMP(PIR);
  206. REG_DUMP(PGCR0);
  207. REG_DUMP(PGCR1);
  208. REG_DUMP(PGCR2);
  209. REG_DUMP(PGCR3);
  210. REG_DUMP(PGSR0);
  211. REG_DUMP(PGSR1);
  212. REG_DUMP(PLLCR);
  213. REG_DUMP(PTR0);
  214. REG_DUMP(PTR1);
  215. REG_DUMP(PTR2);
  216. REG_DUMP(PTR3);
  217. REG_DUMP(PTR4);
  218. REG_DUMP(ACMDLR);
  219. REG_DUMP(ACBDLR0);
  220. REG_DUMP(DXCCR);
  221. REG_DUMP(DSGCR);
  222. REG_DUMP(DCR);
  223. REG_DUMP(DTPR0);
  224. REG_DUMP(DTPR1);
  225. REG_DUMP(DTPR2);
  226. REG_DUMP(DTPR3);
  227. REG_DUMP(MR0);
  228. REG_DUMP(MR1);
  229. REG_DUMP(MR2);
  230. REG_DUMP(MR3);
  231. for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
  232. DX_REG_DUMP(dx, GCR0);
  233. DX_REG_DUMP(dx, GCR1);
  234. DX_REG_DUMP(dx, GCR2);
  235. DX_REG_DUMP(dx, GCR3);
  236. DX_REG_DUMP(dx, GTR);
  237. }
  238. iounmap(phy_base);
  239. }
  240. }
  241. static int do_ddrm(struct cmd_tbl *cmdtp, int flag, int argc,
  242. char *const argv[])
  243. {
  244. const struct uniphier_ddrmphy_param *param;
  245. char *cmd;
  246. param = uniphier_get_ddrmphy_param();
  247. if (!param) {
  248. pr_err("unsupported SoC\n");
  249. return CMD_RET_FAILURE;
  250. }
  251. if (argc == 1)
  252. cmd = "all";
  253. else
  254. cmd = argv[1];
  255. if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
  256. zq_dump(param);
  257. if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
  258. wbdl_dump(param);
  259. if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
  260. rbdl_dump(param);
  261. if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
  262. wld_dump(param);
  263. if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
  264. dqsgd_dump(param);
  265. if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
  266. mdl_dump(param);
  267. if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
  268. reg_dump(param);
  269. return CMD_RET_SUCCESS;
  270. }
  271. U_BOOT_CMD(
  272. ddrm, 2, 1, do_ddrm,
  273. "UniPhier DDR Multi PHY parameters dumper",
  274. "- dump all of the following\n"
  275. "ddrm zq - dump Impedance Data\n"
  276. "ddrm wbdl - dump Write Bit Delay\n"
  277. "ddrm rbdl - dump Read Bit Delay\n"
  278. "ddrm wld - dump Write Leveling\n"
  279. "ddrm dqsgd - dump DQS Gating Delay\n"
  280. "ddrm mdl - dump Master Delay Line\n"
  281. "ddrm reg - dump registers\n"
  282. );