misc.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <cpu_func.h>
  8. #include <hang.h>
  9. #include <asm/cache.h>
  10. #include <init.h>
  11. #include <asm/io.h>
  12. #include <errno.h>
  13. #include <fdtdec.h>
  14. #include <linux/libfdt.h>
  15. #include <altera.h>
  16. #include <miiphy.h>
  17. #include <netdev.h>
  18. #include <watchdog.h>
  19. #include <asm/arch/misc.h>
  20. #include <asm/arch/reset_manager.h>
  21. #include <asm/arch/scan_manager.h>
  22. #include <asm/arch/system_manager.h>
  23. #include <asm/arch/nic301.h>
  24. #include <asm/arch/scu.h>
  25. #include <asm/pl310.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. phys_addr_t socfpga_clkmgr_base __section(".data");
  28. phys_addr_t socfpga_rstmgr_base __section(".data");
  29. phys_addr_t socfpga_sysmgr_base __section(".data");
  30. #ifdef CONFIG_SYS_L2_PL310
  31. static const struct pl310_regs *const pl310 =
  32. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  33. #endif
  34. struct bsel bsel_str[] = {
  35. { "rsvd", "Reserved", },
  36. { "fpga", "FPGA (HPS2FPGA Bridge)", },
  37. { "nand", "NAND Flash (1.8V)", },
  38. { "nand", "NAND Flash (3.0V)", },
  39. { "sd", "SD/MMC External Transceiver (1.8V)", },
  40. { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  41. { "qspi", "QSPI Flash (1.8V)", },
  42. { "qspi", "QSPI Flash (3.0V)", },
  43. };
  44. int dram_init(void)
  45. {
  46. if (fdtdec_setup_mem_size_base() != 0)
  47. return -EINVAL;
  48. return 0;
  49. }
  50. void enable_caches(void)
  51. {
  52. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  53. icache_enable();
  54. #endif
  55. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  56. dcache_enable();
  57. #endif
  58. }
  59. #ifdef CONFIG_SYS_L2_PL310
  60. void v7_outer_cache_enable(void)
  61. {
  62. struct udevice *dev;
  63. if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  64. pr_err("cache controller driver NOT found!\n");
  65. }
  66. void v7_outer_cache_disable(void)
  67. {
  68. /* Disable the L2 cache */
  69. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  70. }
  71. void socfpga_pl310_clear(void)
  72. {
  73. u32 mask = 0xff, ena = 0;
  74. icache_enable();
  75. /* Disable the L2 cache */
  76. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  77. writel(0x0, &pl310->pl310_tag_latency_ctrl);
  78. writel(0x10, &pl310->pl310_data_latency_ctrl);
  79. /* enable BRESP, instruction and data prefetch, full line of zeroes */
  80. setbits_le32(&pl310->pl310_aux_ctrl,
  81. L310_AUX_CTRL_DATA_PREFETCH_MASK |
  82. L310_AUX_CTRL_INST_PREFETCH_MASK |
  83. L310_SHARED_ATT_OVERRIDE_ENABLE);
  84. /* Enable the L2 cache */
  85. ena = readl(&pl310->pl310_ctrl);
  86. ena |= L2X0_CTRL_EN;
  87. /*
  88. * Invalidate the PL310 L2 cache. Keep the invalidation code
  89. * entirely in L1 I-cache to avoid any bus traffic through
  90. * the L2.
  91. */
  92. asm volatile(
  93. ".align 5 \n"
  94. " b 3f \n"
  95. "1: str %1, [%4] \n"
  96. " dsb \n"
  97. " isb \n"
  98. " str %0, [%2] \n"
  99. " dsb \n"
  100. " isb \n"
  101. "2: ldr %0, [%2] \n"
  102. " cmp %0, #0 \n"
  103. " bne 2b \n"
  104. " str %0, [%3] \n"
  105. " dsb \n"
  106. " isb \n"
  107. " b 4f \n"
  108. "3: b 1b \n"
  109. "4: nop \n"
  110. : "+r"(mask), "+r"(ena)
  111. : "r"(&pl310->pl310_inv_way),
  112. "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
  113. : "memory", "cc");
  114. /* Disable the L2 cache */
  115. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  116. }
  117. #endif
  118. #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  119. defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
  120. int overwrite_console(void)
  121. {
  122. return 0;
  123. }
  124. #endif
  125. #ifdef CONFIG_FPGA
  126. /* add device descriptor to FPGA device table */
  127. void socfpga_fpga_add(void *fpga_desc)
  128. {
  129. fpga_init();
  130. fpga_add(fpga_altera, fpga_desc);
  131. }
  132. #endif
  133. int arch_cpu_init(void)
  134. {
  135. socfpga_get_managers_addr();
  136. #ifdef CONFIG_HW_WATCHDOG
  137. /*
  138. * In case the watchdog is enabled, make sure to (re-)configure it
  139. * so that the defined timeout is valid. Otherwise the SPL (Perloader)
  140. * timeout value is still active which might too short for Linux
  141. * booting.
  142. */
  143. hw_watchdog_init();
  144. #else
  145. /*
  146. * If the HW watchdog is NOT enabled, make sure it is not running,
  147. * for example because it was enabled in the preloader. This might
  148. * trigger a watchdog-triggered reboot of Linux kernel later.
  149. * Toggle watchdog reset, so watchdog in not running state.
  150. */
  151. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  152. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  153. #endif
  154. return 0;
  155. }
  156. #ifndef CONFIG_SPL_BUILD
  157. static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
  158. char *const argv[])
  159. {
  160. unsigned int mask = ~0;
  161. if (argc < 2 || argc > 3)
  162. return CMD_RET_USAGE;
  163. argv++;
  164. if (argc == 3)
  165. mask = simple_strtoul(argv[1], NULL, 16);
  166. switch (*argv[0]) {
  167. case 'e': /* Enable */
  168. do_bridge_reset(1, mask);
  169. break;
  170. case 'd': /* Disable */
  171. do_bridge_reset(0, mask);
  172. break;
  173. default:
  174. return CMD_RET_USAGE;
  175. }
  176. return 0;
  177. }
  178. U_BOOT_CMD(bridge, 3, 1, do_bridge,
  179. "SoCFPGA HPS FPGA bridge control",
  180. "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  181. "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  182. ""
  183. );
  184. #endif
  185. static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
  186. {
  187. const void *blob = gd->fdt_blob;
  188. struct fdt_resource r;
  189. int node;
  190. int ret;
  191. node = fdt_node_offset_by_compatible(blob, -1, compat);
  192. if (node < 0)
  193. return node;
  194. if (!fdtdec_get_is_enabled(blob, node))
  195. return -ENODEV;
  196. ret = fdt_get_resource(blob, node, "reg", 0, &r);
  197. if (ret)
  198. return ret;
  199. *base = (phys_addr_t)r.start;
  200. return 0;
  201. }
  202. void socfpga_get_managers_addr(void)
  203. {
  204. int ret;
  205. ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
  206. if (ret)
  207. hang();
  208. ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
  209. if (ret)
  210. hang();
  211. #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
  212. ret = socfpga_get_base_addr("intel,agilex-clkmgr",
  213. &socfpga_clkmgr_base);
  214. #else
  215. ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
  216. #endif
  217. if (ret)
  218. hang();
  219. }
  220. phys_addr_t socfpga_get_rstmgr_addr(void)
  221. {
  222. return socfpga_rstmgr_base;
  223. }
  224. phys_addr_t socfpga_get_sysmgr_addr(void)
  225. {
  226. return socfpga_sysmgr_base;
  227. }
  228. phys_addr_t socfpga_get_clkmgr_addr(void)
  229. {
  230. return socfpga_clkmgr_base;
  231. }