rk3288.c 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <dm.h>
  8. #include <env.h>
  9. #include <clk.h>
  10. #include <init.h>
  11. #include <malloc.h>
  12. #include <asm/armv7.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/bootrom.h>
  15. #include <asm/arch-rockchip/clock.h>
  16. #include <asm/arch-rockchip/cru.h>
  17. #include <asm/arch-rockchip/hardware.h>
  18. #include <asm/arch-rockchip/grf_rk3288.h>
  19. #include <asm/arch-rockchip/pmu_rk3288.h>
  20. #include <asm/arch-rockchip/qos_rk3288.h>
  21. #include <asm/arch-rockchip/sdram.h>
  22. #include <linux/err.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define GRF_BASE 0xff770000
  25. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  26. [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
  27. [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
  28. };
  29. #ifdef CONFIG_SPL_BUILD
  30. static void configure_l2ctlr(void)
  31. {
  32. u32 l2ctlr;
  33. l2ctlr = read_l2ctlr();
  34. l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
  35. /*
  36. * Data RAM write latency: 2 cycles
  37. * Data RAM read latency: 2 cycles
  38. * Data RAM setup latency: 1 cycle
  39. * Tag RAM write latency: 1 cycle
  40. * Tag RAM read latency: 1 cycle
  41. * Tag RAM setup latency: 1 cycle
  42. */
  43. l2ctlr |= (1 << 3 | 1 << 0);
  44. write_l2ctlr(l2ctlr);
  45. }
  46. #endif
  47. int rk3288_qos_init(void)
  48. {
  49. int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
  50. /* set vop qos to higher priority */
  51. writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
  52. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
  53. if (!fdt_node_check_compatible(gd->fdt_blob, 0,
  54. "rockchip,rk3288-tinker")) {
  55. /* set isp qos to higher priority */
  56. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
  57. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
  58. writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
  59. }
  60. return 0;
  61. }
  62. int arch_cpu_init(void)
  63. {
  64. #ifdef CONFIG_SPL_BUILD
  65. configure_l2ctlr();
  66. #else
  67. /* We do some SoC one time setting here. */
  68. struct rk3288_grf * const grf = (void *)GRF_BASE;
  69. /* Use rkpwm by default */
  70. rk_setreg(&grf->soc_con2, 1 << 0);
  71. /*
  72. * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
  73. * cleared
  74. */
  75. rk_clrreg(&grf->soc_con0, 1 << 12);
  76. rk3288_qos_init();
  77. #endif
  78. return 0;
  79. }
  80. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  81. void board_debug_uart_init(void)
  82. {
  83. /* Enable early UART on the RK3288 */
  84. struct rk3288_grf * const grf = (void *)GRF_BASE;
  85. rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
  86. GPIO7C6_MASK << GPIO7C6_SHIFT,
  87. GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
  88. GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
  89. }
  90. #endif
  91. __weak int rk3288_board_late_init(void)
  92. {
  93. return 0;
  94. }
  95. int rk_board_late_init(void)
  96. {
  97. return rk3288_board_late_init();
  98. }
  99. static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc,
  100. char *const argv[])
  101. {
  102. static const struct {
  103. char *name;
  104. int id;
  105. } clks[] = {
  106. { "osc", CLK_OSC },
  107. { "apll", CLK_ARM },
  108. { "dpll", CLK_DDR },
  109. { "cpll", CLK_CODEC },
  110. { "gpll", CLK_GENERAL },
  111. #ifdef CONFIG_ROCKCHIP_RK3036
  112. { "mpll", CLK_NEW },
  113. #else
  114. { "npll", CLK_NEW },
  115. #endif
  116. };
  117. int ret, i;
  118. struct udevice *dev;
  119. ret = rockchip_get_clk(&dev);
  120. if (ret) {
  121. printf("clk-uclass not found\n");
  122. return 0;
  123. }
  124. for (i = 0; i < ARRAY_SIZE(clks); i++) {
  125. struct clk clk;
  126. ulong rate;
  127. clk.id = clks[i].id;
  128. ret = clk_request(dev, &clk);
  129. if (ret < 0)
  130. continue;
  131. rate = clk_get_rate(&clk);
  132. printf("%s: %lu\n", clks[i].name, rate);
  133. clk_free(&clk);
  134. }
  135. return 0;
  136. }
  137. U_BOOT_CMD(
  138. clock, 2, 1, do_clock,
  139. "display information about clocks",
  140. ""
  141. );