board.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Common board functions for OMAP3 based boards.
  5. *
  6. * (C) Copyright 2004-2008
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Author :
  10. * Sunil Kumar <sunilsaini05@gmail.com>
  11. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  12. *
  13. * Derived from Beagle Board and 3430 SDP code by
  14. * Richard Woodruff <r-woodruff2@ti.com>
  15. * Syed Mohammed Khasim <khasim@ti.com>
  16. *
  17. */
  18. #include <common.h>
  19. #include <command.h>
  20. #include <dm.h>
  21. #include <init.h>
  22. #include <spl.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/arch/mem.h>
  26. #include <asm/cache.h>
  27. #include <asm/armv7.h>
  28. #include <asm/gpio.h>
  29. #include <asm/omap_common.h>
  30. #include <linux/compiler.h>
  31. /* Declarations */
  32. extern omap3_sysinfo sysinfo;
  33. #ifndef CONFIG_SYS_L2CACHE_OFF
  34. static void omap3_invalidate_l2_cache_secure(void);
  35. #endif
  36. #if CONFIG_IS_ENABLED(DM_GPIO)
  37. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  38. /* Manually initialize GPIO banks when OF_CONTROL doesn't */
  39. static const struct omap_gpio_platdata omap34xx_gpio[] = {
  40. { 0, OMAP34XX_GPIO1_BASE },
  41. { 1, OMAP34XX_GPIO2_BASE },
  42. { 2, OMAP34XX_GPIO3_BASE },
  43. { 3, OMAP34XX_GPIO4_BASE },
  44. { 4, OMAP34XX_GPIO5_BASE },
  45. { 5, OMAP34XX_GPIO6_BASE },
  46. };
  47. U_BOOT_DEVICES(omap34xx_gpios) = {
  48. { "gpio_omap", &omap34xx_gpio[0] },
  49. { "gpio_omap", &omap34xx_gpio[1] },
  50. { "gpio_omap", &omap34xx_gpio[2] },
  51. { "gpio_omap", &omap34xx_gpio[3] },
  52. { "gpio_omap", &omap34xx_gpio[4] },
  53. { "gpio_omap", &omap34xx_gpio[5] },
  54. };
  55. #endif
  56. #else
  57. static const struct gpio_bank gpio_bank_34xx[6] = {
  58. { (void *)OMAP34XX_GPIO1_BASE },
  59. { (void *)OMAP34XX_GPIO2_BASE },
  60. { (void *)OMAP34XX_GPIO3_BASE },
  61. { (void *)OMAP34XX_GPIO4_BASE },
  62. { (void *)OMAP34XX_GPIO5_BASE },
  63. { (void *)OMAP34XX_GPIO6_BASE },
  64. };
  65. const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
  66. #endif
  67. /******************************************************************************
  68. * Routine: secure_unlock
  69. * Description: Setup security registers for access
  70. * (GP Device only)
  71. *****************************************************************************/
  72. void secure_unlock_mem(void)
  73. {
  74. struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
  75. struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
  76. struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
  77. struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
  78. struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
  79. /* Protection Module Register Target APE (PM_RT) */
  80. writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
  81. writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
  82. writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
  83. writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
  84. writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
  85. writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
  86. writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
  87. writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
  88. writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
  89. writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
  90. writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
  91. /* IVA Changes */
  92. writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
  93. writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
  94. writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
  95. /* SDRC region 0 public */
  96. writel(UNLOCK_1, &sms_base->rg_att0);
  97. }
  98. /******************************************************************************
  99. * Routine: secureworld_exit()
  100. * Description: If chip is EMU and boot type is external
  101. * configure secure registers and exit secure world
  102. * general use.
  103. *****************************************************************************/
  104. void secureworld_exit(void)
  105. {
  106. unsigned long i;
  107. /* configure non-secure access control register */
  108. __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
  109. /* enabling co-processor CP10 and CP11 accesses in NS world */
  110. __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
  111. /*
  112. * allow allocation of locked TLBs and L2 lines in NS world
  113. * allow use of PLE registers in NS world also
  114. */
  115. __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
  116. __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
  117. /* Enable ASA in ACR register */
  118. __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
  119. __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
  120. __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
  121. /* Exiting secure world */
  122. __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
  123. __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
  124. __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
  125. }
  126. /******************************************************************************
  127. * Routine: try_unlock_sram()
  128. * Description: If chip is GP/EMU(special) type, unlock the SRAM for
  129. * general use.
  130. *****************************************************************************/
  131. void try_unlock_memory(void)
  132. {
  133. int mode;
  134. int in_sdram = is_running_in_sdram();
  135. /*
  136. * if GP device unlock device SRAM for general use
  137. * secure code breaks for Secure/Emulation device - HS/E/T
  138. */
  139. mode = get_device_type();
  140. if (mode == GP_DEVICE)
  141. secure_unlock_mem();
  142. /*
  143. * If device is EMU and boot is XIP external booting
  144. * Unlock firewalls and disable L2 and put chip
  145. * out of secure world
  146. *
  147. * Assuming memories are unlocked by the demon who put us in SDRAM
  148. */
  149. if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
  150. && (!in_sdram)) {
  151. secure_unlock_mem();
  152. secureworld_exit();
  153. }
  154. return;
  155. }
  156. void early_system_init(void)
  157. {
  158. hw_data_init();
  159. }
  160. /******************************************************************************
  161. * Routine: s_init
  162. * Description: Does early system init of muxing and clocks.
  163. * - Called path is with SRAM stack.
  164. *****************************************************************************/
  165. void s_init(void)
  166. {
  167. watchdog_init();
  168. early_system_init();
  169. try_unlock_memory();
  170. #ifndef CONFIG_SYS_L2CACHE_OFF
  171. /* Invalidate L2-cache from secure mode */
  172. omap3_invalidate_l2_cache_secure();
  173. #endif
  174. set_muxconf_regs();
  175. sdelay(100);
  176. prcm_init();
  177. per_clocks_enable();
  178. #ifdef CONFIG_USB_EHCI_OMAP
  179. ehci_clocks_enable();
  180. #endif
  181. }
  182. #ifdef CONFIG_SPL_BUILD
  183. void board_init_f(ulong dummy)
  184. {
  185. early_system_init();
  186. mem_init();
  187. /*
  188. * Save the boot parameters passed from romcode.
  189. * We cannot delay the saving further than this,
  190. * to prevent overwrites.
  191. */
  192. save_omap_boot_params();
  193. }
  194. #endif
  195. /*
  196. * Routine: misc_init_r
  197. * Description: A basic misc_init_r that just displays the die ID
  198. */
  199. int __weak misc_init_r(void)
  200. {
  201. omap_die_id_display();
  202. return 0;
  203. }
  204. /******************************************************************************
  205. * Routine: wait_for_command_complete
  206. * Description: Wait for posting to finish on watchdog
  207. *****************************************************************************/
  208. static void wait_for_command_complete(struct watchdog *wd_base)
  209. {
  210. int pending = 1;
  211. do {
  212. pending = readl(&wd_base->wwps);
  213. } while (pending);
  214. }
  215. /******************************************************************************
  216. * Routine: watchdog_init
  217. * Description: Shut down watch dogs
  218. *****************************************************************************/
  219. void watchdog_init(void)
  220. {
  221. struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
  222. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  223. /*
  224. * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
  225. * either taken care of by ROM (HS/EMU) or not accessible (GP).
  226. * We need to take care of WD2-MPU or take a PRCM reset. WD3
  227. * should not be running and does not generate a PRCM reset.
  228. */
  229. setbits_le32(&prcm_base->fclken_wkup, 0x20);
  230. setbits_le32(&prcm_base->iclken_wkup, 0x20);
  231. wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
  232. writel(WD_UNLOCK1, &wd2_base->wspr);
  233. wait_for_command_complete(wd2_base);
  234. writel(WD_UNLOCK2, &wd2_base->wspr);
  235. }
  236. /******************************************************************************
  237. * Dummy function to handle errors for EABI incompatibility
  238. *****************************************************************************/
  239. void abort(void)
  240. {
  241. }
  242. #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
  243. /******************************************************************************
  244. * OMAP3 specific command to switch between NAND HW and SW ecc
  245. *****************************************************************************/
  246. static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
  247. char *const argv[])
  248. {
  249. int hw, strength = 1;
  250. if (argc < 2 || argc > 3)
  251. goto usage;
  252. if (strncmp(argv[1], "hw", 2) == 0) {
  253. hw = 1;
  254. if (argc == 3) {
  255. if (strncmp(argv[2], "bch8", 4) == 0)
  256. strength = 8;
  257. else if (strncmp(argv[2], "bch16", 5) == 0)
  258. strength = 16;
  259. else if (strncmp(argv[2], "hamming", 7) != 0)
  260. goto usage;
  261. }
  262. } else if (strncmp(argv[1], "sw", 2) == 0) {
  263. hw = 0;
  264. if (argc == 3) {
  265. if (strncmp(argv[2], "bch8", 4) == 0)
  266. strength = 8;
  267. else if (strncmp(argv[2], "hamming", 7) != 0)
  268. goto usage;
  269. }
  270. } else {
  271. goto usage;
  272. }
  273. return -omap_nand_switch_ecc(hw, strength);
  274. usage:
  275. printf ("Usage: nandecc %s\n", cmdtp->usage);
  276. return 1;
  277. }
  278. U_BOOT_CMD(
  279. nandecc, 3, 1, do_switch_ecc,
  280. "switch OMAP3 NAND ECC calculation algorithm",
  281. "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
  282. " and 8-bit/16-bit BCH\n"
  283. " ecc calculation (second parameter may"
  284. " be omitted).\n"
  285. "nandecc sw - Switch to NAND software ecc algorithm."
  286. );
  287. #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
  288. #ifdef CONFIG_DISPLAY_BOARDINFO
  289. /**
  290. * Print board information
  291. */
  292. int checkboard (void)
  293. {
  294. char *mem_s ;
  295. if (is_mem_sdr())
  296. mem_s = "mSDR";
  297. else
  298. mem_s = "LPDDR";
  299. printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
  300. sysinfo.nand_string);
  301. return 0;
  302. }
  303. #endif /* CONFIG_DISPLAY_BOARDINFO */
  304. static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
  305. {
  306. u32 i, num_params = *parameters;
  307. u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
  308. /*
  309. * copy the parameters to an un-cached area to avoid coherency
  310. * issues
  311. */
  312. for (i = 0; i < num_params; i++) {
  313. __raw_writel(*parameters, sram_scratch_space);
  314. parameters++;
  315. sram_scratch_space++;
  316. }
  317. /* Now make the PPA call */
  318. do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
  319. }
  320. void __weak omap3_set_aux_cr_secure(u32 acr)
  321. {
  322. struct emu_hal_params emu_romcode_params;
  323. emu_romcode_params.num_params = 1;
  324. emu_romcode_params.param1 = acr;
  325. omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
  326. (u32 *)&emu_romcode_params);
  327. }
  328. void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
  329. u32 cpu_rev_comb, u32 cpu_variant,
  330. u32 cpu_rev)
  331. {
  332. if (get_device_type() == GP_DEVICE)
  333. omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
  334. /* L2 Cache Auxiliary Control Register is not banked */
  335. }
  336. void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
  337. u32 cpu_variant, u32 cpu_rev)
  338. {
  339. /* Write ACR - affects secure banked bits */
  340. if (get_device_type() == GP_DEVICE)
  341. omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
  342. else
  343. omap3_set_aux_cr_secure(acr);
  344. /* Write ACR - affects non-secure banked bits - some erratas need it */
  345. asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
  346. }
  347. #ifndef CONFIG_SYS_L2CACHE_OFF
  348. static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
  349. {
  350. u32 acr;
  351. /* Read ACR */
  352. asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
  353. acr &= ~clear_bits;
  354. acr |= set_bits;
  355. v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
  356. }
  357. /* Invalidate the entire L2 cache from secure mode */
  358. static void omap3_invalidate_l2_cache_secure(void)
  359. {
  360. if (get_device_type() == GP_DEVICE) {
  361. omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
  362. } else {
  363. struct emu_hal_params emu_romcode_params;
  364. emu_romcode_params.num_params = 1;
  365. emu_romcode_params.param1 = 0;
  366. omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
  367. (u32 *)&emu_romcode_params);
  368. }
  369. }
  370. void v7_outer_cache_enable(void)
  371. {
  372. /*
  373. * Set L2EN
  374. * On some revisions L2EN bit is banked on some revisions it's not
  375. * No harm in setting both banked bits(in fact this is required
  376. * by an erratum)
  377. */
  378. omap3_update_aux_cr(0x2, 0);
  379. }
  380. void omap3_outer_cache_disable(void)
  381. {
  382. /*
  383. * Clear L2EN
  384. * On some revisions L2EN bit is banked on some revisions it's not
  385. * No harm in clearing both banked bits(in fact this is required
  386. * by an erratum)
  387. */
  388. omap3_update_aux_cr(0, 0x2);
  389. }
  390. #endif /* !CONFIG_SYS_L2CACHE_OFF */