ddr3.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Keystone2: DDR3 initialization
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <asm/io.h>
  11. #include <common.h>
  12. #include <asm/arch/msmc.h>
  13. #include <asm/arch/ddr3.h>
  14. #include <asm/arch/psc_defs.h>
  15. #include <asm/ti-common/ti-edma3.h>
  16. #define DDR3_EDMA_BLK_SIZE_SHIFT 10
  17. #define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
  18. #define DDR3_EDMA_BCNT 0x8000
  19. #define DDR3_EDMA_CCNT 1
  20. #define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
  21. #define DDR3_EDMA_SLOT_NUM 1
  22. void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
  23. {
  24. unsigned int tmp;
  25. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
  26. & 0x00000001) != 0x00000001)
  27. ;
  28. __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
  29. tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
  30. tmp &= ~(phy_cfg->pgcr1_mask);
  31. tmp |= phy_cfg->pgcr1_val;
  32. __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
  33. __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
  34. __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
  35. __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
  36. __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
  37. tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
  38. tmp &= ~(phy_cfg->dcr_mask);
  39. tmp |= phy_cfg->dcr_val;
  40. __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
  41. __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
  42. __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
  43. __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
  44. __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
  45. __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
  46. __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
  47. __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
  48. __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
  49. __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
  50. __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
  51. __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
  52. __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
  53. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  54. ;
  55. if (cpu_is_k2g()) {
  56. clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
  57. phy_cfg->datx8_2_mask,
  58. phy_cfg->datx8_2_val);
  59. clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
  60. phy_cfg->datx8_3_mask,
  61. phy_cfg->datx8_3_val);
  62. clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
  63. phy_cfg->datx8_4_mask,
  64. phy_cfg->datx8_4_val);
  65. clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
  66. phy_cfg->datx8_5_mask,
  67. phy_cfg->datx8_5_val);
  68. clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
  69. phy_cfg->datx8_6_mask,
  70. phy_cfg->datx8_6_val);
  71. clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
  72. phy_cfg->datx8_7_mask,
  73. phy_cfg->datx8_7_val);
  74. clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
  75. phy_cfg->datx8_8_mask,
  76. phy_cfg->datx8_8_val);
  77. }
  78. __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
  79. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  80. ;
  81. }
  82. void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
  83. {
  84. __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
  85. __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
  86. __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
  87. __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
  88. __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
  89. __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
  90. __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
  91. }
  92. int ddr3_ecc_support_rmw(u32 base)
  93. {
  94. u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
  95. /* Check the DDR3 controller ID reg if the controllers
  96. supports ECC RMW or not */
  97. if (value == 0x40461C02)
  98. return 1;
  99. return 0;
  100. }
  101. static void ddr3_ecc_config(u32 base, u32 value)
  102. {
  103. u32 data;
  104. __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
  105. udelay(100000); /* delay required to synchronize across clock domains */
  106. if (value & KS2_DDR3_ECC_EN) {
  107. /* Clear the 1-bit error count */
  108. data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  109. __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  110. /* enable the ECC interrupt */
  111. __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
  112. KS2_DDR3_WR_ECC_ERR_SYS,
  113. base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
  114. /* Clear the ECC error interrupt status */
  115. __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
  116. KS2_DDR3_WR_ECC_ERR_SYS,
  117. base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
  118. }
  119. }
  120. static void ddr3_reset_data(u32 base, u32 ddr3_size)
  121. {
  122. u32 mpax[2];
  123. u32 seg_num;
  124. u32 seg, blks, dst, edma_blks;
  125. struct edma3_slot_config slot;
  126. struct edma3_channel_config edma_channel;
  127. u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
  128. /* Setup an edma to copy the 1k block to the entire DDR */
  129. puts("\nClear entire DDR3 memory to enable ECC\n");
  130. /* save the SES MPAX regs */
  131. if (cpu_is_k2g())
  132. msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
  133. else
  134. msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
  135. /* setup edma slot 1 configuration */
  136. slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
  137. EDMA3_SLOPT_COMP_CODE(0) |
  138. EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
  139. slot.bcnt = DDR3_EDMA_BCNT;
  140. slot.acnt = DDR3_EDMA_BLK_SIZE;
  141. slot.ccnt = DDR3_EDMA_CCNT;
  142. slot.src_bidx = 0;
  143. slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
  144. slot.src_cidx = 0;
  145. slot.dst_cidx = 0;
  146. slot.link = EDMA3_PARSET_NULL_LINK;
  147. slot.bcntrld = 0;
  148. edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
  149. /* configure quik edma channel */
  150. edma_channel.slot = DDR3_EDMA_SLOT_NUM;
  151. edma_channel.chnum = 0;
  152. edma_channel.complete_code = 0;
  153. /* event trigger after dst update */
  154. edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
  155. qedma3_start(KS2_EDMA0_BASE, &edma_channel);
  156. /* DDR3 size in segments (4KB seg size) */
  157. seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
  158. for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
  159. /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
  160. access slave interface so that edma driver can access */
  161. if (cpu_is_k2g()) {
  162. msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
  163. base >> KS2_MSMC_SEG_SIZE_SHIFT,
  164. KS2_MSMC_DST_SEG_BASE + seg,
  165. MPAX_SEG_2G);
  166. } else {
  167. msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
  168. base >> KS2_MSMC_SEG_SIZE_SHIFT,
  169. KS2_MSMC_DST_SEG_BASE + seg,
  170. MPAX_SEG_2G);
  171. }
  172. if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
  173. edma_blks = KS2_MSMC_MAP_SEG_NUM <<
  174. (KS2_MSMC_SEG_SIZE_SHIFT
  175. - DDR3_EDMA_BLK_SIZE_SHIFT);
  176. else
  177. edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
  178. - DDR3_EDMA_BLK_SIZE_SHIFT);
  179. /* Use edma driver to scrub 2GB DDR memory */
  180. for (dst = base, blks = 0; blks < edma_blks;
  181. blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
  182. edma3_set_src_addr(KS2_EDMA0_BASE,
  183. edma_channel.slot, (u32)edma_src);
  184. edma3_set_dest_addr(KS2_EDMA0_BASE,
  185. edma_channel.slot, (u32)dst);
  186. while (edma3_check_for_transfer(KS2_EDMA0_BASE,
  187. &edma_channel))
  188. udelay(10);
  189. }
  190. }
  191. qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
  192. /* restore the SES MPAX regs */
  193. if (cpu_is_k2g())
  194. msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
  195. else
  196. msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
  197. }
  198. static void ddr3_ecc_init_range(u32 base)
  199. {
  200. u32 ecc_val = KS2_DDR3_ECC_EN;
  201. u32 rmw = ddr3_ecc_support_rmw(base);
  202. if (rmw)
  203. ecc_val |= KS2_DDR3_ECC_RMW_EN;
  204. __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
  205. ddr3_ecc_config(base, ecc_val);
  206. }
  207. void ddr3_enable_ecc(u32 base, int test)
  208. {
  209. u32 ecc_val = KS2_DDR3_ECC_ENABLE;
  210. u32 rmw = ddr3_ecc_support_rmw(base);
  211. if (test)
  212. ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
  213. if (!rmw) {
  214. if (!test)
  215. /* by default, disable ecc when rmw = 0 and no
  216. ecc test */
  217. ecc_val = 0;
  218. } else {
  219. ecc_val |= KS2_DDR3_ECC_RMW_EN;
  220. }
  221. ddr3_ecc_config(base, ecc_val);
  222. }
  223. void ddr3_disable_ecc(u32 base)
  224. {
  225. ddr3_ecc_config(base, 0);
  226. }
  227. #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
  228. static void cic_init(u32 base)
  229. {
  230. /* Disable CIC global interrupts */
  231. __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
  232. /* Set to normal mode, no nesting, no priority hold */
  233. __raw_writel(0, base + KS2_CIC_CTRL);
  234. __raw_writel(0, base + KS2_CIC_HOST_CTRL);
  235. /* Enable CIC global interrupts */
  236. __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
  237. }
  238. static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
  239. {
  240. /* Map the system interrupt to a CIC channel */
  241. __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
  242. /* Enable CIC system interrupt */
  243. __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
  244. /* Enable CIC Host interrupt */
  245. __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
  246. }
  247. static void ddr3_map_ecc_cic2_irq(u32 base)
  248. {
  249. cic_init(base);
  250. cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
  251. KS2_CIC2_DDR3_ECC_IRQ_NUM);
  252. }
  253. #endif
  254. void ddr3_init_ecc(u32 base, u32 ddr3_size)
  255. {
  256. if (!ddr3_ecc_support_rmw(base)) {
  257. ddr3_disable_ecc(base);
  258. return;
  259. }
  260. ddr3_ecc_init_range(base);
  261. ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
  262. /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
  263. #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
  264. ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
  265. #endif
  266. ddr3_enable_ecc(base, 0);
  267. }
  268. void ddr3_check_ecc_int(u32 base)
  269. {
  270. char *env;
  271. int ecc_test = 0;
  272. u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
  273. env = env_get("ecc_test");
  274. if (env)
  275. ecc_test = simple_strtol(env, NULL, 0);
  276. if (value & KS2_DDR3_WR_ECC_ERR_SYS)
  277. puts("DDR3 ECC write error interrupted\n");
  278. if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
  279. puts("DDR3 ECC 2-bit error interrupted\n");
  280. if (!ecc_test) {
  281. puts("Reseting the device ...\n");
  282. reset_cpu(0);
  283. }
  284. }
  285. value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  286. if (value) {
  287. printf("1-bit ECC err count: 0x%x\n", value);
  288. value = __raw_readl(base +
  289. KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
  290. printf("1-bit ECC err address log: 0x%x\n", value);
  291. }
  292. }
  293. void ddr3_reset_ddrphy(void)
  294. {
  295. u32 tmp;
  296. /* Assert DDR3A PHY reset */
  297. tmp = readl(KS2_DDR3APLLCTL1);
  298. tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
  299. writel(tmp, KS2_DDR3APLLCTL1);
  300. /* wait 10us to catch the reset */
  301. udelay(10);
  302. /* Release DDR3A PHY reset */
  303. tmp = readl(KS2_DDR3APLLCTL1);
  304. tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
  305. __raw_writel(tmp, KS2_DDR3APLLCTL1);
  306. }
  307. #ifdef CONFIG_SOC_K2HK
  308. /**
  309. * ddr3_reset_workaround - reset workaround in case if leveling error
  310. * detected for PG 1.0 and 1.1 k2hk SoCs
  311. */
  312. void ddr3_err_reset_workaround(void)
  313. {
  314. unsigned int tmp;
  315. unsigned int tmp_a;
  316. unsigned int tmp_b;
  317. /*
  318. * Check for PGSR0 error bits of DDR3 PHY.
  319. * Check for WLERR, QSGERR, WLAERR,
  320. * RDERR, WDERR, REERR, WEERR error to see if they are set or not
  321. */
  322. tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
  323. tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
  324. if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
  325. printf("DDR Leveling Error Detected!\n");
  326. printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
  327. printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
  328. /*
  329. * Write Keys to KICK registers to enable writes to registers
  330. * in boot config space
  331. */
  332. __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  333. __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  334. /*
  335. * Move DDR3A Module out of reset isolation by setting
  336. * MDCTL23[12] = 0
  337. */
  338. tmp_a = __raw_readl(KS2_PSC_BASE +
  339. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
  340. tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
  341. __raw_writel(tmp_a, KS2_PSC_BASE +
  342. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
  343. /*
  344. * Move DDR3B Module out of reset isolation by setting
  345. * MDCTL24[12] = 0
  346. */
  347. tmp_b = __raw_readl(KS2_PSC_BASE +
  348. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
  349. tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
  350. __raw_writel(tmp_b, KS2_PSC_BASE +
  351. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
  352. /*
  353. * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
  354. * to RSTCTRL and RSTCFG
  355. */
  356. tmp = __raw_readl(KS2_RSTCTRL);
  357. tmp &= KS2_RSTCTRL_MASK;
  358. tmp |= KS2_RSTCTRL_KEY;
  359. __raw_writel(tmp, KS2_RSTCTRL);
  360. /*
  361. * Set PLL Controller to drive hard reset on SW trigger by
  362. * setting RSTCFG[13] = 0
  363. */
  364. tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
  365. tmp &= ~KS2_RSTYPE_PLL_SOFT;
  366. __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
  367. reset_cpu(0);
  368. }
  369. }
  370. #endif