soc.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/mach-imx/boot_mode.h>
  13. #include <asm/mach-imx/hab.h>
  14. #define PMC0_BASE_ADDR 0x410a1000
  15. #define PMC0_CTRL 0x28
  16. #define PMC0_CTRL_LDOEN BIT(31)
  17. #define PMC0_CTRL_LDOOKDIS BIT(30)
  18. #define PMC0_CTRL_PMC1ON BIT(24)
  19. #define PMC1_BASE_ADDR 0x40400000
  20. #define PMC1_RUN 0x8
  21. #define PMC1_STOP 0x10
  22. #define PMC1_VLPS 0x14
  23. #define PMC1_LDOVL_SHIFT 16
  24. #define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
  25. #define PMC1_LDOVL_900 0x1e
  26. #define PMC1_LDOVL_950 0x23
  27. #define PMC1_STATUS 0x20
  28. #define PMC1_STATUS_LDOVLF BIT(8)
  29. static char *get_reset_cause(char *);
  30. #if defined(CONFIG_IMX_HAB)
  31. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  32. .bank = 29,
  33. .word = 6,
  34. };
  35. #endif
  36. #define ROM_VERSION_ADDR 0x80
  37. u32 get_cpu_rev(void)
  38. {
  39. /* Check the ROM version for cpu revision */
  40. u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
  41. return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
  42. }
  43. #ifdef CONFIG_REVISION_TAG
  44. u32 __weak get_board_rev(void)
  45. {
  46. return get_cpu_rev();
  47. }
  48. #endif
  49. enum bt_mode get_boot_mode(void)
  50. {
  51. u32 bt0_cfg = 0;
  52. bt0_cfg = readl(CMC0_RBASE + 0x40);
  53. bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
  54. if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
  55. /* No low power boot */
  56. if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
  57. return DUAL_BOOT;
  58. else
  59. return SINGLE_BOOT;
  60. }
  61. return LOW_POWER_BOOT;
  62. }
  63. int arch_cpu_init(void)
  64. {
  65. return 0;
  66. }
  67. #ifdef CONFIG_BOARD_POSTCLK_INIT
  68. int board_postclk_init(void)
  69. {
  70. return 0;
  71. }
  72. #endif
  73. #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
  74. #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
  75. #define REFRESH_WORD0 0xA602 /* 1st refresh word */
  76. #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
  77. static void disable_wdog(u32 wdog_base)
  78. {
  79. writel(UNLOCK_WORD0, (wdog_base + 0x04));
  80. writel(UNLOCK_WORD1, (wdog_base + 0x04));
  81. writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
  82. writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
  83. writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
  84. writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
  85. writel(REFRESH_WORD1, (wdog_base + 0x04));
  86. }
  87. void init_wdog(void)
  88. {
  89. /*
  90. * ROM will configure WDOG1, disable it or enable it
  91. * depending on FUSE. The update bit is set for reconfigurable.
  92. * We have to use unlock sequence to reconfigure it.
  93. * WDOG2 is not touched by ROM, so it will have default value
  94. * which is enabled. We can directly configure it.
  95. * To simplify the codes, we still use same reconfigure
  96. * process as WDOG1. Because the update bit is not set for
  97. * WDOG2, the unlock sequence won't take effect really.
  98. * It actually directly configure the wdog.
  99. * In this function, we will disable both WDOG1 and WDOG2,
  100. * and set update bit for both. So that kernel can reconfigure them.
  101. */
  102. disable_wdog(WDG1_RBASE);
  103. disable_wdog(WDG2_RBASE);
  104. }
  105. static bool ldo_mode_is_enabled(void)
  106. {
  107. unsigned int reg;
  108. reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
  109. if (reg & PMC0_CTRL_LDOEN)
  110. return true;
  111. else
  112. return false;
  113. }
  114. #if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
  115. #if defined(CONFIG_LDO_ENABLED_MODE)
  116. static void init_ldo_mode(void)
  117. {
  118. unsigned int reg;
  119. if (ldo_mode_is_enabled())
  120. return;
  121. /* Set LDOOKDIS */
  122. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
  123. /* Set LDOVL to 0.95V in PMC1_RUN */
  124. reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
  125. reg &= ~PMC1_LDOVL_MASK;
  126. reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
  127. writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
  128. /* Wait for LDOVLF to be cleared */
  129. reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
  130. while (reg & PMC1_STATUS_LDOVLF)
  131. ;
  132. /* Set LDOVL to 0.95V in PMC1_STOP */
  133. reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
  134. reg &= ~PMC1_LDOVL_MASK;
  135. reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
  136. writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
  137. /* Set LDOVL to 0.90V in PMC1_VLPS */
  138. reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
  139. reg &= ~PMC1_LDOVL_MASK;
  140. reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
  141. writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
  142. /* Set LDOEN bit */
  143. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
  144. /* Set the PMC1ON bit */
  145. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
  146. }
  147. #endif
  148. void s_init(void)
  149. {
  150. /* Disable wdog */
  151. init_wdog();
  152. /* clock configuration. */
  153. clock_init();
  154. if (soc_rev() < CHIP_REV_2_0) {
  155. /* enable dumb pmic */
  156. writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
  157. }
  158. #if defined(CONFIG_LDO_ENABLED_MODE)
  159. init_ldo_mode();
  160. #endif
  161. return;
  162. }
  163. #endif
  164. #ifndef CONFIG_ULP_WATCHDOG
  165. void reset_cpu(ulong addr)
  166. {
  167. setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
  168. while (1)
  169. ;
  170. }
  171. #endif
  172. #if defined(CONFIG_DISPLAY_CPUINFO)
  173. const char *get_imx_type(u32 imxtype)
  174. {
  175. return "7ULP";
  176. }
  177. int print_cpuinfo(void)
  178. {
  179. u32 cpurev;
  180. char cause[18];
  181. cpurev = get_cpu_rev();
  182. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  183. get_imx_type((cpurev & 0xFF000) >> 12),
  184. (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
  185. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  186. printf("Reset cause: %s\n", get_reset_cause(cause));
  187. printf("Boot mode: ");
  188. switch (get_boot_mode()) {
  189. case LOW_POWER_BOOT:
  190. printf("Low power boot\n");
  191. break;
  192. case DUAL_BOOT:
  193. printf("Dual boot\n");
  194. break;
  195. case SINGLE_BOOT:
  196. default:
  197. printf("Single boot\n");
  198. break;
  199. }
  200. if (ldo_mode_is_enabled())
  201. printf("PMC1: LDO enabled mode\n");
  202. else
  203. printf("PMC1: LDO bypass mode\n");
  204. return 0;
  205. }
  206. #endif
  207. #define CMC_SRS_TAMPER (1 << 31)
  208. #define CMC_SRS_SECURITY (1 << 30)
  209. #define CMC_SRS_TZWDG (1 << 29)
  210. #define CMC_SRS_JTAG_RST (1 << 28)
  211. #define CMC_SRS_CORE1 (1 << 16)
  212. #define CMC_SRS_LOCKUP (1 << 15)
  213. #define CMC_SRS_SW (1 << 14)
  214. #define CMC_SRS_WDG (1 << 13)
  215. #define CMC_SRS_PIN_RESET (1 << 8)
  216. #define CMC_SRS_WARM (1 << 4)
  217. #define CMC_SRS_HVD (1 << 3)
  218. #define CMC_SRS_LVD (1 << 2)
  219. #define CMC_SRS_POR (1 << 1)
  220. #define CMC_SRS_WUP (1 << 0)
  221. static u32 reset_cause = -1;
  222. static char *get_reset_cause(char *ret)
  223. {
  224. u32 cause1, cause = 0, srs = 0;
  225. u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
  226. u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
  227. if (!ret)
  228. return "null";
  229. srs = readl(reg_srs);
  230. cause1 = readl(reg_ssrs);
  231. writel(cause1, reg_ssrs);
  232. reset_cause = cause1;
  233. cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
  234. switch (cause) {
  235. case CMC_SRS_POR:
  236. sprintf(ret, "%s", "POR");
  237. break;
  238. case CMC_SRS_WUP:
  239. sprintf(ret, "%s", "WUP");
  240. break;
  241. case CMC_SRS_WARM:
  242. cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
  243. CMC_SRS_JTAG_RST);
  244. switch (cause) {
  245. case CMC_SRS_WDG:
  246. sprintf(ret, "%s", "WARM-WDG");
  247. break;
  248. case CMC_SRS_SW:
  249. sprintf(ret, "%s", "WARM-SW");
  250. break;
  251. case CMC_SRS_JTAG_RST:
  252. sprintf(ret, "%s", "WARM-JTAG");
  253. break;
  254. default:
  255. sprintf(ret, "%s", "WARM-UNKN");
  256. break;
  257. }
  258. break;
  259. default:
  260. sprintf(ret, "%s-%X", "UNKN", cause1);
  261. break;
  262. }
  263. debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
  264. return ret;
  265. }
  266. #ifdef CONFIG_ENV_IS_IN_MMC
  267. __weak int board_mmc_get_env_dev(int devno)
  268. {
  269. return CONFIG_SYS_MMC_ENV_DEV;
  270. }
  271. int mmc_get_env_dev(void)
  272. {
  273. int devno = 0;
  274. u32 bt1_cfg = 0;
  275. /* If not boot from sd/mmc, use default value */
  276. if (get_boot_mode() == LOW_POWER_BOOT)
  277. return CONFIG_SYS_MMC_ENV_DEV;
  278. bt1_cfg = readl(CMC1_RBASE + 0x40);
  279. devno = (bt1_cfg >> 9) & 0x7;
  280. return board_mmc_get_env_dev(devno);
  281. }
  282. #endif
  283. enum boot_device get_boot_device(void)
  284. {
  285. struct bootrom_sw_info **p =
  286. (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
  287. enum boot_device boot_dev = SD1_BOOT;
  288. u8 boot_type = (*p)->boot_dev_type;
  289. u8 boot_instance = (*p)->boot_dev_instance;
  290. switch (boot_type) {
  291. case BOOT_TYPE_SD:
  292. boot_dev = boot_instance + SD1_BOOT;
  293. break;
  294. case BOOT_TYPE_MMC:
  295. boot_dev = boot_instance + MMC1_BOOT;
  296. break;
  297. case BOOT_TYPE_USB:
  298. boot_dev = USB_BOOT;
  299. break;
  300. default:
  301. break;
  302. }
  303. return boot_dev;
  304. }